MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
Quad 3-State D Flip-Flop with
Common Clock and Reset
HighPerformance SiliconGate CMOS
The MC74HC173 is identical in pinout to the LS173. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
Data, when enabled, are clocked into the four D flipflops with the rising
edge of the common Clock. When either or both of the Output Enable
Controls is high, the outputs are in a highimpedance state. This feature
allows the HC173 to be used in busoriented systems. The Reset feature is
asynchronous and active high.
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity 208 FETs or 52 Equivalent Gates
FUNCTION TABLE
Inputs
Output
Output Enables
Reset
Clock
Data Enables
Data
D
OE1
OE2
Reset
Clock
DE1
DE2
Data
D
Q
L
L
H
X
X
X
X
L
L
L
L
L
X
X
X
No Change
L
L
L
H
X
X
X
No Change
L
L
L
H
X
X
No Change
L
L
L
X
H
X
No Change
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
X
X
X
No Change
L
H
X
X
X
X
X
High Impedance
H
L
X
X
X
X
X
High Impedance
H
H
X
X
X
X
X
High Impedance
MC74HC173
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
D2
D1
D0
RESET
VCC
DE1
DE2
D3
Q1
Q0
OE2
OE1
GND
CLOCK
Q3
Q2
D SUFFIX
SOIC PACKAGE
CASE 751B05
N SUFFIX
PLASTIC PACKAGE
CASE 64808
ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXD
Plastic
SOIC
1
16
1
16
LOGIC DIAGRAM
VCC = PIN 16
GND = PIN 8
DATA
INPUTS
3STATE
NONINVERTING
OUTPUTS
D0
D1
D2
D3
14
13
12
11
3
4
5
6
Q0
Q1
Q2
Q3
CLOCK
7
DATA
ENABLES
OUTPUT
ENABLES
DE1
DE2
OE1
OE2
RESET
9
10
15
1
2
MC74HC173
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
1.5 to VCC + 1.5
V
Vout
DC Output Voltage (Referenced to GND)
0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
20
mA
Iout
DC Output Current, per Pin
35
mA
ICC
DC Supply Current, VCC and GND Pins
75
mA
PD
Power Dissipation in Still Air
Plastic DIP
SOIC Package
750
500
mW
Tstg
Storage Temperature
65 to + 150
_
C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
_
C
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating -- Plastic DIP: 10 mW/
_
C from 65
_
to 125
_
C
SOIC Package: 7 mW/
_
C from 65
_
to 125
_
C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, Vout
DC Input Voltage, Output Voltage (Referenced to GND)
0
VCC
V
TA
Operating Temperature, All Package Types
55
+ 125
_
C
tr, tf
Input Rise and Fall Time
VCC = 2.0 V
(Figure 1)
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
Parameter
Test Conditions
VCC
V
Guaranteed Limit
Unit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25
_
C
v
85
_
C
v
125
_
C
Unit
VIH
Minimum HighLevel Input
Voltage
Vout = 0.1 V or VCC 0.1 V
|Iout|
v
20
A
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum LowLevel Input
Voltage
Vout = 0.1 V or VCC 0.1 V
|Iout|
v
20
A
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VOH
Minimum HighLevel Output
Voltage
Vin = VIH or VIL
|Iout|
v
20
A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL |Iout|
v
6.0 mA
|Iout|
v
7.8 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
VOL
Maximum LowLevel Output
Voltage
Vin = VIH or VIL
|Iout|
v
20
A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL |Iout|
v
6.0 mA
|Iout|
v
7.8 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
0.1
1.0
1.0
A
IOZ
Maximum ThreeState
Leakage Current
Output in HighImpedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
0.5
5.0
10
A
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0
A
6.0
8
80
160
A
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND
v
(Vin or Vout)
v
VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74HC173
HighSpeed CMOS Logic Data
DL129 -- Rev 6
3
MOTOROLA
AC ELECTRICAL CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
Symbol
Parameter
VCC
V
55 to
25
_
C
v
85
_
C
v
125
_
C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 5)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q
(Figures 1 and 5)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tPHL
Maximum Propagation Delay, Reset to Q
(Figures 2 and 5)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
Cin
Maximum Input Capacitance
--
10
10
10
pF
Cout
Maximum ThreeState Output Capacitance
(Output in HighImpedance State)
--
15
15
15
pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per FlipFlop)*
Typical @ 25
C, VCC = 5.0 V
pF
CPD
Power Dissipation Capacitance (Per FlipFlop)*
35
pF
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS
(Input tr = tf = 6 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
Symbol
Parameter
VCC
V
55 to
25
_
C
v
85
_
C
v
125
_
C
Unit
tsu
Minimum Setup Time, Input D or DE to Clock
(Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
th
Minimum Hold Time, Clock to Input D or DE
(Figure 4)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
trec
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0
4.5
6.0
90
18
15
115
23
20
135
27
23
ns
tw
Minimum Pulse Width, Clock
(Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tw
Minimum Pulse Width, Reset
(Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
MC74HC173
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
4
PIN DESCRIPTIONS
INPUTS
D0, D1, D2, D3 (Pins 14, 13, 12, 11)
4bit data inputs. Data on these pins, when enabled by the
DataEnable Controls, are entered into the flipflops on the
rising edge of the clock.
CLOCK (Pin 7)
Clock input.
OUTPUTS
Q0, Q1, Q2, Q3 (Pins 3, 4, 5, 6)
3state register outputs. During normal operation of the
device, the outputs of the D flipflops appear at these pins.
During 3state operation, these outputs assume a high
impedance state.
CONTROL INPUT
Reset (Pin 15)
Asynchronous reset input. A high level on this pin resets all
flipflops and forces the Q outputs low, if they are not already
in highimpedance state.
DE1, DE2 (Pins 9, 10)
Activelow Data Enable Control inputs. When both Data
Enable Controls are low, data at the D inputs are loaded into
the flipflops with the rising edge of the Clock input. When
either or both of these controls are high, there is no change in
the state of the flipflops, regardless of any changes at the D
or Clock inputs.
OE1, OE2 (Pins 1, 2)
Output Enable Control inputs. When either or both of the
Output Enable Controls are high, the Q outputs of the device
are in the highimpedance state. When both controls are
low, the device outputs display the data in the flipflops.
SWITCHING WAVEFORMS
tr
tf
VCC
GND
tTHL
tTLH
90%
50%
10%
90%
50%
10%
CLOCK
tPLH
tPHL
tw
50%
tPHL
VCC
GND
VCC
GND
CLOCK
RESET
50%
50%
trec
Figure 1.
Figure 2.
Q
Q
VCC
GND
VCC
GND
50%
50%
CLOCK
INPUT D
OR DE
50%
50%
50%
OE
Q
Q
tPZL
tPLZ
tPZH tPHZ
10%
90%
VCC
GND
HIGH
IMPEDANCE
VOL
VOH
Figure 3.
Figure 4.
tw
1/fmax
HIGH
IMPEDANCE
VALID
tsu
th
MC74HC173
HighSpeed CMOS Logic Data
DL129 -- Rev 6
5
MOTOROLA
TEST CIRCUITS
* Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 5.
Figure 6.
OUTPUT
TEST POINT
CL *
1 k
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ and tPZH.
DEVICE
UNDER
TEST
* Includes all probe and jig capacitance
LOGIC DETAIL
D0
14
D1
13
D2
12
D3
11
9
10
DE1
DE2
15
RESET
CLOCK
7
OE1
OE2
1
2
DATA
ENABLES
OUTPUT
ENABLES
DATA
INPUTS
C
C
R
Q
VCC
3
Q0
D
C
C
R
Q
D
C
C
R
Q
D
C
C
R
Q
D
VCC
4
Q1
VCC
5
Q2
VCC
6
Q3
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