MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
31
REV 6
Motorola, Inc. 1995
10/95
Dual Precision
Monostable Multivibrator
(Retriggerable, Resettable)
The MC54/74HC4538A is identical in pinout to the MC14538B. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This dual monostable multivibrator may be triggered by either the positive
or the negative edge of an input pulse, and produces a precision output
pulse over a wide range of pulse widths. Because the device has conditioned
trigger inputs, there are no triggerinput rise and fall time restrictions. The
output pulse width is determined by the external timing components, Rx and
Cx. The device has a reset function which forces the Q output low and the Q
output high, regardless of the state of the output pulse circuitry.
Unlimited Rise and Fall Times Allowed on the Trigger Inputs
Output Pulse is Independent of the Trigger Pulse Width
10% Guaranteed Pulse Width Variation from Part to Part (Using the
Same Test Jig)
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 3.0 to 6.0 V
Low Input Current: 1.0
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 145 FETs or 36 Equivalent Gates
LOGIC DIAGRAM
PIN 16 = VCC
PIN 8 = GND
RX AND CX ARE EXTERNAL COMPONENTS
PIN 1 AND PIN 15 MUST BE HARD WIRED TO GND
CX1
RX1
VCC
Q1
RESET 1
B1
A1
TRIGGER
INPUTS
Q1
1
2
4
5
3
6
7
CX2
RX2
VCC
Q2
RESET 2
B2
A2
TRIGGER
INPUTS
Q2
15
14
12
11
13
10
9
MC54/74HC4538A
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
A2
RESET 2
CX2/RX2
GND
VCC
Q2
Q2
B2
A1
RESET 1
CX1/RX1
GND
GND
Q1
Q1
B1
FUNCTION TABLE
Inputs
Outputs
Reset
A
B
Q
Q
H
H
H
L
H
X
L
Not Triggered
H
H
X
Not Triggered
H
L,H,
H
Not Triggered
H
L
L,H,
Not Triggered
L
X
X
L
H
X
X
Not Triggered
D SUFFIX
SOIC PACKAGE
CASE 751B05
N SUFFIX
PLASTIC PACKAGE
CASE 64808
ORDERING INFORMATION
MC54HCXXXXAJ
MC74HCXXXXAN
MC74HCXXXXAD
Ceramic
Plastic
SOIC
1
16
1
16
J SUFFIX
CERAMIC PACKAGE
CASE 62010
1
16
MC54/74HC4538A
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
32
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
1.5 to VCC + 1.5
V
Vout
DC Output Voltage (Referenced to GND)
0.5 to VCC + 0.5
Iin
DC Input Current, per Pin
A, B, Reset
Cx, Rx
20
30
mA
Iout
DC Output Current, per Pin
25
mA
ICC
DC Supply Current, VCC and GND Pins
50
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP
SOIC Package
750
500
mW
Tstg
Storage Temperature
65 to + 150
_
C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)
260
300
_
C
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating -- Plastic DIP: 10 mW/
_
C from 65
_
to 125
_
C
Ceramic DIP: 10 mW/
_
C from 100
_
to 125
_
C
SOIC Package: 7 mW/
_
C from 65
_
to 125
_
C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage (Referenced to GND)
3.0**
6.0
V
Vin, Vout
DC Input Voltage, Output Voltage (Referenced to GND)
0
VCC
V
TA
Operating Temperature, All Package Types
55
+ 125
_
C
tr, tf
Input Rise and Fall Time
VCC = 2.0 V
(Figure 7)
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
A or B (Figure 5)
--
No Limit
Rx
External Timing Resistor
VCC < 4.5 V
VCC
4.5 V
1.0
2.0
*
*
k
Cx
External Timing Capacitor
0
*
F
* The maximum allowable values of Rx and Cx are a function of the leakage of capacitor Cx, the leakage of the HC4538A, and leakage due to
board layout and surface resistance. For most applications, Cx/Rx should be limited to a maximum value of 10
F/1.0 M
. Values of Cx > 1.0
F
may cause a problem during power down (see Power Down Considerations). Susceptibility to externally induced noise signals may occur for
Rx > 1.0 M
.
** The HC4538A will function at 2.0 V but for optimum pulse width stability, VCC should be above 3.0 V.
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND
v
(Vin or Vout)
v
VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC54/74HC4538A
HighSpeed CMOS Logic Data
DL129 -- Rev 6
33
MOTOROLA
DC CHARACTERISTICS FOR THE MC54/74HC4538A
Symbol
Parameter
Test Conditions
VCC
Volts
Guaranteed Limits
Unit
Symbol
Parameter
Test Conditions
VCC
Volts
55 to
25
_
C
v
85
_
C
v
125
_
C
Unit
Symbol
Parameter
Test Conditions
VCC
Volts
Min
Max
Min
Max
Min
Max
Unit
VIH
Minimum HighLevel
Input Voltage
Vout = 0.1 V or VCC 0.1 V
|Iout|
v
20
A
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum LowLevel
Input Voltage
Vout = 0.1 V or VCC 0.1 V
|Iout|
v
20
A
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
VOH
Minimum HighLevel
Output Voltage
Vin = VIH or VIL
|Iout|
v
20
A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL
|Iout|
v
4.0 mA
|Iout|
v
5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VOL
Maximum LowLevel
Output Voltage
Vin = VIH or VIL
|Iout|
v
20
A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL
|Iout|
v
4.0 mA
|Iout|
v
5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
Iin
Maximum Input
Leakage Current
(A, B, Reset)
Vin = VCC or GND
6.0
0.1
1.0
1.0
A
Iin
Maximum Input
Leakage Current
(Rx, Cx)
Vin = VCC or GND
6.0
50
500
500
nA
ICC
Maximum Quiescent
Supply Current
(per package)
Standby State
Vin = VCC or GND
Q1 and Q2 = Low
Iout = 0
A
6.0
130
220
350
A
ICC
Maximum Supply Current
(per package)
Active State
Vin = VCC or GND
Q1 and Q2 = High
Iout = 0
A
Pins 2 and 14 = 0.5 VCC
6.0
25
_
C
45
_
C to
85
_
C
55
_
C to
125
_
C
A
Active State
Iout = 0
A
Pins 2 and 14 = 0.5 VCC
6.0
400
600
800
A
MC54/74HC4538A
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
34
AC CHARACTERISTICS FOR THE MC54/74HC4538A
(CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
Parameter
VCC
Volts
Guaranteed Limits
Unit
Symbol
Parameter
VCC
Volts
55 to
25
_
C
v
85
_
C
v
125
_
C
Unit
Symbol
Parameter
VCC
Volts
Min
Max
Min
Max
Min
Max
Unit
tPLH
Maximum Propagation Delay
Input A or B to Q
(Figures 6 and 8)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tPHL
Maximum Propagation Delay
Input A or B to NQ
(Figures 6 and 8)
2.0
4.5
6.0
195
39
33
245
49
42
295
59
50
ns
tPHL
Maximum Propagation Delay
Reset to Q
(Figures 7 and 8)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tPLH
Maximum Propagation Delay
Reset to NQ
(Figures 7 and 8)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tTLH
tTHL
Maximum Output Transition Time, Any Output
(Figures 7 and 8)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Cin
Maximum Input Capacitance
(A. B, Reset)
(Cx, Rx)
--
10
25
10
25
10
25
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High
Speed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Multivibrator)*
Typical @ 25
C, VCC = 5.0 V
pF
CPD
Power Dissipation Capacitance (Per Multivibrator)*
150
pF
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
TIMING CHARACTERISTICS FOR THE MC54/74HC4538A
(Input tr = tf = 6.0 ns)
Symbol
Parameter
VCC
Volts
Guaranteed Limits
Unit
Symbol
Parameter
VCC
Volts
55 to
25
_
C
v
85
_
C
v
125
_
C
Unit
Symbol
Parameter
VCC
Volts
Min
Max
Min
Max
Min
Max
Unit
trec
Minimum Recovery Time, Inactive to A or B
(Figure 7)
2.0
4.5
6.0
0
0
0
0
0
0
0
0
0
ns
tw
Minimum Pulse Width, Input A or B
(Figure 6)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
tw
Minimum Pulse Width, Reset
(Figure 7)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
tr, tf
Maximum Input Rise and Fall Times, Reset
(Figure 7)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
A or B
(Figure 7)
2.0
4.5
6.0
No Limit
MC54/74HC4538A
HighSpeed CMOS Logic Data
DL129 -- Rev 6
35
MOTOROLA
OUTPUT PULSE WIDTH CHARACTERISTICS
(CL = 50 pF)t
Symbol
Parameter
Conditions
Guaranteed Limits
Unit
Symbol
Parameter
Timing Components
VCC
Volts
55 to
25
_
C
v
85
_
C
v
125
_
C
Unit
Symbol
Parameter
Timing Components
VCC
Volts
Min
Max
Min
Max
Min
Max
Unit
Output Pulse Width*
(Figures 6 and 8)
Rx = 10 k
, Cx = 0.1
F
5.0
0.63
0.77
0.6
0.8
0.59
0.81
ms
--
Pulse Width Match
Between Circuits in the
same Package
--
--
5.0
%
--
Pulse Width Match
Variation (Part to Part)
--
--
10
%
* For output pulse widths greater than 100
s, typically
= kRxCx, where the value of k may be found in Figure 1.
Figure 1. Typical Output Pulse Width Constant, k,
versus Supply Voltage
(For output pulse widths
>
100
s:
= kRxCx)
Figure 2. Output Pulse Width versus
Timing Capacitance
Figure 3. Normalized Output Pulse Width
versus Power Supply Voltage
0.8
0.7
0.6
0.5
0.4
0.3
10 s
1 s
100 ms
10 ms
1 ms
100
s
10
s
1
s
100 ns
1.1
1
0.9
0.8
0.7
0.6
0.5
1
2
3
4
5
6
7
0.00001 0.0001
0.001
0.01
0.1
1
10
100
1
2
3
4
5
6
7
VCC, POWER SUPPLY VOLTAGE (VOLTS)
CAPACITANCE (
F)
VCC, POWER SUPPLY VOLTAGE (VOLTS)
k, OUTPUT
PULSE WIDTH CONST
ANT
(TYPICAL)
OUTPUT
PULSE WIDTH (
)
OUTPUT
PULSE WIDTH (t)
(NORMALIZED
T
O 5 V NUMBER)
TA = 25
C
VCC = 5 V, TA = 25
C
1 M
100 k
10 k
1 k
TA = 25
C
Rx = 100 k
Cx = 1000 pF
Rx = 1 M
Cx = 0.1
F
MC54/74HC4538A
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
36
Figure 4. Normalized Output Pulse Width
versus Power Supply Voltage
Figure 5. Normalized Output Pulse Width
versus Power Supply Voltage
1.1
1.05
1
0.95
0.9
0.85
0.8
1.03
1.02
1.01
1
0.99
0.98
0.97
75
50
25
0
25
50
75
100
125
150
75
50
25
0
25
50
75
100
125
150
TA, AMBIENT TEMPERATURE (
C)
TA, AMBIENT TEMPERATURE (
C)
OUTPUT
PULSE WIDTH (
)
(NORMALIZED
T
O 25
C NUMBER)
Rx = 10 k
Cx = 0.1
F
VCC = 6 V
VCC = 3 V
Rx = 10 k
Cx = 0.1
F
VCC = 5.5 V
VCC = 4.5 V
VCC = 5 V
OUTPUT
PULSE WIDTH (
)
(NORMALIZED
T
O 25
C NUMBER)
MC54/74HC4538A
HighSpeed CMOS Logic Data
DL129 -- Rev 6
37
MOTOROLA
SWITCHING WAVEFORMS
Figure 6.
A
B
Q
Q
A
B
RESET
Q
Q
50%
tPLH
50%
50%
tPLH
50%
GND
VCC
GND
VCC
tr
tf
90%
10%
tf
tTLH
tTHL
90%
10%
90%
10%
tPLH
tPHL
50%
50%
tf
90%
10%
50%
50%
(RETRIGGERED PULSE)
50%
GND
VCC
GND
VCC
GND
VCC
tw(H)
tw(L)
tw(L)
trec
+ trr
trr
tPHL
tPHL
Figure 7.
* Includes all probe and jig capacitance
Figure 8. Test Circuit
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
MC54/74HC4538A
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
38
PIN DESCRIPTIONS
INPUTS
A1, A2 (Pins 4, 12)
Positiveedge trigger inputs. A risingedge signal on
either of these pins triggers the corresponding multivibrator
when there is a high level on the B1 or B2 input.
B1, B2 (Pins 5, 11)
Negativeedge trigger inputs. A fallingedge signal on
either of these pins triggers the corresponding multivibrator
when there is a low level on the A1 or A2 input.
Reset 1, Reset 2 (Pins 3, 13)
Reset inputs (active low). When a low level is applied to
one of these pins, the Q output of the corresponding multi-
vibrator is reset to a low level and the Q output is set to a high
level.
CX1/RX1 and CX2/RX2 (Pins 2 and 14)
External timing components. These pins are tied to the
common points of the external timing resistors and capaci-
tors (see the Block Diagram). Polystyrene capacitors are
recommended for optimum pulse width control. Electrolytic
capacitors are not recommended due to high leakages
associated with these type capacitors.
GND (Pins 1 and 15)
External ground. The external timing capacitors discharge
to ground through these pins.
OUTPUTS
Q1, Q2 (Pins 6, 10)
Noninverted monostable outputs. These pins (normally
low) pulse high when the multivibrator is triggered at either
the A or the B input. The width of the pulse is determined by
the external timing components, RX and CX.
Q1, Q2 (Pins 7, 9)
Inverted monostable outputs. These pins (normally high)
pulse low when the multivibrator is triggered at either the A or
the B input. These outputs are the inverse of Q1 and Q2.
+
+
Figure 9.
RxCx
VCC
M1
2 k
M3
M2
A
B
RESET
POWER
ON
RESET
RESET LATCH
TRIGGER CONTROL
RESET CIRCUIT
TRIGGER CONTROL
CIRCUIT
OUTPUT
LATCH
UPPER
REFERENCE
CIRCUIT
Vre, UPPER
LOWER
REFERENCE
CIRCUIT
Vre, LOWER
Q
Q
C
CB
Q
R
VCC
LOGIC DETAIL
(1/2 THE DEVICE)
MC54/74HC4538A
HighSpeed CMOS Logic Data
DL129 -- Rev 6
39
MOTOROLA
CIRCUIT OPERATION
Figure 12 shows the HC4538A configured in the retrigger-
able mode. Briefly, the device operates as follows (refer to
Figure 10): In the quiescent state, the external timing capac-
itor, Cx, is charged to VCC. When a trigger occurs, the Q out-
put goes high and Cx discharges quickly to the lower
reference voltage (Vref Lower
[
1/3 VCC). Cx then charges,
through Rx, back up to the upper reference voltage (Vref Up-
per
[
2/3 VCC), at which point the oneshot has timed out
and the Q output goes low.
The following, more detailed description of the circuit op-
eration refers to both the logic detail (Figure 9) and the timing
diagram (Figure 10).
QUIESCENT STATE
In the quiescent state, before an input trigger appears, the
output latch is high and the reset latch is high (#1 in Fig-
ure 10). Thus the Q output (pin 6 or 10) of the monostable
multivibrator is low (#2, Figure 10).
The output of the triggercontrol circuit is low (#3), and
transistors M1, M2, and M3 are turned off. The external tim-
ing capacitor, Cx, is charged to VCC (#4), and both the upper
and lower reference circuit has a low output (#5).
In addition, the output of the triggercontrol reset circuit is
low.
TRIGGER OPERATION
The HC4538A is triggered by either a risingedge signal at
input A (#7) or a fallingedge signal at input B (#8), with the
unused trigger input and the Reset input held at the voltage
levels shown in the Function Table. Either trigger signal will
cause the output of the triggercontrol circuit to go high (#9).
The triggercontrol circuit going high simultaneously initi-
ates two events. First, the output latch goes low, thus taking
the Q output of the HC4538A to a high state (#10). Second,
transistor M3 is turned on, which allows the external timing
capacitor, Cx, to rapidly discharge toward ground (#11).
(Note that the voltage across Cx appears at the input of both
the upper and lower reference circuit comparator).
When Cx discharges to the reference voltage of the lower
reference circuit (#12), the outputs of both reference circuits
will be high (#13). The triggercontrol reset circuit goes high,
resetting the triggercontrol circuit flipflop to a low state
(#14). This turns transistor M3 off again, allowing Cx to begin
to charge back up toward VCC, with a time constant t = RxCx
(#15). Once the voltage across Cx charges to above the low-
er reference voltage, the lower reference circuit will go low
allowing the monostable multivibrator to be retriggered.
2
18
1
6
5
4
17
14
3
9
8
7
QUIESCENT
STATE
TRIGGER CYCLE
(A INPUT)
TRIGGER CYCLE
(B INPUT)
RESET
RETRIGGER
trr
Vref UPPER
Vref LOWER
TRIGGER INPUT A
(PIN 4 OR 12)
TRIGGER INPUT B
(PIN 5 OR 11)
TRIGGER-CONTROL
CIRCUIT OUTPUT
RX/CX INPUT
(PIN 2 OR 14)
UPPER REFERENCE
CIRCUIT
LOWER REFERENCE
CIRCUIT
RESET INPUT
(PIN 3 OR 13)
RESET LATCH
Q OUTPUT
(PIN 6 OR 10)
Figure 10. Timing Diagram
10
11
12
13
15
16
19
20
21
22
23
24
25
+ trr
13
MC54/74HC4538A
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
310
When Cx charges up to the reference voltage of the upper
reference circuit (#17), the output of the upper reference cir-
cuit goes low (#18). This causes the output latch to toggle,
taking the Q output of the HC4538A to a low state (#19), and
completing the timeout cycle.
POWERDOWN CONSIDERATIONS
Large values of Cx may cause problems when powering
down the HC4538A because of the amount of energy stored
in the capacitor. When a system containing this device is
powered down, the capacitor may discharge from VCC
through the input protection diodes at pin 2 or pin 14. Current
through the protection diodes must be limited to 30 mA;
therefore, the turnoff time of the VCC power supply must not
be faster than t = V C C
C x /(30 mA). For example, if
VCC = 5.0 V and Cx = 15
F, the VCC supply must turn off no
faster than t = (5.0 V)
(15
F)/30 mA = 2.5 ms. This is usually
not a problem because power supplies are heavily filtered
and cannot discharge at this rate.
When a more rapid decrease of VCC to zero volts occurs,
the HC4538A may sustain damage. To avoid this possibility,
use an external damping diode, Dx, connected as shown in
Figure 11. Best results can be achieved if diode Dx is chosen
to be a germanium or Schottky type diode able to withstand
large current surges.
RESET AND POWER ON RESET OPERATION
A low voltage applied to the Reset pin always forces the Q
output of the HC4538A to a low state.
The timing diagram illustrates the case in which reset oc-
curs (#20) while Cx is charging up toward the reference volt-
age of the upper reference circuit (#21). When a reset
occurs, the output of the reset latch goes low (#22), turning
on transistor M1. Thus Cx is allowed to quickly charge up to
VCC (#23) to await the next trigger signal.
On power up of the HC4538A the poweron reset circuit
will be high causing a reset condition. This will prevent the
triggercontrol circuit from accepting a trigger input during
this state. The HC4538A's Q outputs are low and the Q not
outputs are high.
RETRIGGER OPERATION
When used in the retriggerable mode (Figure 12), the
HC4538A may be retriggered during timing out of the output
pulse at any time after the triggercontrol circuit flipflop has
been reset (#24), and the voltage across Cx is above the low-
er reference voltage. As long as the Cx voltage is below the
lower reference voltage, the reset of the flipflop is high, dis-
abling any trigger pulse. This prevents M3 from turning on
during this period resulting in an output pulse width that is
predictable.
The amount of undershoot voltage on RxCx during the
trigger mode is a function of loop delay, M3 conductivity, and
VDD. Minimum retrigger time, trr (Figure 7), is a function of
1) time to discharge RxCx from VDD to lower reference
voltage (Tdischarge); 2) loop delay (Tdelay); 3) time to charge
RxCx from the undershoot voltage back to the lower refer-
ence voltage (Tcharge).
Figure 13 shows the device configured in the nonretrig-
gerable mode.
An Application Note (AN1558/D) titled
Characterization of
Retrigger Time in the HC4538A Dual Precision Monstable
Multivibrator is being prepared. Please consult the factory for
its availability.
DX
CX
VCC
Q
Q
RESET
A
B
Figure 11. Discharge Protection During Power Down
RX
MC54/74HC4538A
HighSpeed CMOS Logic Data
DL129 -- Rev 6
311
MOTOROLA
TYPICAL APPLICATIONS
RESET = VCC
RISINGEDGE
TRIGGER
B = VCC
RESET = VCC
RISINGEDGE
TRIGGER
A = GND
RESET = VCC
FALLINGEDGE
TRIGGER
RESET = VCC
FALLINGEDGE
TRIGGER
Figure 12. Retriggerable Monostable Circuitry
Figure 13. Nonretriggerable Monostable Circuitry
CX
VCC
Q
Q
A
B
RX
CX
VCC
Q
Q
A
B
RX
CX
VCC
Q
Q
B
RX
CX
VCC
Q
Q
A
B
RX
ONESHOT SELECTION GUIDE
100 ns
1
s
10
s 100
s 1 ms
10 ms 100 ms
1 s
10 s
MC14528B
MC14536B
MC14538B
MC14541B
HC4538A*
* Limited operating voltage (2 6 V)
23 HR
5 MIN
TOTAL OUTPUT PULSE WIDTH RANGE
RECOMMENDED PULSE WIDTH RANGE
MC54/74HC4538A
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
312
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 62010
ISSUE V
N SUFFIX
PLASTIC PACKAGE
CASE 64808
ISSUE R
19.05
6.10
--
0.39
1.40
0.21
3.18
19.93
7.49
5.08
0.50
1.65
0.38
4.31
0
0.51
15
1.01
1.27 BSC
2.54 BSC
7.62 BSC
MIN
MIN
MAX
MAX
INCHES
MILLIMETERS
DIM
0.750
0.240
--
0.015
0.055
0.008
0.125
0.785
0.295
0.200
0.020
0.065
0.015
0.170
0.050 BSC
0.100 BSC
0.300 BSC
A
B
C
D
E
F
G
J
K
L
M
N
0
0.020
15
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
1
8
9
16
A
B
C
K
N
G
E
F
D
16 PL
T
SEATING
PLANE
M
L
J
16 PL
0.25 (0.010)
T
A
M
S
0.25 (0.010)
T
B
M
S
MIN
MIN
MAX
MAX
INCHES
MILLIMETERS
DIM
A
B
C
D
F
G
H
J
K
L
M
S
18.80
6.35
3.69
0.39
1.02
0.21
2.80
7.50
0
0.51
19.55
6.85
4.44
0.53
1.77
0.38
3.30
7.74
10
1.01
0.740
0.250
0.145
0.015
0.040
0.008
0.110
0.295
0
0.020
0.770
0.270
0.175
0.021
0.070
0.015
0.130
0.305
10
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
2.54 BSC
1.27 BSC
0.100 BSC
0.050 BSC
A
B
1
8
9
16
F
H
G
D
16 PL
S
C
T
SEATING
PLANE
K
J
M
L
T
A
0.25 (0.010)
M
M
0.25 (0.010)
T
B
A
M
S
S
MIN
MIN
MAX
MAX
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
K
M
P
R
9.80
3.80
1.35
0.35
0.40
0.19
0.10
0
5.80
0.25
10.00
4.00
1.75
0.49
1.25
0.25
0.25
7
6.20
0.50
0.386
0.150
0.054
0.014
0.016
0.008
0.004
0
0.229
0.010
0.393
0.157
0.068
0.019
0.049
0.009
0.009
7
0.244
0.019
1.27 BSC
0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
8
9
16
A
B
D
16 PL
K
C
G
T
SEATING
PLANE
R
X 45
M
J
F
P
8 PL
0.25 (0.010)
B
M
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B05
ISSUE J
MC54/74HC4538A
HighSpeed CMOS Logic Data
DL129 -- Rev 6
313
MOTOROLA
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