5-1
FAST AND LS TTL DATA
8-BIT SHIFT REGISTERS
The SN54L/ 74LS166 is an 8-Bit Shift Register. Designed with all inputs
buffered, the drive requirements are lowered to one 54/ 74LS standard load.
By utilizing input clamping diodes, switching transients are minimized and
system design simplified.
The LS166 is a parallel-in or serial-in, serial-out shift register and has a
complexity of 77 equivalent gates with gated clock inputs and an overriding
clear input. The shift/load input establishes the parallel-in or serial-in mode.
When high, this input enables the serial data input and couples the eight
flip-flops for serial shifting with each clock pulse. Synchronous loading occurs
on the next clock pulse when this is low and the parallel data inputs are
enabled. Serial data flow is inhibited during parallel loading. Clocking is done
on the low-to-high level edge of the clock pulse via a two input positive NOR
gate, which permits one input to be used as a clock enable or clock inhibit
function. Clocking is inhibited when either of the clock inputs are held high,
holding either input low enables the other clock input. This will allow the
system clock to be free running and the register stopped on command with
the other clock input. A change from low-to-high on the clock inhibit input
should only be done when the clock input is high. A buffered direct clear input
overrides all other inputs, including the clock, and sets all flip-flops to zero.
Synchronous Load
Direct Overriding Clear
Parallel to Serial Conversion
14
13
12
11
10
9
1
2
3
4
5
6
7
16
15
8
VCC
SERIAL
INPUT
SHIFT/
LOAD
H
QH
G
E
F
CLEAR
A
B
C
D
CLOCK
INHIBIT
CLOCK GND
PARALLEL
PARALLEL INPUTS
INPUT OUTPUT
PARALLEL INPUTS
SHIFT/
LOAD
SERIAL INPUT
CLOCK
INHIBIT
H
QH
G
F
E
A
B
C
D
CK
CLEAR
FUNCTION TABLE
INPUTS
INTERNAL
OUTPUTS
OUTPUT
QH
CLEAR
SHIFT/
LOAD
CLOCK
INHIBIT
CLOCK
SERIAL
PARALLEL
INTERNAL
OUTPUTS
OUTPUT
QH
CLEAR
SHIFT/
LOAD
CLOCK
INHIBIT
CLOCK
SERIAL
A . . . H
QA
QB
QH
L
X
X
X
X
X
L
L
L
H
X
L
L
X
X
QA0
QB0
QH0
H
L
L
X
a . . . h
a
b
h
H
H
L
H
X
H
QAn
QGn
H
H
L
L
X
L
QAn
QGn
H
X
H
X
X
QA0
QB0
QH0
SN54/74LS166
8-BIT SHIFT REGISTERS
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN
Plastic
SN74LSXXXD
SOIC
16
1
D SUFFIX
SOIC
CASE 751B-03
5-2
FAST AND LS TTL DATA
SN54/74LS166
Typical Clear, Shift, Load, Inhibit, and Shift Sequences
PARALLEL
INPUTS
A
B
C
D
CLOCK INIHIBIT
CLOCK
SHIFT/LOAD
H
OUTPUT QH
G
F
E
CLEAR
SERIAL INPUT
H
H
H
H
H
L
L
L
H H
H
H
H
L
L
L
CLEAR
SERIAL SHIFT
LOAD
INHIBIT
SERIAL SHIFT
CLEAR
SERIAL INPUT
SHIFT/LOAD
A
B
C
D
H
G
F
E
(9)
(1)
(15)
(2)
(3)
(4)
(5)
(10)
(11)
(12)
(14)
(7)
(6)
CLOCK INHIBIT
CLOCK
(13)
R
CK
S
QA
R
CK
S
QB
R
CK
S
QC
R
CK
S
QD
R
CK
S
QE
R
CK
S
QF
R
CK
S
QG
R
CK
S
QH
5-3
FAST AND LS TTL DATA
SN54/74LS166
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
55
0
25
25
125
70
C
IOH
Output Current -- High
54, 74
0.4
mA
IOL
Output Current -- Low
54
74
4.0
8.0
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54
0.7
V
Guaranteed Input LOW Voltage for
All Inputs
VIL
Input LOW Voltage
74
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK
Input Clamp Diode Voltage
0.65
1.5
V
VCC = MIN, IIN = 18 mA
VOH
Output HIGH Voltage
54
2.5
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOH
Output HIGH Voltage
74
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL
Output LOW Voltage
54, 74
0.25
0.4
V
IOL = 4.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VOL
Output LOW Voltage
74
0.35
0.5
V
IOL = 8.0 mA
VIN = VIL or VIH
per Truth Table
IIH
Input HIGH Current
20
A
VCC = MAX, VIN = 2.7 V
IIH
Input HIGH Current
0.1
mA
VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
0.4
mA
VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current (Note 1)
20
100
mA
VCC = MAX
ICC
Power Supply Current
38
mA
VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
5-4
FAST AND LS TTL DATA
SN54/74LS166
TEST TABLE FOR SYNCHRONOUS INPUTS
DATA INPUT
FOR TEST
SHIFT/LOAD
OUTPUT TESTED
H
0 V
QH at tn+1
Serial
Input
4.5 V
QH at tn+8
AC WAVEFORMS
NOTE 1. tn = bit time before clocking transition
NOTE 1.
tn+1 = bit time after one clocking transition
NOTE 1.
tn+8 = bit time after eight clocking transition
NOTE 1.
LS166 Vref = 1.3 V.
CLEAR INPUT
CLOCK INPUT
DATA
INPUT
(SEE TEST
TABLE)
OUTPUT Q
Vref
tw(clear)
tPHL
(clear-Q)
(SEE NOTE 1)
tn + 1
tn
tsu
th
tPLH
(CLK-Q)
3 V
0 V
VOH
VOL
3 V
3 V
0 V
0 V
Vref
Vref
Vref
Vref
Vref
Vref
Vref
Vref
tn
tn + 1
tsu
th
tPHL
tw(clock)
(CLK-Q)
Vref
Vref
Vref
AC CHARACTERISTICS
(TA = 25
C)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
fMAX
Maximum Clock Frequency
25
35
MHz
VCC = 5.0 V
CL = 15 pF
tPHL
Clear to Output
19
30
ns
VCC = 5.0 V
CL = 15 pF
tPLH
tPHL
Clock to Output
23
24
35
35
ns
CC = 5.0 V
CL = 15 pF
AC SETUP REQUIREMENTS
(TA = 25
C)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
tW
Clock Clear Pulse Width
30
ns
VCC = 5.0 V
ts
Mode Control Setup Time
30
ns
VCC = 5.0 V
ts
Data Setup Time
20
ns
VCC = 5.0 V
th
Hold Time, Any Input
15
ns
PDF 
ZIP