5-447
FAST AND LS TTL DATA
OCTAL D FLIP-FLOP WITH CLEAR
The SN54 / 74LS273 is a high-speed 8-Bit Register. The register consists of
eight D-Type Flip-Flops with a Common Clock and an asynchronous active
LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3
inch lead spacing.
8-Bit High Speed Register
Parallel Register
Common Clock and Master Reset
Input Clamp Diodes Limit High-Speed Termination Effects
18
17
16
15
14
13
1
2
3
4
5
6
7
20
19
8
VCC
MR
Q7 D7 D6 Q6
D5
Q5
D4
Q0 D0 D1 Q1 Q2 D2 D3
9
10
Q3 GND
12
11
Q4 CP
CONNECTION DIAGRAM DIP (TOP VIEW)
PIN NAMES
LOADING (Note a)
HIGH
LOW
CP
Clock (Active HIGH Going Edge) Input
0.5 U.L.
0.25 U.L.
D0 D7
Data Inputs
0.5 U.L.
0.25 U.L.
MR
Master Reset (Active LOW) Input
0.5 U.L.
0.25 U.L.
Q0 Q7
Register Outputs (Note b)
10 U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
A HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
(74) Temperature Ranges.
TRUTH TABLE
MR
CP
Dx
Qx
L
X
X
L
H
H
H
H
L
L
H = HIGH Logic Level
L = LOW Logic Level
X = Immaterial
LOGIC DIAGRAM
CP
MR
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP D
CD Q
CP D
CD Q
CP D
CD Q
CP D
CD Q
CP D
CD Q
CP D
CD Q
CP D
CD Q
CP D
CD Q
14
1
2
6
7
3
8
4
5
9
11
12
13
15
VCC = PIN 20
GND = PIN 10
= PIN NUMBERS
17
18
16
19
SN54/74LS273
OCTAL D FLIP-FLOP
WITH CLEAR
LOW POWER SCHOTTKY
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN
Plastic
SN74LSXXXDW SOIC
20
1
J SUFFIX
CERAMIC
CASE 732-03
20
1
N SUFFIX
PLASTIC
CASE 738-03
20
1
DW SUFFIX
SOIC
CASE 751D-03
5-448
FAST AND LS TTL DATA
SN54/74LS273
FUNCTIONAL DESCRIPTION
The SN54 / 74LS273 is an 8-Bit Parallel Register with a
common Clock and common Master Reset.
When the MR input is LOW, the Q outputs are LOW,
independent of the other inputs. Information meeting the setup
and hold time requirements of the D inputs is transferred to the
Q outputs on the LOW-to-HIGH transition of the clock input.
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
55
0
25
25
125
70
C
IOH
Output Current -- High
54, 74
0.4
mA
IOL
Output Current -- Low
54
74
4.0
8.0
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54
0.7
V
Guaranteed Input LOW Voltage for
All Inputs
VIL
Input LOW Voltage
74
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK
Input Clamp Diode Voltage
0.65
1.5
V
VCC = MIN, IIN = 18 mA
VOH
Output HIGH Voltage
54
2.5
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOH
Output HIGH Voltage
74
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL
Output LOW Voltage
54, 74
0.25
0.4
V
IOL = 4.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VOL
Output LOW Voltage
74
0.35
0.5
V
IOL = 8.0 mA
VIN = VIL or VIH
per Truth Table
IIH
Input HIGH Current
20
A
VCC = MAX, VIN = 2.7 V
IIH
Input HIGH Current
0.1
mA
VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
0.4
mA
VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current (Note 1)
20
100
mA
VCC = MAX
ICC
Power Supply Current
27
mA
VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25
C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
fMAX
Maximum Input Clock Frequency
30
40
MHz
Figure 1
tPHL
Propagation Delay, MR to Q Output
18
27
ns
Figure 2
tPLH
tPHL
Propagation Delay, Clock to Output
17
18
27
27
ns
Figure 1
5-449
FAST AND LS TTL DATA
SN54/74LS273
AC SETUP REQUIREMENTS
(TA = 25
C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
tw
Pulse Width, Clock or Clear
20
ns
Figure 1
ts
Data Setup Time
20
ns
Figure 1
th
Hold Time
5.0
ns
Figure 1
trec
Recovery Time
25
ns
Figure 2
1.3 V
*The shaded areas indicate when the input is permitted to
*
change for predictable output performance.
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
CP
D
Qn
ts(H)
th(H)
ts(L)
th(L)
1/f max
tPLH
tPLH
tPHL
tPHL
MR
CP
Qn
Qn
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
trec
tPHL
tPLH
tW
1.3 V
1.3 V
1.3 V
*
tW
Figure 1. Clock to Output Delays, Clock Pulse Width,
Frequency, Setup and Hold Times Data to Clock
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
AC WAVEFORMS
DEFINITION OF TERMS
SETUP TIME (ts) -- is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW-to-HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) -- is defined as the minimum time following
the clock transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the correct
logic level may be released prior to the clock transition from
LOW-to-HIGH and still be recognized.
RECOVERY TIME (trec) -- is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer HIGH data to the Q outputs.
5-450
FAST AND LS TTL DATA
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. 751D 01, AND 02 OBSOLETE, NEW STANDARD
751D 03.
MIN
MIN
MAX
MAX
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
K
M
P
R
12.65
7.40
2.35
0.35
0.50
0.25
0.10
0
10.05
0.25
12.95
7.60
2.65
0.49
0.90
0.32
0.25
7
10.55
0.75
0.499
0.292
0.093
0.014
0.020
0.010
0.004
0
0.395
0.010
0.510
0.299
0.104
0.019
0.035
0.012
0.009
7
0.415
0.029
1.27 BSC
0.050 BSC
-A-
-B-
P
10 PL
1
10
11
20
G
-T-
D
20 PL
K
C
SEATING
PLANE
R X 45
M
F
J
Case 751D-03 DW Suffix
20-Pin Plastic
SO-20 (WIDE)
B
0.25 (0.010)
M
M
T
0.25 (0.010)
B
A
M
S
S
Case 732-03 J Suffix
20-Pin Ceramic Dual In-Line
NOTES:
1. LEADS WITHIN 0.25 mm (0.010) DIA., TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIM L TO CENTER OF LEADS WHEN FORMED
PARALLEL.
3. DIM A AND B INCLUDES MENISCUS.
MIN
MIN
MAX
MAX
MILLIMETERS
INCHES
DIM
23.88
6.60
3.81
0.38
1.40
0.51
0.20
3.18
25.15
7.49
5.08
0.56
1.65
1.27
0.30
4.06
0
0.25
0.940
0.260
0.150
0.015
0.055
0.020
0.008
0.125
0.990
0.295
0.200
0.022
0.065
0.050
0.012
0.160
15
1.02
2.54 BSC
7.62 BSC
0.100 BSC
0.300 BSC
A
B
C
D
F
G
H
J
K
L
M
N
0
0.010
15
0.040
B
C
D
G
H
J
M
N
A
L
20
11
1
10
SEATING
PLANE
K
F
Case 738-03 N Suffix
20-Pin Plastic
MIN
MIN
MAX
MAX
MILLIMETERS
INCHES
DIM
25.66
6.10
3.81
0.39
1.27
0.21
2.80
27.17
6.60
4.57
0.55
1.77
0.38
3.55
0
0.51
1.010
0.240
0.150
0.015
0.050
0.008
0.110
1.070
0.260
0.180
0.022
0.070
0.015
0.140
15
1.01
1.27 BSC
2.54 BSC
7.62 BSC
0.050 BSC
0.100 BSC
0.300 BSC
A
B
C
D
E
F
G
J
K
L
M
N
0
0.020
15
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L" TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B" DOES NOT INCLUDE MOLD
FLASH.
5. 738 02 OBSOLETE, NEW STANDARD 738 03.
-A-
B
C
K
N
E
G
F
D
20 PL
J
20 PL
L
M
-T-
SEATING
PLANE
1
10
11
20
T A
0.25 (0.010)
M
M
T B
0.25 (0.010)
M
M
5-451
FAST AND LS TTL DATA
SYMBOL
SW1
SW2
tPZH
Open
Closed
tPZL
Closed
Open
tPLZ
Closed
Closed
tPHZ
Closed
Closed
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