5-573
FAST AND LS TTL DATA
FOUR-BIT UP/DOWN COUNTER
WITH THREE-STATE OUTPUTS
The SN54 / 74LS569A is designed as programmable up/down BCD and
Binary counters respectively. These devices have 3-state outputs for use in
bus organized systems. With the exception of output enable (OE) and
asynchronous clear (ACLR), all functions occur on the positive edge of the
clock pulse (CP).
When the LOAD input is LOW, the outputs will be programmed by the
parallel data inputs (A, B, C, D) on the next clock edge. Enabling of the
counters occurs only when CEP and CET are LOW and LOAD is HIGH.
Direction of the count is controlled by the up-down input (U/D), HIGH counts
up and LOW counts down. High-speed counting and cascading is implement-
ed by internal look-ahead carry logic and an active LOW ripple carry output
(RCO). On the LS569A, the RCO is LOW at binary 15 during up-count and
during down-count it is also LOW at binary 0. During normal cascading
operation RCO connected to the succeeding block at CET is the only
requisite. When counting and when RCO is LOW, the clocked carry output
(CCO) provides a HIGH-LOW-HIGH pulse for a duration equal to the LOW
time of the clock pulse. Two active LOW reset lines are provided, a master
reset asynchronous clear (ACLR) and a synchronous clear (SCLR). When in
a HIGH state, the output control (OE) input forces the counter output into a
HIGH impedance state and when LOW, the counter outputs are enabled.
ESD > 3500 Volts
CONNECTION DIAGRAM (TOP VIEW)
18
17
16
15
14
13
1
2
3
4
5
6
7
20
19
8
VCC
U/D
RCO CCO OE YA
YC
YB
YD
CP
A
B
C
D CEP ACLR
9
10
SCLR GND
12
11
CET LOAD
VCC = PIN 20
GND = PIN 10
Note: Pin 1 is marked
for orientation.
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
55
0
25
25
125
70
C
IOH
Output Current -- High Except RCO, CCO
54
74
1.0
2.6
mA
IOH
Output Current -- High RCO, CCO
54, 74
0.44
mA
IOL
Output Current -- Low Except RCO, CCO
54
74
12
24
mA
IOL
Output Current -- Low, RCO, CCO
54
74
4.0
8.0
mA
SN54/74LS569A
FOUR-BIT UP / DOWN COUNTER
WITH THREE-STATE OUTPUTS
LOW POWER SCHOTTKY
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN
Plastic
SN74LSXXXDW SOIC
20
1
J SUFFIX
CERAMIC
CASE 732-03
20
1
N SUFFIX
PLASTIC
CASE 738-03
20
1
DW SUFFIX
SOIC
CASE 751D-03
5-574
FAST AND LS TTL DATA
SN54/74LS569A
FUNCTION TABLE
INPUTS
OUTPUTS
CP
D
C
B
A
LOAD
CET
CEP
U/D
ACLR
SCLR
OE
RCO
CCO
YD
YC
YB
YA
X
X
X
X
H
L
L
H
H
H
L
A/R
A/R
(QT CP) + 1
Count Up
X
X
X
X
H
L
L
L
H
H
L
A/R
A/R
(QT CP) 1
Count Down
X
X
X
X
H
H
X
X
H
H
L
H
H
NC
NC
NC
NC
Count Inhibit
X
X
X
X
H
L
H
X
H
H
L
A/R
H
NC
NC
NC
NC
Count Inhibit
X
X
X
X
X
L
L
H
H
H
L
L
H
H
H
H
Overflow
X
X
X
X
X
L
H
H
H
H
L
L
H
H
H
H
H
Overflow
X
X
X
X
X
H
X
H
H
H
L
H
H
H
H
H
H
Overflow Inhibit
X
X
X
X
X
L
L
L
H
H
L
L
L
L
L
L
Underflow
X
X
X
X
X
L
H
L
H
H
L
L
H
L
L
L
L
Underflow
X
X
X
X
X
H
X
L
H
H
L
H
H
L
L
L
L
Underflow Inhibit
L
H
L
H
L
X
X
X
H
H
L
H
H
L
H
L
H
Load Example
X
X
X
X
X
H
X
H
H
L
L
H
H
L
L
L
L
Clear (Synchronous)
X
X
X
X
X
L
L
L
H
L
L
L
L
L
L
L
Clear (Synchronous)
X
X
X
X
X
L
H
L
H
L
L
L
H
L
L
L
L
Clear (Synchronous)
X
X
X
X
X
H
X
L
H
L
L
H
H
L
L
L
L
Clear (Synchronous)
X
X
X
X
X
X
X
X
H
L
X
L
H
H
L
L
L
L
Asynchronous Clear
X
X
X
X
X
L
L
L
L
X
L
L
L
L
L
L
Asynchronous Clear
X
X
X
X
X
X
L
H
L
L
X
L
L
H
L
L
L
L
Asynchronous Clear
X
X
X
X
X
X
H
X
L
L
X
L
H
H
L
L
L
L
Asynchronous Clear
X
X
X
X
X
X
X
X
X
X
X
H
X
X
Hi-Z
Output Disabled
(QT -- CP) = Output state prior to clock edge
A/R = Assumes required output state;
X = Don't care
NC = No change
High except during Overflow and Underflow
LOGIC DIAGRAM
OE
ACLR
A
B
C
SCLR
LOAD
CEP
CET
CP
U/D
YA
YB
YC
YD
RCO
CCO
*
*
*
*
D
D
R
CP
Q
Q
*
5-575
FAST AND LS TTL DATA
SN54/74LS569A
DEFINITION OF FUNCTIONAL TERMS
A, B, C, D
The four programmable data inputs.
CEP
Count Enable Parallel. Can be used to
enable and inhibit counting in high speed
cascaded operation. CEP must be LOW to
count.
CET
Count Enable Trickle. Enables the ripple
carry output for cascaded operation. Must
be LOW to count.
CP
Clock Pulse. All synchronous functions
occur on the LOW-to-HIGH transition of the
clock.
LOAD
Enables parallel load of counter outputs
from data inputs on the next clock edge.
Must be HIGH to count.
U/D
Up/Down Count Control. HIGH counts up
and LOW counts down.
ACLR
Asynchronous Clear. Master reset of
counters to zero when ACLR is LOW,
independent of the clock.
SCLR
Synchronous clear of counters to zero on
the next clock edge when SCLR is LOW.
OE
A HIGH on the output control sets the four
counter outputs in the high impedance, and
a LOW, enables the output.
YA, YB, YC, YD The four counter outputs.
RCO
Ripple Carry Output. Output will be LOW on
the maximum count on up-count. Upon
down-count, RCO is LOW at 0000.
CCO
Clock Carry Output. While counting and
RCO is LOW, CCO will follow the clock
HIGH-LOW-HIGH transition.
Note: Actual current flow direction shown
DRIVING OUTPUT
DRIVING OUTPUT
DRIVEN INPUT
VCC
IOL
IOH
IOL
IOH IIL
IIH
LOW-POWER SCHOTTKY INPUT/OUTPUT
CURRENT INTERFACE CONDITIONS
5-576
FAST AND LS TTL DATA
SN54/74LS569A
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54
0.7
V
Guaranteed Input LOW Voltage for
All Inputs
VIL
Input LOW Voltage
74
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK
Input Clamp Diode Voltage
0.65
1.5
V
VCC = MIN, IIN = 18 mA
VOH
Output HIGH Voltage
YA
YD
54
2.4
3.4
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOH
Output HIGH Voltage
YA
YD
74
2.4
3.1
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOH
RCO,
CCO
54
2.5
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
RCO,
CCO
74
2.7
3.5
V
VOL
Output LOW Voltage
54, 74
0.25
0.4
V
IOL = IOL MAX
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VOL
Output LOW Voltage
74
0.35
0.5
V
IOL = IOL MAX
VIN = VIL or VIH
per Truth Table
IOZH
Output Off Current HIGH
20
A
VCC = MAX, VO = 2.7 V
IOZL
Output Off Current LOW
20
A
VCC = MAX, VO = 0.4 V
IIH
Input HIGH Current
20
A
VCC = MAX, VIN = 2.7 V
IIH
Input HIGH Current
0.1
mA
VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
Others
0.4
mA
VCC = MAX, VIN = 0.4 V
IIL
Input LOW Current
CET
0.8
mA
VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current
(Note 1)
RCO, CCO
20
100
mA
VCC = MAX
IOS
Short Circuit Current
(Note 1)
Others
30
130
mA
VCC = MAX
ICC
Power Supply Current, 3-State
43
mA
VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25
C)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
5-577
FAST AND LS TTL DATA
fMAX
Maximum Toggle Frequency
35
MHz
VCC = 5.0 V
CL = 45 pF
RL = 667
tPLH
tPHL
Propagation Delay
Clock to Q
15
20
ns
VCC = 5.0 V
CL = 45 pF
RL = 667
tPLH
tPHL
Propagation Delay
CET to RCO
14
15
ns
VCC = 5.0 V
CL = 45 pF
RL = 667
tPLH
tPHL
Propagation Delay
U/D to RCO
20
24
ns
VCC = 5.0 V
CL = 45 pF
RL = 667
tPLH
tPHL
Propagation Delay
Clock to RCO
20
25
ns
VCC = 5.0 V
CL = 45 pF
RL = 667
tPLH
tPHL
Propagation Delay
CET to CCO
16
28
ns
VCC = 5.0 V
CL = 45 pF
RL = 667
tPLH
tPHL
Propagation Delay
CEP to CCO
16
26
ns
tPLH
tPHL
Propagation Delay
Clock to CCO
15
17
ns
tPLH
tPHL
Propagation Delay
ACLR to Q
22
32
ns
tPZH
tPZL
Output Enable Time
15
20
ns
tPHZ
tPLZ
Output Disable Time
20
27
ns
CL = 5.0 pF
5-578
FAST AND LS TTL DATA
SN54/74LS569A
AC SETUP REQUIREMENTS
(TA = 25
C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
tW
Clock Pulse Width (Low)
20
ns
VCC = 5.0 V
ts
Setup Time, A, B, C, D
20
ns
VCC = 5.0 V
ts
Setup Time, SCLR
20
ns
VCC = 5.0 V
ts
Setup Time, LOAD
25
ns
VCC = 5.0 V
ts
Setup Time, U/D
30
ns
VCC = 5.0 V
ts
Setup Time, CET, CEP
20
ns
th
Hold Time, Any Inputs
0
ns
trec
ACLR
15
ns
MICROPROGRAMMABLE DUAL-EVENT 8-BIT COUNTERS
CP
LOAD1 U/D1 COUNT1
ACLR1
OE1
LOAD2 U/D2 COUNT2
ACLR2
OE2
8-BIT BUS
U/D
LOAD
CET
CEP
ACLR
OE
RCO
A-D
YA-D
4
4
4
4
4
4
4
4
8
8
CP
U/D
LOAD
CET
CEP
ACLR
OE
A-D
YA-D
CP
U/D
LOAD
CET
CEP
ACLR
OE
RCO
A-D
YA-D
CP
U/D
LOAD
CET
CEP
ACLR
OE
A-D
YA-D
LS569A
LS569A
LS569A
LS569A
5-579
FAST AND LS TTL DATA
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. 751D 01, AND 02 OBSOLETE, NEW STANDARD
751D 03.
MIN
MIN
MAX
MAX
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
K
M
P
R
12.65
7.40
2.35
0.35
0.50
0.25
0.10
0
10.05
0.25
12.95
7.60
2.65
0.49
0.90
0.32
0.25
7
10.55
0.75
0.499
0.292
0.093
0.014
0.020
0.010
0.004
0
0.395
0.010
0.510
0.299
0.104
0.019
0.035
0.012
0.009
7
0.415
0.029
1.27 BSC
0.050 BSC
-A-
-B-
P
10 PL
1
10
11
20
G
-T-
D
20 PL
K
C
SEATING
PLANE
R X 45
M
F
J
Case 751D-03 DW Suffix
20-Pin Plastic
SO-20 (WIDE)
B
0.25 (0.010)
M
M
T
0.25 (0.010)
B
A
M
S
S
Case 732-03 J Suffix
20-Pin Ceramic Dual In-Line
NOTES:
1. LEADS WITHIN 0.25 mm (0.010) DIA., TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIM L TO CENTER OF LEADS WHEN FORMED
PARALLEL.
3. DIM A AND B INCLUDES MENISCUS.
MIN
MIN
MAX
MAX
MILLIMETERS
INCHES
DIM
23.88
6.60
3.81
0.38
1.40
0.51
0.20
3.18
25.15
7.49
5.08
0.56
1.65
1.27
0.30
4.06
0
0.25
0.940
0.260
0.150
0.015
0.055
0.020
0.008
0.125
0.990
0.295
0.200
0.022
0.065
0.050
0.012
0.160
15
1.02
2.54 BSC
7.62 BSC
0.100 BSC
0.300 BSC
A
B
C
D
F
G
H
J
K
L
M
N
0
0.010
15
0.040
B
C
D
G
H
J
M
N
A
L
20
11
1
10
SEATING
PLANE
K
F
Case 738-03 N Suffix
20-Pin Plastic
MIN
MIN
MAX
MAX
MILLIMETERS
INCHES
DIM
25.66
6.10
3.81
0.39
1.27
0.21
2.80
27.17
6.60
4.57
0.55
1.77
0.38
3.55
0
0.51
1.010
0.240
0.150
0.015
0.050
0.008
0.110
1.070
0.260
0.180
0.022
0.070
0.015
0.140
15
1.01
1.27 BSC
2.54 BSC
7.62 BSC
0.050 BSC
0.100 BSC
0.300 BSC
A
B
C
D
E
F
G
J
K
L
M
N
0
0.020
15
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L" TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B" DOES NOT INCLUDE MOLD
FLASH.
5. 738 02 OBSOLETE, NEW STANDARD 738 03.
-A-
B
C
K
N
E
G
F
D
20 PL
J
20 PL
L
M
-T-
SEATING
PLANE
1
10
11
20
T A
0.25 (0.010)
M
M
T B
0.25 (0.010)
M
M
5-580
FAST AND LS TTL DATA
SYMBOL
SW1
SW2
tPZH
Open
Closed
tPZL
Closed
Open
tPLZ
Closed
Closed
tPHZ
Closed
Closed
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