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MM908E624
Internal Rev 4.0, 12/2004
Freescale Semiconductor
Technical Data
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
Freescale Semiconductor, Inc., 2004. All rights reserved.
Integrated Triple High-Side
Switch with Embedded MCU
and LIN Serial Communication
for Relay Drivers
The 908E624 is an integrated single-package solution that
includes a high-performance HC08 microcontroller with a
SMARTMOS
TM
analog control IC. The HC08 includes flash memory,
a timer, enhanced serial communications interface (ESCI), an
analog-to-digital converter (ADC), serial peripheral interface (SPI)
(only internal), and an internal clock generator module. The analog
control die provides three high-side outputs with diagnostic functions,
voltage regulator, watchdog, operational amplifier, and local
interconnect network (LIN) physical layer.
The single-package solution, together with LIN, provides optimal
application performance adjustments and space-saving PCB design.
It is well suited for the control of automotive high-current motors
applications using relays (e.g., window lifts, fans, and sun roofs).
Features
High-Performance M68HC908EY16 Core
16 K Bytes of On-Chip Flash Memory
512 Bytes of RAM
Internal Clock Generator Module
Two 16-Bit, 2-Channel Timers
10-Bit Analog-to-Digital Converter (ADC)
LIN Physical Layer Interface
Low Dropout Voltage Regulator
Three High-Side Outputs
Two Wake-Up Inputs
16 Microcontroller I/Os
Figure 1. 908E624 Simplified Application Diagram
TRIPLE HIGH-SIDE SWITCH WITH
EMBEDDED MCU AND LIN
908E624
ORDERING INFORMATION
Device
Temperature
Range (T
A
)
Package
MM908E624ACDWB/R
-40C to 85C
54 SOICW
DW SUFFIX
98ASA99294D
54-TERMINAL SOICW
M
PTD1/TACH1
PTA0
-4
PWMin
PTD0/TACH0
IRQB_A
IRQB
RSTB_A
RSTB
PTE1/RxD
RxD
GND
EVSS
VSSA
VREFL
VDD
EVDD
VDDA
VREFH
LIN
HS3
L1
L2
HS1
HS2
+E
OUT
-E
WDCONF
VSUP1
VSUP2
VBAT
LIN
Interface
Microcontroller
Ports
To Microcontroller A/D Channel
+5.0 V
VCC
AGND
PTB1;3
-7
PTC2
-4
Analog Integrated Circuit Device Data
2
Freescale Semiconductor
908E624
Internal Block Diagram
INTERNAL BLOCK DIAGRAM
Cont
rol
and S
t
at
us Regi
st
er
,

64 B
y
t
e
s
User Fl
ash,

15,
8
72 B
y
t
e
s
User RA
M
,

512 B
y
t
e
s
M
o
ni
t
o
r ROM
,

310
B
y
t
e
s
User Fl
ash V
e
ct
or S
pace
,

36
B
y
t
e
s
FLA
S
H
program
m
i
ng (burn i
n
) ROM
,
1024 B
y
t
e
s
5
-
B
i
t K
e
y
b
o
a
r
d
In
te
r
r
u
p
t
Mo
d
u
le
2-channel
Ti
m
e
r I
n
t
e
rf
ace
Mo
d
u
le
A
Se
cu
ri
t
y
M
o
d
u
l
e
2-channel
Ti
m
e
r I
n
t
e
rf
ace
Mo
d
u
le
B
M68HC08 CPU
CPU
Regi
st
ers
AL
U
P
e
ri
odi
c Wakeup Ti
m
e
base
Mo
d
u
le
Arb
i
t
e
r M
o
d
u
l
e
S
e
ri
al
P
heri
p
heral
I
n
t
e
rf
ace
Mo
d
u
le
P
r
escal
e
r M
o
dul
e
In
te
r
n
a
l
C
l
o
c
k
G
e
n
e
r
a
to
r
Mo
d
u
le
Com
p
ut
er Operat
i
n
g
P
r
operl
y
M
o
dul
e
Si
n
g
l
e
Br
e
a
kp
o
i
n
t
Bre
a
k
Mo
d
u
le
Po
we
r
-
O
n
Re
se
t
M
o
d
u
l
e
2
4
In
te
r
n
a
l
S
y
s
t
e
m
I
n
t
e
grat
i
o
n M
o
dul
e
10 B
i
t
A
n
al
og-t
o-Di
gi
t
a
l
Convert
e
r M
odul
e
E
n
hanced S
e
ri
al
Com
m
uni
c
at
i
o
n I
n
t
e
rf
ace
Mo
d
u
le
PTB
6
/AD
6
/TBC
H0
VREFL
VSSA
EVSS
EVDD
VDDA
VREFH
PTB
7
/AD
7
/TBC
H1
PT
B
5
/AD
5
PT
B
4
/AD
4
PT
B
3
/AD
3
PT
A
0
/
KBD
0
PT
A
1
/
KBD
1
PT
A2
/KBD
2
PT
A3
/KBD
3
PT
A4
/KBD
4
PT
D
1
/T
AC
H
1
PT
C
4
/OSC
1
PT
C
3
/OSC
2
F
L
SVPP
PT
A
5
/
SPSC
K
PT
C
1
/
M
OSI
PT
C
0
/M
ISO
PT
E0
/T
XD
S
i
n
g
le
E
x
te
r
n
a
l
IR
Q
Mo
d
u
le
Conf
i
g
urat
i
o
n Regi
st
er
Mo
d
u
le
B
E
MF Mo
d
u
le
POR
T A
DDRA
OS
C
2
OS
C
1
RS
T
PO
W
E
R
IRQ
VR
EF
H
V
DDA
VR
EF
L
VSSA
VD
D
VSS
PORT
B
DDRB
PT
A6
/
S
S
PT
A5
/
S
PSCK
PT
A4
/
K
BD
4
PT
A3
/
K
BD
3
PT
A2
/
K
BD
2
PT
A1
/
K
BD
1
PT
A0
/
K
BD
0
P
T
B
7
/A
D
7
/T
B
C
H
1
P
T
B
6
/A
D
6
/T
B
C
H
0
PT
B5
/
A
D
5
PT
B4
/
A
D
4
PT
B3
/
A
D
3
PT
B2
/
A
D
2
PT
B1
/
A
D
1
PT
B0
/
A
D
0
PORT
C
POR
T D
DDRC
DDRD
PT
C4
/
O
SC
1
PT
C3
/
O
SC
2
PT
C2
/
M
CL
K
PT
C1
/
M
O
S
I
PT
C0
/
M
I
S
O
DDRE
PORT
E
PT
D1
/
T
ACH
1
PT
D0
/
T
ACH
0
PT
E1
/
R
x
D
PT
E0
/
T
x
D
Inte
rn
al
Bus
PTD0/TACH0
PTE1/RXD
Vol
t
age
Re
g
u
la
t
o
r
SPI
&
M
o
de C
o
ntr
o
l
Re
se
t
Co
n
t
ro
l
Mo
d
u
le
W
i
ndow
W
a
tc
hdog
W
a
ke
Up
Input 1
VD
D
L1
WDCONF
PWMIN
VSUP2
GND
LIN
TX
D
SPSC
K
MO
S
I
MI
S
O
RXD
IRQ
RST
IRQ_A
RST_A
SS
PT
C
2
/M
C
L
K
PT
B1
/AD
1
PT
A6
/SS
VC
C
+E
-E
OU
T
W
a
ke
Up
Input 2
L2
VSUP1
Hig
h
S
i
d
e
Drive
r
&
D
i
agnos
ti
c
HS
1
VSU
P
2
PW
M
I
N
VSU
P
1
L
I
N Ph
ysica
l
Lay
er
AGND
H
i
gh Si
de
Drive
r
&
D
i
agnos
t
i
c
HS
2
H
i
gh Si
de
Drive
r
&
D
i
agnos
t
i
c
HS
3
PW
M
I
N
VSU
P
2
VSU
P2
Amplifier
Analog Die
MCU Die
F
i
gu
re
2.
9
08E6
24
Simp
lified
Inte
rna
l

Bloc
k
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
908E624
Terminal Connections
TERMINAL CONNECTIONS
Figure 3. Terminal Connections
Table 1. Terminal Definitions
A functional description of each terminal can be found in the
Functional Terminal Description
section beginning on page
17
.
Die
Terminal
Terminal Name
Formal Name
Definition
MCU
1
2
6
7
8
11
PTB7/AD7/TBCH1
PTB6/AD6/TBCH0
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTB1/AD1
Port B I/Os
These terminals are special-function, bidirectional I/O port terminals
that are shared with other functional modules in the MCU.
MCU
3
4
5
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
Port C I/Os
These terminals are special-function, bidirectional I/O port terminals
that are shared with other functional modules in the MCU.
MCU
9
IRQ
External Interrupt
Input
This terminal is an asynchronous external interrupt input terminal.
MCU
10
RST
External Reset
This terminal is bidirectional, allowing a reset of the entire system. It is
driven low when any internal reset source is asserted.
MCU
12
13
PTD0/TACH0
PTD1/TACH1
Port D I/Os
These terminals are special-function, bidirectional I/O port terminals
that are shared with other functional modules in the MCU.
--
14, 15, 16,
20, 21, 22,
32, 41
NC
No Connect
Not connected.
MCU
42
PTE1/RXD
Port E I/O
This terminal is a special-function, bidirectional I/O port terminal that
can is shared with other functional modules in the MCU.
PTA0/KBD0
PTA1/KBD1
PTA2/KBD2
PTA3/KBD3
PTA4/KBD4
VREFH
VDDA
EVDD
EVSS
VSSA
VREFL
PTE1/RXD
NC
RXD
WDCONF
+E
-E
OUT
VCC
AGND
VDD
NC
VSUP1
GND
LIN
VSUP2
FLSVPP
PTB7/AD7/TBCH1
PTB6/AD6/TBCH0
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
PTB5/AD5
PTB4/AD4
PTB3/AD3
IRQ
RST
PTB1/AD1
PTD0/TACH0
PTD1/TACH1
NC
NC
NC
PWMIN
RST_A
IRQ_A
NC
NC
NC
L1
L2
HS3
HS2
HS1
1
11
12
13
14
15
16
17
18
19
20
9
10
21
22
23
24
25
26
27
6
7
8
4
5
2
3
54
44
43
42
41
40
39
38
37
36
35
46
45
34
33
32
31
30
29
28
49
48
47
51
50
53
52
Analog Integrated Circuit Device Data
4
Freescale Semiconductor
908E624
Terminal Connections
MCU
43
48
VREFL
VREFH
ADC References
These terminals are the reference voltage terminals for the analog-to-
digital converter (ADC).
MCU
44
47
VSSA
VDDA
ADC Supply
Terminals
These terminals
are the power supply terminals for the analog-to-digital
converter.
MCU
45
46
EVSS
EVDD
MCU Power Supply
Terminals
These terminals are the ground and power supply terminals,
respectively. The MCU operates from a single-power supply.
MCU
49
50
52
53
54
PTA4/KBD4
PTA3/KBD3
PTA2/KBD2
PTA1/KBD1
PTA0/KBD0
Port A I/Os
These terminals are special-function, bidirectional I/O port terminals
that are shared with other functional modules in the MCU.
MCU
51
FLSVPP
Test Terminal
For test purposes only. Do not connect in the application.
Analog
17
PWMIN
Direct High-Side
Control Input
This terminal allows the enabling and PWM control of the high-side HS1
and HS2 terminals.
Analog
18
RST_A
Internal Reset Output This terminal is the reset output terminal of the analog die.
Analog
19
IRQ_A
Internal Interrupt
Output
This terminal is the interrupt output terminal of the analog die indicating
errors or wake-up events.
Analog
23
24
L1
L2
Wake-Up Inputs
These terminals are the wake-up inputs of the analog chip.
Analog
25
26
27
HS3
HS2
HS1
High-Side Output
These output terminals are low R
DS(ON)
high-side switches.
Analog
31
28
VSUP1
VSUP2
Power Supply
Terminals
These terminals are device power supply terminals.
Analog
29
LIN
LIN Bus
This terminal represents the single-wire bus transmitter and receiver.
Analog
30
34
GND
AGND
Power Ground
Terminals
These terminals are device power ground connections.
Analog
33
VDD
Voltage Regulator
Output
The +5.0 V voltage regulator output terminal is intended to supply the
embedded microcontroller.
Analog
35
VCC
Amplifier Power
Supply
This terminal is the single +5.0 V power supply for the operational
amplifier.
Analog
36
OUT
Amplifier Output
This terminal is the output of the operational amplifier.
Analog
37
38
-E
+E
Amplifier Inputs
These terminals are the amplifier inverted and non-inverted inputs.
Analog
39
WDCONF
Watchdog
Configuration
Terminal
This input terminal is for configuration of the watchdog period and
allows the disabling of the watchdog.
Analog
40
RXD
LIN Transceiver
Output
This terminal is the output of LIN transceiver.
Table 1. Terminal Definitions (continued)
A functional description of each terminal can be found in the
Functional Terminal Description
section beginning on page
17
.
Die
Terminal
Terminal Name
Formal Name
Definition
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
908E624
Maximum Ratings
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding limits on any terminal may cause permanent
damage to the device.
Rating
Symbol
Value
Unit
Electrical Ratings
Supply Voltage
Analog Chip Supply Voltage under Normal Operation (Steady-State)
Analog Chip Supply Voltage under Transient Conditions
MCU Chip Supply Voltage
V
SUP(SS)
V
SUP(
PK)
V
DD
-0.3 to 27
-0.3 to 40
-0.3 to 5.5
V
Input Terminal Voltage
Analog Chip
Microcontroller Chip
V
IN(ANALOG)
V
IN(MCU)
-0.3 to V
DD
+0.3
V
SS
-0.3 to V
DD
+0.3
V
Maximum Microcontroller Current per Terminal
All Terminals except VDD, VSS, PTA0:PTA6, PTC0:PTC1
PTA0:PTA6, PTC0:PTC1 Terminals
I
PIN(1)
I
PIN(2)
15
25
mA
Maximum Microcontroller VSS Output Current
I
MVSS
100
mA
Maximum Microcontroller VDD Input Current
I
MVDD
100
mA
Current Sense Amplifier
Maximum Input Voltage, +E, -E Terminals
Maximum Input Current, +E, -E Terminals
Maximum Output Voltage, OUT Terminal
Maximum Output Current, OUT Terminal
V
+E-E
I
+E-E
V
OUT
I
OUT
-0.3 to 7.0
20
-0.3 to V
CC
+0.3
20
V
mA
V
mA
LIN Supply Voltage
Normal Operation (Steady-State)
Transient Input Voltage (per ISO7637 Specification) and with
External Components
(Figure 4,
page
15)
V
BUS(SS)
V
BUS(
PK)
-18 to 40
-150 to 100
V
L1 and L2 Terminal Voltage
Normal Operation with a 33 k
resistor
(Steady-State)
Transient Input Voltage (per ISO7637 Specification) and with
External Components
(Figure 4,
page
15)
V
WAKE(SS)
V
WAKE(PK)
-18 to 40
-100 to 100
V
ESD Voltage
Human Body Model
(1)
Machine Model
(2)
Charge Device Model
(3)
V
ESD1
V
ESD2
V
ESD3
2000
100
500
V
Notes
1.
ESD1 testing is performed in accordance with the Human Body Model (C
ZAP
= 100 pF, R
ZAP
= 1500
).
2.
ESD2 testing is performed in accordance with the Machine Model (C
ZAP
=200 pF, R
ZAP
= 0
).
3.
ESD3 testing is performed in accordance with Charge Device Model, Robotic (C
ZAP
= 4.0 pF).
Analog Integrated Circuit Device Data
6
Freescale Semiconductor
908E624
Maximum Ratings
Thermal Ratings
Operating Ambient Temperature
T
A
-40 to 85
C
Operating Junction Temperature
(4)
Analog
MCU
T
J(ANALOG)
T
J(MCU)
-40 to 150
-40 to 125
C
C
Storage Temperature
T
STG
-40 to 150
C
Peak Package Reflow Temperature During Solder Mounting
(5)
T
SOLDER
245
C
Thermal Resistance, Junction to Ambient
(6)
,
(7)
R
JA
36
C/ W
Notes
4.
Die temperature of analog and MCU is linked via the package. High temperature on analog die can lead to a high MCU temperature.
5.
Terminal soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
6.
All power outputs ON and dissipating equal power.
7.
Per JEDEC JESD51-2 at natural convection, still air condition; and 2s2p thermal test board per JEDEC JESD51-7.
Table 2. Maximum Ratings (continued)
All voltages are with respect to ground unless otherwise noted. Exceeding limits on any terminal may cause permanent
damage to the device.
Rating
Symbol
Value
Unit
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
908E624
Static Electrical Characteristics
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller
chip. Characteristics noted under conditions 9.0 V
V
SUP
16 V, -40
C
T
J
125
C unless otherwise noted. Typical values
noted reflect the approximate parameter mean at T
A
= 25
C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Supply Voltage Range
Nominal Operating Voltage
V
SUP
5.5
--
18
V
Functional Operating Voltage
(8)
V
SUPOP
--
--
27
V
Supply Current Range
Normal Mode
(9)
V
SUP
= 13.5 V, Analog Chip in Normal Mode, MCU Operating Using
Internal Oscillator at 32 MHz (8.0 MHz Bus Frequency), SPI, ESCI, ADC
Enabled
Stop Mode
(9)
,
(10)
V
SUP
= 13.5 V
Sleep Mode
(9)
,
(10)
V
SUP
= 13.5 V
I
RUN
I
STOP
I
SLEEP
--
--
--
20
60
35
--
75
45
mA
A
A
Digital Interface Ratings (Analog Die)
Output Terminal RST_A
Low-State Output Voltage (I
OUT
= -1.5 mA)
High-State Output Current (V
OUT
> 3.5 V)
Pulldown Current Limitation
V
OL
I
OH
I
OL_MAX
--
--
-1.5
--
250
--
0.4
--
-8.0
V
A
mA
Output Terminal IRQ_A
Low-State Output Voltage (I
OUT
= -1.5 mA)
High-State Output Voltage (I
OUT
= 250
A)
V
OL
V
OH
--
3.85
--
--
0.4
--
V
Output Terminal RXD
Low-State Output Voltage (I
OUT
= -1.5 mA)
High-State Output Voltage (I
OUT
= 250
A)
Capacitance
(11)
V
OL
V
OH
C
IN
--
3.85
--
--
--
4.0
0.4
--
--
V
V
pF
Input Terminal PWMIN
Input Logic Low Voltage
Input Logic High Voltage
Input Current
Capacitance
(11)
V
IL
V
IH
I
IN
C
IN
--
3.5
-10
--
--
--
--
4.0
1.5
--
10
--
V
V
A
pF
Terminal TXD, SSPullup Current
I
PULLUP
--
40
--
A
Notes
8.
Device is fully functional. All functions are operating. Overtemperature may occur.
9.
Total current (I
VSUP1
+ I
VSUP2
) measured at GND terminal.
10.
Stop and Sleep mode current will increase if V
SUP
exceeds 15 V.
11.
This parameter is guaranteed by process monitoring but is not production tested.
Analog Integrated Circuit Device Data
8
Freescale Semiconductor
908E624
Static Electrical Characteristics
System Resets and Interrupts
Low-Voltage Reset (LVR)
Threshold
V
LVRON
3.6
4.0
4.4
V
Low-Voltage Interrupt (LVI)
Threshold
Hysteresis
V
LVI
V
LVI_
HYS
5.7
--
6.0
1.0
6.6
--
V
High-Voltage Interrupt (HVI)
Threshold
Hysteresis
V
HVI
V
HVI_
HYS
18
--
19.25
220
20.5
--
V
mV
Voltage Regulator
(12)
Normal Mode Output Voltage
2.0 mA < I
DD
< 50 mA, 5.5 V < V
SUP
< 27 V
V
DDRUN
4.75
5.0
5.25
V
Normal Mode Output Current Limitation
(13)
I
DDRUN
50
110
200
mA
Dropout Voltage
(14)
I
DD
= 50 mA
V
DDDROP
--
0.1
0.2
V
Stop Mode Output Voltage
(15)
V
DDSTOP
4.75
5.0
5.25
V
Stop Mode Regulator Current Limitation
I
DDSTOP
4.0
8.0
14
mA
Line Regulation
Normal Mode, 5.5 V < V
SUP
< 27 V, I
DD
= 10 mA
Stop Mode, 5.5 V < V
SUP
< 27 V, I
DD
= 2.0 mA
LR
RUN
LR
STOP
--
--
20
10
150
100
mV
Load Regulation
Normal Mode, 1.0 mA < I
DD
< 50 mA, V
SUP
= 18 V
Stop Mode, 1.0 mA < I
DD
< 5 mA, V
SUP
= 18 V
LD
RUN
LD
STOP
--
--
40
40
150
150
mV
Overtemperature Pre-Warning (Junction)
(16)
T
PRE
120
135
160
C
Thermal Shutdown Temperature (Junction)
(16)
T
SD
155
170
C
Temperature Threshold Difference
T
SD
-T
PRE
TSD-TPRE
20
30
45
C
Notes
12.
Specification with external capacitor 1.0
F< C < 10 F and 200 m ESR 1.0 . Capacitor value up to 47 F can be used.
13.
Total VDD regulator current. A 5.0 mA current for operational amplifier is included. Digital output supplied from VDD.
14.
Measured when voltage has dropped 100 mV below its nominal value.
15.
When switching from Normal to Stop mode or from Stop mode to Normal mode, the output voltage can vary within the output voltage
specification.
16.
This parameter is guaranteed by process monitoring but not production tested
Table 3. Static Electrical Characteristics (continued)
All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller
chip. Characteristics noted under conditions 9.0 V
V
SUP
16 V, -40
C
T
J
125
C unless otherwise noted. Typical values
noted reflect the approximate parameter mean at T
A
= 25
C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
908E624
Static Electrical Characteristics
Window Watchdog Configuration Terminal (WDCONF)
External Resistor Range
R
EXT
10
--
100
k
Watchdog Period Accuracy with External Resistor (Excluding Resistor
Accuracy)
(17)
WD
CACC
-15
--
15
%
LIN Physical Layer
LIN Transceiver Output Level
Recessive State, TXD HIGH, I
OUT
= 1.0
A
Dominant State, TXD LOW, 500
External Pullup Resistor
V
LIN_REC
V
LIN_DOM
V
SUP
-1
--
--
--
--
1.4
V
Normal Mode Pullup Resistor to V
SUP
R
PU
20
30
60
k
Stop, Sleep Mode Pullup Current Source
I
PU
--
2.0
--
A
Output Current Shutdown Threshold
I
OV-CUR
50
75
150
mA
Output Current Shutdown Delay
I
OV-DELAY
--
10
--
s
Leakage Current to GND
VSUP Disconnected, V
BUS
at 18 V
Recessive State, V
SUP
8.0 V to 18 V, V
BUS
8.0 V to 18 V, V
BUS
V
SUP
GND Disconnected, V
GND
= V
SUP
, V
BUS
at -18 V
I
BUS
--
0
-1.0
1.0
3.0
--
10
20
1.0
A
LIN Receiver
Receiver Threshold Dominant
Receiver Threshold Recessive
Receiver Threshold Center
Receiver Threshold Hysteresis
V
BUS_DOM
V
BUS_REC
V
BUS_CNT
V
BUS_HYS
--
0.6
0.475
--
--
--
0.5
--
0.4
--
0.525
0.175
V
SUP
Notes
17.
Watchdog timing period calculation formula: P
WD
= 0.991
*
R
EXT
+0.648 (R
EXT
in k
and P
WD
in ms).
Table 3. Static Electrical Characteristics (continued)
All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller
chip. Characteristics noted under conditions 9.0 V
V
SUP
16 V, -40
C
T
J
125
C unless otherwise noted. Typical values
noted reflect the approximate parameter mean at T
A
= 25
C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Analog Integrated Circuit Device Data
10
Freescale Semiconductor
908E624
Static Electrical Characteristics
High-Side Outputs HS1 and HS2
Switch On Resistance
T
J
= 25
C, I
LOAD
= 150 mA, V
SUP
> 9.0 V
T
J
= 125
C, I
LOAD
= 150 mA, V
SUP
> 9.0 V
T
J
= 125
C, I
LOAD
= 120 mA, 5.5 V < V
SUP
> 9.0 V
R
DS(ON)
--
--
--
2.0
--
3.0
2.5
4.5
--
Output Current Limit
I
LIM
300
--
600
mA
Overtemperature Shutdown
(18)
,
(19)
T
HSSD
155
--
190
C
Leakage Current
I
LEAK
--
--
10
A
High-Side Output HS3
Switch On Resistance
T
J
= 25
C, I
LOAD
= 50 m A, V
SUP
> 9.0 V
T
J
= 125
C, I
LOAD
= 50 mA, V
SUP
> 9.0 V
T
J
= 125
C, I
LOAD
= 30 mA, 5.5 V < V
SUP
> 9.0 V
R
DS(ON)
--
--
--
--
--
--
7.0
10
14
Output Current Limitation
I
LIM
60
100
200
mA
Overtemperature Shutdown
(18)
,
(19)
T
HSSD
155
--
190
C
Leakage Current
I
LEAK
--
--
10
A
Output Clamp Voltage
I
OUT
= -100 mA
V
CL
-6.0
--
--
V
Notes
18.
This parameter is guaranteed by process monitoring but it is not production tested
19.
When overtemperature occurs, switch is turned off and latched off. Flag is set in SPI.
Table 3. Static Electrical Characteristics (continued)
All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller
chip. Characteristics noted under conditions 9.0 V
V
SUP
16 V, -40
C
T
J
125
C unless otherwise noted. Typical values
noted reflect the approximate parameter mean at T
A
= 25
C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
908E624
Static Electrical Characteristics
Sense Current Amplifier
Rail to Rail Input Voltage
V
IMC
-0.1
--
V
CC
+0.1
V
Output Voltage Range
Output Current 1.0 mA
Output Current 5.0 mA
V
OUT1
V
OUT2
0.1
0.3
--
--
V
CC
-0.1
V
CC
-0.3
V
Input Bias Current
I
B
--
--
250
nA
Input Offset Current
I
O
-100
--
100
nA
Input Offset Voltage
V
IO
-25
--
25
mV
Supply Voltage Rejection Ratio
(20)
SVR
60
--
--
dB
Common Mode Rejection Ratio
(20)
CMR
70
--
--
dB
Gain Bandwidth
(20)
GBP
1.0
--
--
MHz
Slew Rate
SR
0.5
--
--
V/
s
Phase Margin (for Gain = 1, Load 100 pF/ /5.0 k
(20)
PHMO
40
--
--
Open Loop Gain
OLG
--
85
--
dB
L1 and L2 Inputs
Negative Switching Threshold
5.5 V < V
SUP
< 6.0 V
6.0 V < V
SUP
< 18 V
18 V < V
SUP
< 27 V
V
THN
2.0
2.5
2.7
2.5
3.0
3.2
3.0
3.5
3.7
V
Positive Switching Threshold
5.5 V < V
SUP
< 6.0 V
6.0 V < V
SUP
< 18 V
18 V < V
SUP
< 27 V
V
THP
2.7
3.0
3.5
3.3
4.0
4.2
3.8
4.5
4.7
V
Hysteresis
5.5 V < V
SUP
< 27 V
V
HYST
0.5
--
1.3
V
Input Current
-0.2 V < V
IN
< 40 V
I
IN
-10
--
10
A
Notes
20.
This parameter is guaranteed by process monitoring but is not production tested.
Table 3. Static Electrical Characteristics (continued)
All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller
chip. Characteristics noted under conditions 9.0 V
V
SUP
16 V, -40
C
T
J
125
C unless otherwise noted. Typical values
noted reflect the approximate parameter mean at T
A
= 25
C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Analog Integrated Circuit Device Data
12
Freescale Semiconductor
908E624
Dynamic Electrical Characteristics
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the
microcontroller chip. Characteristics noted under conditions 9.0 V
V
SUP
16 V, -40
C
T
J
125
C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at T
A
= 25
C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LIN Physical Layer
Driver Characteristics for Normal Slew Rate
(21)
,
(22)
Dominant Propagation Delay TXD to LIN
t
DOM-
MIN
--
--
50
s
Dominant Propagation Delay TXD to LIN
t
DOM-
MAX
--
--
50
s
Recessive Propagation Delay TXD to LIN
t
REC-
MIN
--
--
50
s
Recessive Propagation Delay TXD to LIN
t
REC-
MAX
--
--
50
s
Propagation Delay Symmetry: t
DOM-MIN
- t
REC-
MAX
dt1
-10.44
--
--
s
Propagation Delay Symmetry: t
DOM-
MAX
- t
REC-
MIN
dt2
--
--
11
s
Driver Characteristics for Slow Slew Rate
(21)
,
(23)
Dominant Propagation Delay TXD to LIN
t
DOM-
MIN
--
--
100
s
Dominant Propagation Delay TXD to LIN
t
DOM-
MAX
--
--
100
s
Recessive Propagation Delay TXD to LIN
t
REC-
MIN
--
--
100
s
Recessive Propagation Delay TXD to LIN
t
REC-
MAX
--
--
100
s
Propagation Delay Symmetry: t
DOM-
MIN
- t
REC-
MAX
dt1s
-22
--
--
s
Propagation Delay Symmetry: t
DOM-MAX
- t
REC-
MIN
dt2s
--
--
23
s
Driver Characteristics for Fast Slew Rate
LIN High Slew Rate (Programming Mode)
SR
FAST
--
15
--
V/
s
Receiver Characteristics and Wake-Up Timings
Receiver Dominant Propagation Delay
(24)
t
RL
--
3.5
6.0
s
Receiver Recessive Propagation Delay
(24)
t
RH
--
3.5
6.0
s
Receiver Propagation Delay Symmetry
t
R-SYM
-2.0
--
2.0
s
Bus Wake-Up Deglitcher
t
PROP
WL
35
80
s
Bus Wake-Up Event Reported
(25)
t
WAKE
--
20
--
s
Notes
21.
V
SUP
from 7.0 V to 18 V, bus load R0 and C0 1.0 nF/1.0 k
, 6.8 nF/660 , 10 nF/500 . Measurement thresholds: 50% of TXD signal
to LIN signal threshold defined at each parameter.
22.
See
Figure 6
, page
15
.
23.
See
Figure 7
, page
16
.
24.
Measured between LIN signal threshold V
IL
or V
IH
and 50% of RXD signal.
25.
t
WAKE
is typically 2 internal clock cycles after LIN rising edge detected. See
Figure 8
and
Figure 9
, page
16
. In Sleep mode the V
DD
rise time is strongly dependent upon the decoupling capacitor at VDD terminal.
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
908E624
Dynamic Electrical Characteristics
SPI Interface Timing
SPI Operating Recommended Frequency
f
SPIOP
0.25
--
4.0
MHz
L1 AND L2 INPUTS
Wake-Up Filter Time
(26)
t
WUF
8.0
20
38
s
Window Watchdog Configuration Terminal (WDCONF)
Watchdog Period
External Resistor R
EXT
= 10 k
(1%)
External Resistor R
EXT
= 100 k
(1%)
Without External Resistor R
EXT
(WDCONF Terminal Open)
P
WD
--
--
97
10.558
99.748
150
--
--
205
ms
State Machine Timing
Reset Low-Level Duration after V
DD
High
t
RST
0.65
1.0
1.35
ms
Interrupt Low-Level Duration
t
INT
7.0
10
13
s
Normal Request Mode Timeout
NR
TOUT
97
150
205
ms
Delay Between SPI Command and HS1/HS2/HS3 Turn On
(27)
,
(28)
t
S-HS
ON
--
3.0
10
s
Delay Between SPI Command and HS1/HS2/HS3 Turn Off
(27)
,
(28)
t
S-HS
OFF
--
3.0
10
s
Delay Between Normal Request and Normal Mode After W/D Trigger
Command
(29)
t
S-NR2N
6.0
35
70
s
Delay Between SS Wake-Up (SS LOW to HIGH) and Normal Request Mode
(VDD On and Reset High)
t
W-SSB
15
40
80
s
Delay Between SS Wake-Up (SS LOW to HIGH) and First Accepted SPI
Command
t
W-SPI
90
--
N/A
s
Delay Between Interrupt Pulse and First SPI Command Accepted
t
S-1STSPI
30
--
N/A
s
Minimum Time Between Two Rising Edges on SS
t
2SSB
15
--
--
s
Notes
26.
This parameter is guaranteed by process monitoring but is not production tested.
27.
Delay between turn-on or turn-off command and high-side on or high-side off, excluding rise or fall time due to external load.
28.
Delay between the end of the SPI command (rising edge of the SS) and start of device activation/deactivation.
29.
This parameter is guaranteed by process monitoring but it is not production tested.
Table 4. Dynamic Electrical Characteristics (continued)
All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the
microcontroller chip. Characteristics noted under conditions 9.0 V
V
SUP
16 V, -40
C
T
J
125
C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at T
A
= 25
C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Analog Integrated Circuit Device Data
14
Freescale Semiconductor
908E624
Microcontroller Parametrics
MICROCONTROLLER PARAMETRICS
Table 5. Microcontroller
For a detailed microcontroller description, refer to the MC68HC908EY16 datasheet.
Module
Description
Core
High-Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0 MHz
Timer
Two 16-Bit Timers with 2 Channels (TIM A and TIM B)
Flash
16 K Bytes
RAM
512 Bytes
ADC
10-Bit Analog-to-Digital Converter
SPI
SPI Module
ESCI
Standard Serial Communication Interface (SCI) Module
Bit-Time Measurement
Arbitration
Prescaler with Fine Baud-Rate Adjustment
ICG
Internal Clock Generation Module
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
908E624
Timing Diagrams
TIMING DIAGRAMS
Figure 4. Test Circuit for Transient Test Pulses
Figure 5. Test Circuit for LIN Timing Measurements
Figure 6. LIN Timing Measurements for Normal Slew Rate
LIN, L1, and L2
10k
1nF
Transient Pulse
Generator
Note Waveform in accordance with ISO7637 Part 1, Test Pulses 1, 2, 3a, and 3b.
10 k
1.0 nF
R0
C0
VSUP
RXD
TXD
LIN
R0 and C0 combinations:
- 1k Ohm and 1nF
- 660 Ohm and 6.8nF
- 500 Ohm and 10nF
R0 and C0 Combinations:
1.0 k
and 1.0 nF
600
and 6.8 nF
500
and 10 nF
Tdom-min
Tdom-max
TrL
TXD
LIN
RXD
Vrec
TrH
Trec-min
Trec-max
58.1% Vsup
40% Vsup
28.4% Vsup
42.2% Vsup
60% Vsup
74.4% Vsup
V
LIN_REC
t
DOM-MIN
58.1% V
SUP
40% V
SUP
28.4% V
SUP
t
DOM-MAX
42.4% V
SUP
60% V
SUP
74.4% V
SUP
t
REC-MAX
t
REC-MIN
t
RH
t
RL
Analog Integrated Circuit Device Data
16
Freescale Semiconductor
908E624
Timing Diagrams
Figure 7. LIN Timing Measurements for Slow Slew Rate
Figure 8. Wake-Up Sleep Mode Timing
Figure 9. Wake-Up Stop Mode Timing
Tdom-min
Tdom-max
TrL
TXD
LIN
RXD
Vrec
TrH
Trec-min
Trec-max
58.1% Vsup
40% Vsup
28.4% Vsup
42.2% Vsup
60% Vsup
74.4% Vsup
V
LIN_REC
t
DOM-MIN
61.6% V
SUP
40% V
SUP
25.1% V
SUP
t
DOM-MAX
38.9% V
SUP
60% V
SUP
77.8% V
SUP
t
REC-MAX
t
REC-MIN
t
RH
t
RL
VDD
LIN
Vrec
TpropWL
Twake
Dominant level
0.4VSUP
V
LIN_REC
0.4 V
SUP
Dominant Level
t
PROP
WL
t
WAKE
IRQ_A
LIN
Vrec
TpropWL
Twake
Dominant level
0.4VSUP
t
PROP
WL
t
WAKE
Dominant Level
0.4 V
SUP
V
LIN_REC
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
908E624
Functional Description
Introduction
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 908E624 was designed and developed as a highly
integrated and cost-effective solution for automotive and
industrial applications. For automotive body electronics, the
908E624 is well suited to perform relay control in applications
like window lift, sunroof, etc., via a three-wire LIN bus.
The device combines an HC908EY16 MCU core with flash
memory together with a SmartMOS IC chip. The SmartMOS
IC chip combines power and control in one chip. Power
switches are provided on the SmartMOS IC configured as
high-side outputs. Other ports are also provided, which
include an operational amplifier port and two wake-up
terminals. An internal voltage regulator provides power to the
MCU chip.
Also included in this device is a LIN physical layer, which
communicates using a single wire. This enables this device
to be compatible with three-wire bus systems, where one wire
is used for communication, one for battery, and one for
ground.
FUNCTIONAL TERMINAL DESCRIPTION
See
Figure 1, 908E624 Simplified Application Diagram
,
page
1
, for a graphic representation of the various terminals
referred to in the following paragraphs. Also, see the terminal
diagram on
page 3
for a depiction of the terminal locations on
the package.
PORT A I/O TERMINALS
These terminals are special-function, bidirectional I/O port
terminals that are shared with other functional modules in the
MCU. PTA0:PTA4 are shared with the keyboard interrupt
terminals KBD0:KBD4.
The PTA5/SPSCK terminal is not accessible in this device
and is internally connected to the SPI clock terminal of the
analog die. The PTA6/
SS
terminal is likewise
not accessible.
For details refer to the 68HC908EY16 datasheet.
PORT B I/O TERMINALS
These terminals are special-function, bidirectional I/O port
terminals that are shared with other functional modules in the
MCU. All terminals are shared with the ADC module. The
PTB6:PTB7 terminals are also shared with the Timer B
module.
The PTB0/AD0 and PTB2/AD2 terminals are not
accessible in this device.
For details refer to the 68HC908EY16 datasheet.
PORT C I/O TERMINALS
These terminals are special-function, bidirectional I/O port
terminals that are shared with other functional modules in the
MCU.
For example, PTC2:PTC4 are shared with the ICG
module.
PTC0/MISO and PTC1/MOSI are not accessible in this
device and are internally connected to the MISO and MOSI
SPI terminals of the analog die.
For details refer to the 68HC908EY16 datasheet.
PORT D I/O TERMINALS
PTD1/TACH1 and PTD0/TACH0/BEMF are special-
function, bidirectional I/O port terminals that can also be
programmed to be timer terminals.
For details refer to the 68HC908EY16 datasheet.
PORT E I/O TERMINAL
PTE1/RXD and PTE0/TXD are special-function,
bidirectional I/O port terminals that can also be programmed
to be enhanced serial communication.
PTE0/TXD is internally connected to the TXD terminal of
the analog die.
The connection for the receiver must be done
externally.
For details refer to the 68HC908EY16 datasheet.
EXTERNAL INTERRUPT TERMINAL (IRQ)
The
IRQ
terminal is an asynchronous external interrupt
terminal. This terminal contains an internal pullup resistor that
is always activated, even when the
IRQ
terminal is pulled
LOW.
For details refer to the 68HC908EY16 datasheet.
EXTERNAL RESET TERMINAL (RST)
A logic [0] on the
RST
terminal forces the MCU to a known
startup state. It is driven LOW when any internal reset source
is asserted.
This terminal contains an internal pullup resistor that is
always activated, even when the reset terminal is pulled
LOW.
Important
To ensure proper operation, do not add any
external pullup resistor.
For details refer to the 68HC908EY16 datasheet.
MCU POWER SUPPLY TERMINALS (EVDD AND
EVSS)
EVDD
and EVSS
are the power supply and ground
terminals, respectively. The MCU operates from a single-
power supply.
Analog Integrated Circuit Device Data
18
Freescale Semiconductor
908E624
Functional Description
Functional Terminal Description
Fast signal transitions on MCU terminals place high, short-
duration current demands on the power supply. To prevent
noise problems, take special care to provide power supply
bypassing at the MCU.
For details refer to the 68HC908EY16 datasheet.
ADC SUPPLY TERMINALS (VDDA AND VSSA)
VDDA and VSSA
are the power supply terminals for the
analog-to-digital converter (ADC). It is recommended that a
high-quality ceramic decoupling capacitor be placed between
these terminals.
Important
VDDA is the supply for the ADC and should be
tied to the same potential as EVDD via separate traces.
VSSA is the ground terminal for the ADC and should be tied
to the same potential as EVSS via separate traces.
For details refer to the 68HC908EY16 datasheet.
ADC REFERENCE TERMINALS (VREFL AND
VREFH)
VREFL and VREFH are the reference voltage terminals for
the ADC. It is recommended that a high-quality ceramic
decoupling capacitor be placed between these terminals.
Important
VREFH is the high reference supply for the
ADC and should be tied to the same potential as VDDA via
separate traces. VREFL is the low reference supply for the
ADC and should be tied to the same potential as VSSA via
separate traces.
For details refer to the 68HC908EY16 datasheet.
TEST TERMINAL (FLSVPP)
This terminal is for test purposes only. Do not connect in
the application.
PWMIN TERMINAL
This terminal is the direct PWM input for high-side
outputs 1 and 2 (HS1 and HS2). If no PWM control is
required, PWMIN must be connected to VDD to enable the
HS1 and HS2 outputs.
LIN TRANSCEIVER OUTPUT TERMINAL (RXD)
This terminal is the output of LIN transceiver. The terminal
must be connected to the microcontroller's Enhanced Serial
Communications Interface (ESCI) module (RXD terminal).
RESET TERMINAL (RST_A)
RST_A
is the reset output terminal of the analog die and
must be connected to the
RST
terminal of the MCU.
Important
To ensure proper operation, do not add any
external pullup resistor.
INTERRUPT TERMINAL (IRQ_A)
IRQ_A
is the interrupt output terminal of the analog die
indicating errors or wake-up events. This terminal must be
connected to the
IRQ
terminal of the MCU.
WINDOW WATCHDOG CONFIGURATION
TERMINAL (WDCONF)
This terminal is the configuration terminal for the internal
watchdog. A resistor is connected to this terminal. The
resistor value defines the watchdog period. If the terminal is
open, the watchdog period is fixed to its default value.
The watchdog can be disabled (e.g., for flash
programming or software debugging) by connecting this
terminal to GND.
POWER SUPPLY TERMINALS (VSUP1 AND
VSUP2)
This VSUP1 power supply terminal supplies the voltage
regulator, the internal logic, and LIN transceiver.
This VSUP2 power supply terminal is the positive supply
for the high-side switches.
POWER GROUND TERMINAL (GND)
This terminal is the device ground connection.
HIGH-SIDE OUTPUT TERMINALS (HS1 AND HS2)
These terminals are high-side switch outputs to drive loads
such as relays or lamps. Each switch is protected with
overtemperature and current limit (overcurrent). The output
has an internal clamp circuitry for inductive load. The HS1
and HS2 outputs are controlled by SPI and have a direct
enabled input (PWMIN) for PWM capability.
HIGH-SIDE OUTPUT TERMINAL (HS3)
This high-side switch can be used to drive small lamps,
Hall-effect sensors, or switch pullup resistors. The switch is
protected with overtemperature and current limit
(overcurrent). The output is controlled only by SPI.
LIN BUS TERMINAL (LIN)
The LIN terminal represents the single-wire bus
transmitter and receiver. It is suited for automotive bus
systems and is based on the LIN bus specification.
WAKE-UP TERMINALS (L1 AND L2)
These terminals are high-voltage capable inputs used to
sense external switches and to wake up the device from
Sleep or Stop mode. During Normal mode the state of these
terminals can be read through SPI.
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
908E624
Functional Description
Functional Terminal Description
SENSE AMPLIFIER TERMINALS (E+, E-, OUT, VCC)
These are the terminals of the single-supply sense
amplifier.
The E+ and E- input terminals are the non-inverting and
inverting inputs of the amplifier, respectively.
The OUT terminal is the output terminal of the current
sense amplifier.
The VCC terminal is the +5.0 V single-supply
connection.
+5.0 V VOLTAGE REGULATOR OUTPUT
TERMINAL (VDD)
The VDD terminal is needed to place an external capacitor
to stabilize the regulated output voltage. The VDD terminal is
intended to supply the embedded microcontroller. The
terminal is protected against shorts to GND with an integrated
current limit (temperature shutdown could occur).
Important
The VDD, EVDD, VDDA, and VREFH terminals
must be connected together.
VOLTAGE REGULATOR AND SENSE AMPLIFIER
GROUND TERMINAL (AGND)
The AGND terminal is the ground terminal of the voltage
regulator and the Sense Amplifier.
Important
GND, AGND, VSS, EVSS, VSSA, and VREFL
terminals must be connected together.
Analog Integrated Circuit Device Data
20
Freescale Semiconductor
908E624
Functional Description
Functional Device Operation
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
908E624 ANALOG DIE MODES OF OPERATION
The 908E624 offers three operating modes: Normal (Run),
Stop, and Sleep. In Normal mode the device is active and is
operating under normal application conditions. The Stop and
Sleep modes are low-power modes with wake-up
capabilities.
In Stop mode the voltage regulator still supplies the MCU
with V
DD
(limited current capability) and in Sleep mode the
voltage regulator is turned off (V
DD
= 0 V).
Wake-up from Stop mode is initiated by a wake-up
interrupt. Wakeup from Sleep mode is done by a reset and
the voltage regulator is turned back on.
The selection of the different modes is controlled by the
MODE1:2 bits in the SPI Control register.
Figure 10
describes how transitions are done between the
different operating modes and
Table 6
, page
21
, gives an
overview of the operating mode.
Figure 10. Operating Modes and Transitions
Reset
Power
Down
Notes:
WD - means Watchdog
WD disabled - means Watchdog disabled (WDCONF terminal connected to GND)
WD trigger means Watchdog is triggered by SPI command
WD failed means no Watchdog trigger or trigger occurs in closed window
STOP Command - means STOP command sent via SPI
SLEEP Command - means SLEEP command send via SPI
Wake-Up - means L1 or L2 state change or LIN bus wake up or SS rising edge
Normal
Request
V
DD
High and Reset Delay (t
RST
) expired
Normal
Normal Request timeout expired (NR
TOUT
)
W
D
tri
gge
r
Sleep
Wake-Up (Reset)
Stop
V
DD
Low
V
DD
Low (>NR
TOUT
) expired
and VSUV = 0
SLEEP Command
V
DD
Low
S
T
O
P
Comm
and
W
a
k
e
-U
p Int
e
rru
p
t
WD dis
a
b
l
ed
V
DD
Low
WD failed
Normal Request Timeout Expired (NR
TOUT
)
V
DD
High and
Reset Delay (t
RST
) Expired
V
DD
Low
V
DD
Low
WD Failed
V
DD
LOW (>NR
TOUT
) Expired
and LVF = 0
Sleep Command
Sl
e
ep Comma
nd
Wake-Up (Reset)
W
D
T
r
i
g
ger
WD
Di
s
abl
ed
Power Up
W
a
ke-
U
p I
n
t
e
r
r
upt
Legend
WD: Watchdog
WD Disabled: Watchdog disabled (WDCONF terminal connected to GND)
WD Trigger: Watchdog is triggered by SPI command
WD Failed: No watchdog trigger or trigger occurs in closed window
Stop Command: Stop command sent via SPI
Sleep Command: Sleep command sent via SPI
Wake-Up: L1 or L2 state change or LIN bus wake-up or
SS
rising edge
V
DD
Low
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
908E624
Functional Description
Functional Device Operation
INTERRUPTS
In Normal (Run) mode the 908E624 has four different
interrupt sources. An interrupt pulse on the
IRQ_A
terminal is
generated to report a fault to the MCU. All interrupts are not
maskable and cannot be disabled.
After an Interrupt the INTSRC bit in the SPI Status register
is set, indicating the source of the event. This interrupt source
information is only transferred once, and the INTSRC bit is
cleared automatically.
Low-Voltage Interrupt
Low-voltage interrupt (LVI) is related to external supply
voltage VSUP1. If this voltage falls below the LVI threshold,
it will set the LVF bit in the SPI Status register and an interrupt
will be initiated. The LVF bit remains set as long as the Low-
voltage condition is present.
During Sleep and Stop mode the low-voltage interrupt
circuitry is disabled.
High-Voltage Interrupt
High-voltage interrupt (HVI) is related to external supply
voltage VSUP1. If this voltage rises above the HVI threshold,
it will set the HVF bit in the SPI Status register and an
interrupt will be initiated. The HVF bit remains set as long as
the high-voltage condition is present.
During Sleep and Stop mode the low-voltage interrupt
circuitry is disabled.
Wake-Up Interrupts
In Stop mode the
IRQ_A
terminal reports wake-up events
on the L1, L2, or the LIN bus to the MCU. All wake-up
interrupts are not maskable and cannot be disabled.
After a wake-up interrupt, the INTSRC bit in the Serial
Peripheral Interface (SPI) Status register is set, indicating the
source of the event. This wake-up source information is only
transferred once, and the INTSRC bit is cleared
automatically.
Figure 11
, page
22
, describes the Stop/Wake-Up
procedure.
VOLTAGE REGULATOR TEMPERATURE
PREWARNING (VDDT)
Voltage regulator temperature prewarning (VDDT) is
generated if the voltage regulator temperature is above the
T
PRE
threshold, it will set the VDDT bit in the SPI Status
register and an interrupt will be initiated. The VDDT bit
remains set as long as the error condition is present.
During Sleep and Stop mode the voltage regulator
temperature prewarning circuitry is disabled.
HIGH-SIDE SWITCH THERMAL SHUTDOWN
(HSST)
The high-side switch thermal shutdown HSST is
generated if one of the high-side switches HS1:HS3 is above
the HSST threshold, it will shutdown the corresponding High-
side switch, set the HSST flag in the SPI Status register and
an interrupt will be initiated. The HSST bit remains set as long
as the error condition is present.
During Sleep and Stop mode the high-side switch thermal
shutdown circuitry is disabled.
Table 6. Operating Modes Overview
Device
Mode
Voltage Regulator
Wake-Up
Capabilities
RST_A
Output
Watchdog
Function
HS1, HS2,
and HS3
LIN Interface
Sense
Amplifier
Reset
V
DD
ON
N/A
LOW
Disabled
Disabled
Recessive only
Not active
Normal
Request
V
DD
ON
N/A
HIGH
150 ms time out if
WD enabled
Enabled
Transmit and
receive
Not active
Normal
(Run)
V
DD
ON
N/A
HIGH
Window WD if
enabled
Enabled
Transmit and
receive
Active
Stop
V
DD
ON with limited
current capability
LIN wake-up,
L1, L2 state change,
SS
rising edge
HIGH
Disabled
Disabled
Recessive state with
wake-up capability
Not active
Sleep
V
DD
OFF
LIN wake-up
L1, L2 state change
LOW
Disabled
Disabled
Recessive state with
wake-up capability
Not active
Analog Integrated Circuit Device Data
22
Freescale Semiconductor
908E624
Functional Description
Functional Device Operation
Figure 11. Stop Mode/Wake-Up Procedure
ANALOG DIE INPUTS/OUTPUTS
High-Side Output Terminals HS1 and HS2
These are two high-side switches used to drive loads such
as relays or lamps. They are protected with overtemperature
and current limit (overcurrent) and include an active internal
clamp circuitry for inductive load drive. Control is done using
the SPI Control register. PWM capability is offered through
the PWMIN input terminal.
The high-side switch is turned on if both the HSxON bit in
the SPI Control register is set and the PWMIN input is HIGH
(refer to
Figure 12
, page
23
). In order to have HS1 on, the
PWMIN must be HIGH and bit HS1ON must be set. The
same applies to the HS2 output.
If no PWM control is required, PWMIN must be connected
to the VDD terminal.
Current Limit (Overcurrent) Protection
These high-side switches feature current limit to protect
them against overcurrent and short circuit conditions.
Overtemperature Protection
If an overtemperature condition occurs on any of the three
high-side switches, the faulty switch is turned off and latched
off until the HS1 (or HS2 or HS3) bit is set to "1" in the SPI
Control register. The failure is reported by the HSST bit in the
SPI Control register.
Sleep and Stop Mode
In Sleep and Stop modes the high-sides are disabled.
High-Side Output HS3
This high-side switch can be used to drive small lamps,
Hall-effect sensors, or switch pullup resistors. Control is done
using the SPI Control register. No direct PWM control is
possible on this terminal (refer to
Figure 13
, page
23
).
Current Limit (Overcurrent) Protection
This high-side feature switch feature current limit to protect
it against overcurrent and short circuit conditions.
Overtemperature Protection
If an overtemperature condition occurs on any of the three
high-side switches, the faulty switch is turned off and latched
off until the HS3 (or HS1 or HS2) bit is set to "1" in the SPI
Control register. The failure is reported by the HSST bit in the
SPI Control register.
Sleep and Stop Mode
In Sleep and Stop mode the high-side is disabled.
From Reset
initialize
operate
SPI:
2x STOP
Command
STOP
IRQ
interrupt
?
SPI: reason for
interrupt
operate
Switch to VREG
low current mode
Assert IRQ
Switch to VREG
high current mode
MCU
Power Die
Wake Up on
LIN or L1, L2?
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
908E624
Functional Description
Functional Device Operation
.
Figure 12. High-Side HS1 and HS2 Circuitry
.
Figure 13. High-Side HS3 Circuitry
WINDOW WATCHDOG
The window watchdog is configurable using an external
resistor at the WDCONF terminal. The watchdog is cleared
through by the MODE1:2 bits in the SPI Control register (refer
to
Table 8
, page
26
).
A watchdog clear is only allowed in the open window. If the
watchdog is cleared in the closed window or has not been
cleared at the end of the open window, the watchdog will
generate a reset on the
RST_A
terminal and reset the whole
device.
Note
The watchdog clear in Normal request mode
(150 ms) (first watchdog clear) has no window.
Figure 14. Window Watchdog Operation
VSUP2
HSx
High-Side Driver
Charge Pump,
Current Limit Protection,
Overtemperature Protection
Control
On/Off
Status
MODE1:2
HSxON
PWMIN
VSUP2
HS3
High-Side Driver
Charge Pump,
Current Limit Protection,
Overtemperature Protection
Control
On/Off
Status
MODE1:2
HS3ON
Window closed
no watchdog clear allowed
Window open
for watchdog clear
WD timing x 50%
WD timing x 50%
WD period (P
WD
)
WD timing selected by resistor on WDCONF terminal.
Analog Integrated Circuit Device Data
24
Freescale Semiconductor
908E624
Functional Description
Functional Device Operation
Watchdog Configuration
If the WDCONF terminal is left open, the default watchdog
period is selected (typ. 150 ms). If no watchdog function is
required, the WDCONF terminal must be connected to GND.
The watchdog period is calculated using the following
formula:
P
WD
[ms] = 0.991
*
R
EXT
[k
] + 0.648
VOLTAGE REGULATOR
The 908E624 chip contains a low-power, low dropout
voltage regulator to provide internal power and external
power for the MCU. The on-chip regulator consist of two
elements, the main voltage regulator and the low-voltage
reset circuit.
The V
DD
regulator accepts an unregulated input supply
and provides a regulated V
DD
supply to all digital sections of
the device. The output of the regulator is also connected to
the VDD terminal to provide the 5.0 V to the microcontroller.
Current Limit (Overcurrent) Protection
The voltage regulator has current limit to protect the device
against overcurrent and short circuit conditions.
Overtemperature Protection
The voltage regulator also features an overtemperature
protection having an overtemperature warning (Interrupt -
VDDT) and an overtemperature shutdown.
Stop Mode
During Stop mode the Stop mode regulator supplies a
regulated output voltage. The Stop mode regulator has a
limited output current capability.
Sleep Mode
In Sleep mode the voltage regulator external V
DD
is turned
off.
FACTORY TRIMMING AND CALIBRATION
To enhance the ease-of-use of the 908E624, various
parameters (e.g., ICG trim value) are stored in the flash
memory of the device. The following flash memory locations
are reserved for this purpose and might have a value different
from the "empty" (0xFF) state:
0xFD80:0xFDDF Trim and Calibration Values
0xFFFE:0xFFFF Reset Vector
In the event the application uses these parameters, one
has to take care not to erase or override these values. If these
parameters are not used, these flash locations can be erased
and otherwise used.
OPERATING MODES OF THE MCU
For a detailed description of the operating modes of the
MCU, refer to the MC68HC908EY16 datasheet.
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
908E624
Functional Description
Functional Device Operation
LOGIC COMMANDS AND REGISTERS
908E624 SPI INTERFACE AND CONFIGURATION
The serial peripheral interface creates the communication
link between the microcontroller and the analog die of the
908E624.
The interface consists of four terminals (see
Figure 15
):
SS
--Slave Select
MOSI--Master-Out Slave-In
MISO--Master-In Slave-Out
SPSCK--Serial Clock
A complete data transfer via the SPI consists of 1 byte.
The master sends 8 bits of control information and the slave
replies with 8 bits of status data.
Figure 15. SPI Protocol
During the inactive phase of the
SS
(High), the new data
transfer is prepared.
The falling edge of the
SS
indicates the start of a new data
transfer and puts the MISO in the low-impedance state and
latches the analog status data (Register read data).
With the rising edge of the SPI clock, SPSCK the data is
moved to MISO/MOSI terminals. With the falling edge of the
SPI clock SPSCK the data is sampled by the Receiver.
The data transfer is only valid if exactly 8 sample clock
edges are present in the active (low) phase of
SS
.
The rising edge of the slave select
SS
indicates the end of
the transfer and latches the write data (MOSI) into the
register The
SS
high forces MISO to the high impedance
state.
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Register write data
Register read data
Rising edge of SPSCK
Change MISO/MOSI Output
Falling edge of SPSCK
Sample MISO/MOSI Input
Write data latch
SS
MOSI
MISO
SPSCK
Read data latch
Analog Integrated Circuit Device Data
26
Freescale Semiconductor
908E624
Functional Description
Functional Device Operation
SPI REGISTER OVERVIEW
Table 7
summarizes the SPI Register bit meaning, reset
value, and bit reset condition.
.
SPI Control Register (Write)
Table 8
shows the SPI Control register bits by name.
LINSL2:1--LIN Baud Rate and Low-Power Mode
Selection Bits
These bits select the LIN slew rate and requested low-
power mode in accordance with
Table 9
. Reset clears the
LINSL2:1 bits.
LIN-PU--LIN Pullup Enable Bit
This bit controls the LIN pullup resistor during Sleep and
Stop modes.
1 = Pullup disconnected in Sleep and Stop modes.
0 = Pullup connected in Sleep and Stop modes.
HS3ON:HS1ON--High-Side H3:HS1 Enable Bit
This bit enables the HSx. Reset clears the HSx bit.
1 = HSx switched on (refer to Note below).
0 = HSx switched off.
Note
If no PWM on HS1 and HS2 is required, the PWMIN
terminal must be connected to the VDD terminal.
MODE2:1--Mode Section Bits
The MODE2:1 bits control the operating modes and the
watchdog in accordance with
Table 10
.
To safely enter Sleep or Stop mode and to ensure that
these modes are not affected by noise issue during SPI
transmission, the Sleep/Stop commands require two SPI
transmissions.
Table 7. SPI Register Overview
Read/Write
Information
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Write
LINSL2
LINSL1
LIN-PU
HS3ON
HS2ON
HS1ON
MODE2
MODE1
Read
INTSRC
(30)
LINWU
or
LINFAIL
HVF
LVF
or
BATFAIL
(31)
VDDT
HSST
L2
L1
Write Reset Value
0
0
0
0
0
0
--
--
Write Reset Condition
POR,
RESET
POR,
RESET
POR
POR, RESET
POR,
RESET
POR,
RESET
--
--
Notes
30.
D7 signals interrupts and wake-up interrupts, D6:D0 indicated the source.
31.
The first SPI read after reset returns the BATFAIL flag state on bit D4.
Table 8. Control Bits Function (Write Operation)
D7
D6
D5
D4
D3
D2
D1
D0
LINSL2 LINSL1 LIN-PU HS3ON HS2ON HS1ON MODE2 MODE1
Table 9. LIN Baud Rate and Low-Power Mode Selection
Bits
LINSL2
LINSL1
Description
0
0
Baud Rate up to 20 kbps (normal)
0
1
Baud Rate up to 10 kbps (slow)
1
0
Fast Program Download
Baud Rate up to 100 kbps
1
1
Low-Power Mode (Sleep or Stop) Request
Table 10. Mode Selection Bits
MODE2
MODE1
Description
0
0
Sleep Mode
(32)
0
1
Stop Mode
(32)
1
0
Watchdog Clear
(33)
1
1
Run (Normal) Mode
Notes
32.
To enter Sleep and Stop mode, a special sequence of SPI
commands is implemented.
33.
The device stays in Run (Normal) mode.
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
908E624
Functional Description
Functional Device Operation
Sleep Mode Sequence
The Sleep command, as shown in
Table 11
, has to be sent
twice.
Stop Mode Sequence
The Stop command, as shown in
Table 12
, has to be sent
twice.
SPI Status Register (Read)
Table 13
shows the SPI Status register bits by name.
INTSCR --Register Content Flags or Interrupt Source
This bit indicates if the register contents reflect the flags or
an interrupt/wake-up interrupt source.
1 = D6:D0 reflects the interrupt or wake-up source.
0 = No interrupt occurred. Other SPI bits report real time
status.
LINWU/LINFAIL--LIN Status Flag Bit
This bit indicates a LIN wake-up condition.
1 = LIN bus wake-up occurred or LIN overcurrent/
overtemperature occurred.
0 = No LIN bus wake-up occurred.
HVF --High-Voltage Flag Bit
This flag is set on an overvoltage (VSUP1) condition.
1 = High-voltage condition has occurred.
0 = no High-voltage condition.
LVF/BATFAIL--Low-Voltage Flag Bit
This flag is set on an undervoltage (VSUP1) condition.
1 = Low-voltage condition has occurred.
0 = No low-voltage condition.
VDDT--Voltage Regulator Status Flag Bit
This flag is set as pre-warning in case of an over-
temperature condition on the voltage regulator.
1 = Voltage regulator overtemperature condition, pre-
warning.
0 = No overtemperature detected.
HSST--High-Side Status Flag Bit
This flag is set on overtemperature conditions on one of
the high-side outputs.
1 = HSx off due to overtemperature.
0 = No overtemperature.
L2:L1-- Wake-Up Inputs L1, L2 Status Flag Bit
These flags reflect the status of the L2 and L1 input
terminals and indicate the wake-up source.
1 = L2:L1 input high or wake-up by L2:L1 (first register
read after wake-up indicated with INTSRC = 1).
0 = L2:L1 input low.
Table 11. Sleep Command Bits
LINSL2 LINSL1 LIN-PU HS3ON HS2ON HS1ON MODE
2
MODE
1
1
1
x
x
x
x
0
0
x = Don't care.
Table 12. Stop Command Bits
LINSL2 LINSL1 LIN-PU
HS3O
N
HS2O
N
HS1O
N
MODE2 MODE1
1
1
x
x
x
x
0
1
x = Don't care.
Table 13. Control Bits Function (Read Operation)
D7
D6
D5
D4
D3
D2
D1
D0
INTSRC
LINWU
or
LINFAIL
HVF
LVF
or
BATFAIL
VDDT
HSST
L2
L1
Analog Integrated Circuit Device Data
28
Freescale Semiconductor
908E624
Package Dimensions
PACKAGE DIMENSIONS
Important
For the most current revision of the package,
visit www.freescale.com and do a keyword search on the 98A
drawing number below.
CASE 1365-01
ISSUE O
DATE 09/19/01
NOTES:
1.
ALL DIMENSIONS ARE IN MILLIMETERS.
2.
DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3.
DATUMS B AND C TO BE DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT THE
PLASTIC BODY.
4.
THIS DIMENSION DOES NOT INCLUDE MOLD FLASH,
PROTRUSION OR GATE BURRS. MOLD FLASH,
PROTRUSION OR GATE BURRS SHALL NOT EXCEED
0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED
AT THE PLANE WHERE THE BOTTOM OF THE LEADS
EXIT THE PLASTIC BODY.
5.
THIS DIMENSION DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSIONS. INTERLEAD FLASH AND
PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER
SIDE. THIS DIMENSION IS DETERMINED AT THE
PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE
PLASTIC BODY.
6.
THIS DIMENSION DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46
MM. DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN
PROTRUSION AND ADJACENT LEAD SHALL NOT LESS
THAN 0.07 MM.
7.
EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8.
THESE DIMENSIONS APPLY TO THE FLAT SECTION
OF THE LEAD BETWEEN 0.1 MM AND 0.3 MM FROM
THE LEAD TIP.
9.
THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM. THIS DIMENSION IS
DETERMINED AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE
BAR BURRS, GATE BURRS AND INTER-LEAD FLASH,
BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
CL
17.8
7.4
1
27
28
54
0.10
A
2.35
SEATING
PLANE
0.9
SECTION B-B
0.65
R0.08 MIN
B
A
(0.29)
0.38
0.30
(0.25)
PLATING
BASE METAL
SECTION A-A
ROTATED 90 CLOCKWISE
8
0.25
0.22
9
5
0.13
M
C
A B
6
A
C
7.6
18.0
9
4
10.3
5.15
A
54X
52X
2.65
0.3 A
2X 27 TIPS
B C
B
B
0.29
0.13
0.5
0
8
0
0.25
GAUGE PLANE
MIN
PIN 1 INDEX
DWB SUFFIX
54-TERMINAL SOIC WIDE BODY
PLASTIC PACKAGE
98ASA99294D
ISSUE O
MM908E624DWTAD
Rev 2.0, 12/2004
Freescale Semiconductor
Technical Data
Freescale Semiconductor, Inc., 2004. All rights reserved.
Integrated Triple High-Side
Switch with Embedded MCU
and LIN Serial Communication
for Relay Drivers
Introduction
This package is a dual die package. There are two heat sources in
the package independently heating with P
1
and P
2
. This results in two
junction temperatures, T
J1
and T
J2
, and a thermal resistance matrix
with R
JAmn
.
For m, n = 1, R
JA11
is the thermal resistance from Junction 1 to
the reference temperature while only heat source 1 is heating with P
1
.
For m = 1, n = 2, R
JA12
is the thermal resistance from Junction 1
to the reference temperature while heat source 2 is heating with P
2
.
This applies to R
J21
and R
J22
, respectively.
The stated values are solely for a thermal performance
comparison of one package to another in a standardized
environment. This methodology is not meant to and will not predict
the performance of a package in an application-specific environment.
Stated values were obtained by measurement and simulation
according to the standards listed below.
54-TERMINAL
SOICW
908E624DW
DW SUFFIX
98ASA99294D
54-TERMINAL SOICW
Note
For package dimensions, refer to the 908E624
device datasheet.
T
J1
T
J2
=
R
JA11
R
JA21
R
JA12
R
JA22
.
P
1
P
2
Standards
Table 1. Thermal Performance Comparison
Thermal
Resistance
1 = Power Chip, 2 = Logic Chip (
C/W)
m = 1,
n = 1
m = 1, n = 2
m = 2, n = 1
m = 2,
n = 2
R
JAmn
40
31
36
R
JBmn
25
16
21
R
JAmn
57
47
52
R
JCmn
21
12
16
Analog Integrated Circuit Device Data
32
Freescale Semiconductor
908E624DW
Figure 1. Thermal Test Board
Device on Thermal Test Board
R
JAmn
is the thermal resistance between die junction and
ambient air.
This device is a dual die package. Index m indicates the die
that is heated. Index n refers to the number of the die where
the junction temperature is sensed.
908E624 Terminal Connections
54-Terminal SOICW
0.65 mm Pitch
17.9 mm x 7.5 mm Body
PTA0/KBD0
PTA1/KBD1
PTA2/KBD2
PTA3/KBD3
PTA4/KBD4
VREFH
VDDA
EVDD
EVSS
VSSA
VREFL
PTE1/RXD
NC
RXD
WDCONF
+E
-E
OUT
VCC
AGND
VDD
NC
VSUP1
GND
LIN
VSUP2
FLSVPP
PTB7/AD7/TBCH1
PTB6/AD6/TBCH0
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
PTB5/AD5
PTB4/AD4
PTB3/AD3
IRQ
RST
PTB1/AD1
PTD0/TACH0
PTD1/TACH1
NC
NC
NC
PWMIN
RST_A
IRQ_A
NC
NC
NC
L1
L2
HS3
HS2
HS1
1
11
12
13
14
15
16
17
18
19
20
9
10
21
22
23
24
25
26
27
6
7
8
4
5
2
3
54
44
43
42
41
40
39
38
37
36
35
46
45
34
33
32
31
30
29
28
49
48
47
51
50
53
52
A
Material:
Single layer printed circuit board
FR4, 1.6 mm thickness
Cu traces, 0.07 mm thickness
Outline:
80 mm x 100 mm board area,
including edge connector for thermal
testing
Area A:
Cu heat-spreading areas on board
surface
Ambient Conditions: Natural convection, still air
Table 2. Thermal Resistance Performance
Terminal
Resistance
Area A
(mm
2
)
1 = Power Chip, 2 = Logic Chip (
C/W)
m = 1,
n = 1
m = 1, n = 2
m = 2, n = 1
m = 2,
n = 2
R
JA
mn
0
58
48
53
300
56
46
51
600
54
45
50
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
908E624DW
Figure 2. Device on Thermal Test Board R
JA
Figure 3. Transient Thermal Resistance (1.0 W Step Response)
Device on Thermal Test Board Area A = 600 (mm
2
)
0
10
20
30
40
50
60
70
0
300
600
Therm
a
l Re
si
sta
n
ce
(
CW
)
Heat Spreading Area A (mm
2
)
R
JA11
R
JA22
R
JA12
= R
JA21
x
0.1
1
10
100
1.00E-03
1.00E-02
1.00E-01
1.00E+00
1.00E+01
1.00E+02
1.00E+03
1.00E+04
time[s]
T
hermal Resistance
(CW
)
R
JA11
R
JA22
R
JA12
= R
JA21
x
Time (s)
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MM908E624
Rev. 4.0
12/2004
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