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1
MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION
AN1687
A FULL-FEATURED WIRELESS INTERFACE FOR
RS-232 COMMUNICATIONS
Prepared by; Paul Sofianos
Motorola, Inc., WSSG RF/IF Applications Engineering
INTRODUCTION
This application note describes a fullduplex, wireless
data communication link targeted for RS232 applications.
An encoding technique has been designed which addresses
many of the problems incurred when attempting to implement
the RS232 (EIA232) standard, including but not limited to:
hardware flow control, the DC component of the transmitted
signal, automatic synchronization from host to slave and
error detection. The design emulates a RS232 null modem
cable for computertocomputer communications.
The actual design was realized with standard SSI logic
from the high speed CMOS family (MC74HCxxx), an HC05
based MCU, and Motorola's ISM Band RF chipset. The
targeted data rate was 57,600 Baud, although both higher
and lower data rates are easily attainable. It is expected that
most applications would embed the logic functions (and
possibly the MCU functions) into a FPGA, CPLD, ASIC, or
other LSI logic building block.
Throughout this application note, it is assumed the user is
familiar with standard TTLcompatible CMOS devices and
the ISM Band RF chipset. Please refer to DL110/D and
DL129/D for additional details on individual device
specifications.
THE WIRELESS LINK
The actual implementation of the wireless link transceiver
was accomplished with the Motorola's ISM Band RF chipset.
This consists of a MC13145 RF Receiver, MC13146 RF
Transmitter and MC33411 Baseband. Figure 1 depicts the
block diagram of the RF transceiver. Figures 2, 3, and 4 are
the actual schematics for the Receiver, Transmitter, and
Baseband, respectively.
The transceiver was designed to operate in the unlicensed
(i.e. FCC Part 15) 902928 MHz Industrial, Scientific and
Medical (ISM) band with lowpower transmission. Since
directconversion FSK modulation is used in conjunction
with a PLL synthesized carrier, the digital modulation source
must meet certain requirements:
1. The DC component should be as close to zero as
possible. This maintains the best noise immunity at the
receiver.
2. A minimum frequency component must be maintained at
all times. If this condition is not met, the transmitter's PLL
and receiver's coilless demodulator will tend to
"trackout" the modulating signal.
3. The maximum frequency component should be known.
This will help define the modulation index and total
bandwidth required for the transceiver.
4. The system should be able to tolerate reasonable
biterrors.
The MC33411 baseband controls all of the synthesizer
functions via a MCU SPI compatible interface. None of the
audio processing capabilities of the device are used. Table 1
lists various MC33411 register values for both baseset and
handset for the 5 channels used for the prototype.
Baseband
DETI
LO2
FRX
RXMC
RXPD
RSSI
FTX
TXMC
TXPD
ENB
DATA
DCK
RCD
Receiver
Antenna
RF In
Transmitter
DETO
LO2
FRX
RXMC
RXPD
RSSI
TXD
ENB
DATA
DCK
RCD
RF Out
TXD
FTX
TXMC
TXPD
Figure 1. RF Transceiver
Block Diagram
Order this document
by AN1687/D
MOTOROLA
SEMICONDUCTOR APPLICATION NOTE
Motorola, Inc. 1999
REV 1
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MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION
C37
100 p
14
19
22
23
24
30
33
20
29
47
2
3
4
21
10
17
27
28
35
36
39
40
38
41
45
46
44
5
6
7
9
LNA In
oscC
oscE
oscB
LO2
Lin Adj1
Lin Adj2
BWadj
Fadj
AFT Out
AFT In
EN
MC
C41
C31
R6
C32
C12
D1
C35
C34
VCC
LNA Out
IF1+
IF1-
IF2+
IF2-
IF Dec1
IF Dec2
IF In
IF Out
Lim Dec1
Lim Dec2
Lim In
Det G
Det Out
RSSI
PRES Out
Mix2 In
Mix1 In
U1
MC13145
4.7 p
C11
4.7 p
R3
27 k
C25 47 p
R11
33 k
C43 22 n
C44 0.01
100 p
1.0 n
L5
6.8 n
C6 100 p
CF4
CF3
33 k
R9
2.2 n
L6
C10 100 p
1.0
120 k
R5
2.85 k
R4
100 k
1.0 n
C30 1.0 n
0.01
RF In
RXPD
LO2
RXMC
VCC
C21 1.0 n
C20 1.0 n
VCC
C19 1.0 n
C18 1.0 n
VCC
VCC
C16 39 p
VCC
L7 2.7
L8 2.7
C15 36 p
C42 100 p
C27 0.01
C17 1.0 n
C29 0.1
C23 1.0 n
C24 0.1
CF2
CF1
C9 100 p
C39 100 p
C26 0.01
10 p
C40
12 p
C14
C13
16 p
10
R10
T1
VCC
C46 1.0 n
C47 1.0 n
C48 1.0 n
C49 1.0 n
C50 100 p
C51 100 p
C52 100 p
C53 100 p
VCC
C45
1.0
+
R2 300
C7 100 p
C8 1.0 n
Figure 2. RF Receiver
DETO
RSSI
FRX
C22 0.1
C28 0.1
C36 100 p
Default Units: Ohms, Microfarads and Microhenries
CF1,CF2 Toko Type CFSK Series
SK107MXAEXXX, 330 kHz BW
CF3,CF4 Handset: TDK CF6118702
Baseset: TDK CF6118902
D1
MMBV809LT1
T1
Toko A638ANA099YWN
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MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION
OSCB
OSCE
OSCC
MIX/BUF_IN
LINADJ
RF-
RF+
PA_OUT
PRSCOUT
MC
EN
PA_IN
C63
2.7 p
47 p
C64
2.7 p
V
CC
C55
1.0 n
R14
200
1.0 n
L9
C68
C70
FTX
C72
Figure 3. RF Transmitter
9
11
12
5
4
22
16
17
14
19
100 p
C54
10 n
100 p
0.01
150
R13
C65
100 p
C66
1.0 n
C67
V
CC
R19
10 k
0.5 p
C75
R20
10 k
C77
47 p
C78
47 p
C74
15 p
V
CC
R22
51
V
CC
C57
1.0 n
C56
1.0
C58
1.0 n
C59
1.0 n
C60
100 p
C61
100 p
C62
100 p
C71
100 p
V
CC
L10
1.8 n
+
D3
TXMC
TXD
TXPD
Appx.
1.5 V
PP
MC13146
U2
RF Out
3
1
D2
CF5
Default Units: Ohms, Microfarads and Microhenries
CF5
Handset: TDK CF 6118902
Baseset: TDK CF 6118702
D2,D3
MMBV809LT1
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MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION
Figure 4. Baseband
VCCA
VCCR
R
x
O
u
t
RSSI In
E
I
n
E
c
a
p
E
O
u
t
P
A
I
G
n
d
S
A
P
A
O
-
P
A
O
+
V
C
C
S
A
V
B
V
A
G
M
C
I
F
R
x
M
C
F
R
x
P
L
L
V
C
C
R
x
P
D
P
L
L
G
n
d
T
x
P
D
P
L
L
V
C
C
F
T
x
F
T
x
M
C
E
N
C
L
K
D
a
t
a
Rx Audio In
DS In
Gnd Audio
LO2 Out
LO2 VCC
LO2+
LO2 Ctl
LO2-
LO2 Gnd
LO2 PD
LO2 Gnd
MCO
VCC Audio
C In
Ccap
C Out
Lim In
Tx Out
DS Out
MCU Clk Out
Gnd Digital
Fref Out
Fref In
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
1 2 3 4 5 6 7 8 9 1
0
1
1
1
2
VCCA
C94
0.1
C95
C97
1.0
C111
1.0
C112
1.0
C96
1.0 n
C98
1.0 n
C99
1.0 n
C107 1.0
VCC
R30
51
L12
150 n
C92
27 p
R29
R28
C91
C104
VCCR
C90
R24
C85
C86
C87
R31
R32
U3
MC33411
VCC
C93 100 p
RSSI
DETI
LO2
RXMC
FRX
RXPD
TXPD
FTX
TXMC
ENB
DCK
DATA
0.1
1.0
20 k
R25 2.0 k
0.33
R27
180 k
R26
51 k
2.7 n
C89 0.01
C88 200 p
470 p
C105 3.9 n
270 k
82 p
68 k
RCD
VCCA
Y1
11.2 M
C83
5-40 p
C84 20 p
4.7
C114 100 p
R35
18 k
VCC
10
10
C113
100 p
Default Units: Ohms, Microfarads and Microhenries
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MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION
DIGITAL ENCODING DESCRIPTION
As mentioned above, it is necessary to encode the raw
RS232 data prior to RF transmission since the incoming
data stream can, and usually will, contain a DC component
and has no predefined minimum frequency component.
Figure 5 is a block diagram of the digital encoder/decoder
section, and Figure 6 shows a possible implementation of the
encoder.
MCU
TXD
RXD
RTS
CTS
DCK
ENB
DATA
Translator
ETXD
TXD
RXD
RTS
CTS
Figure 5. Encoder/Decoder Block Diagram
(Baseset Shown)
D(0-7)
I
D/C
NTXA
TXR
CK
DOUT
DETI
I
D/C
NRXA
RXR
FE
DIN
CK
D(0-7)
I
D/C
NTXA
TXR
CK
Serial-Parallel/
Decoder
Parallel-Serial/
Encoder
NRXA
RXR
FE
16XCK
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
To RF
Transceiver
Baseband
DB25
P2
ERXD
ERTS
ECTS
TXD
RCD
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MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION
Figure 6. Encoder
SER
A
B
C
D
E
F
G
H
SRCLK
SRLOAD
14
15
1
2
3
4
5
6
7
11
13
U1
SRCLR
RCLK
QH
9
10
12
SER
A
B
C
D
E
F
G
H
SRCLK
SRLOAD
14
15
1
2
3
4
5
6
7
11
13
U2
SRCLR
RCLK
QH
9
10
12
74HC04A
8
9
U5D
74HC04A
10
11
U5E
74HC597A
A
B
C
D
ENP
ENT
CLK
LOAD
3
4
5
6
7
10
2
9
CLR
1
CK
14
13
12
11
15
74HC597A
74HC163A
VCC
VCC
74HC04A
13
12
U5F
74HC32A
8
10
9
U24C
74HC32A
11
13
12
U24D
CK
C23 4700 p
C17 2200 p
R13
5 k
TXR
DOUT
J
CLK
K
QA
QB
QC
QD
RCO
74HC86A
11
13
12
U15D
U3
U4B
VCC
10
9
PR
CL
Q
Q
74HC109
15
11
14
12
13
D5
D4
D3
D2
D1
D0
D7
D6
CK
CK
CK
NTXA
D(0-7)
D/C
I
VCC
Figure 7 illustrates the encoding scheme which was
developed for this purpose. Four additional bits surround a
data byte: the I bit, I bit, D/C bit and D/C bit. The function of
these bits are:
I (Invert) Bit: A logic low on this bit indicates that the data
byte and D/C bit are in true form. A logic high on this bit
indicates that the data byte and D/C bit are complemented
from their original form.
I (Invert Bar) Bit: Just the complement of the I bit.
D/C (Data/Control) Bit: A logic low on this bit indicates
that the data byte should be interpreted as a control word. A
logic high on this bit indicates that the data byte contains real
data.
D/C (Data/Control): Just the complement of the D/C bit.
Figure 7.
D/C
I
D0
D1
D2
D3
D4
D5
D6
D7
D/C
I
D/C
I
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MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION
This encoding scheme allows for the representation of 256
unique data words and 256 unique control words. The control
byte $h00 is reserved and referred to as the idle byte.
When the ParallelInput/SerialOutput (PISO) register is
ready to transmit a data byte (TXR asserted), a check is
made to see if real data has been transferred into the Serial
Communications Interface (SCI) data register of the MCU. If
data has been received, the data byte will be read, and the
initial state of D/C will be set to 1. If data has not been
received, the data byte will be set to $h00 (the idle byte) and
the initial state of D/C will be set to 0.
Next, the data byte is examined for a DC component. Each
0 bit of the data byte represents 1 and each 1 bit of the data
byte represents +1. All of these values are summed together:
a negative result indicates a low DC component, zero
indicates no DC component, and a positive (nonzero) result
indicates a high DC component. This component is
compared to a cumulative sum (which may be negative, zero,
or positive) and the following actions are taken:
If the current DC component sum is negative, and the
cumulative sum is positive or zero
OR
if the current DC component sum is positive or zero and the
cumulative sum is negative
THEN
clear the I bit (I=0). The new cumulative sum is equal to the
old cumulative sum plus the current sum.
OTHERWISE
set the I bit (I=1). The new cumulative sum is equal to the old
cumulative sum minus the current sum.
If the I bit is set, the contents of the data byte and D/C bit
are complemented.
The updated value of the I bit, data byte, and D/C bit are
placed on the PISO, and a transmission acknowledge signal
(NTXA) is asserted. Please note, the net effect of the DC
component contributed by the I and I bits and D/C and D/C
bits will always equal zero.
An analysis of this encoding scheme brings to light a few
interesting observations:
1. The average DC component over time will approach
zero.
2. The minimum frequency component which will be
observed in the data stream will equal 1/(2 x transmitted
bit period x 10).
3. The maximum (fundamental) frequency component
which will be observed in the data stream will equal 1/(2
x transmitted bit period).
4. A sequence of ten consecutive zeros or ones indicates
the presence of an idle byte.
Item 4 is perhaps the most interesting observation, since it
will allow the receiver to synchronize the incoming data and
align the serial stream on a bytewide basis.
TRANSMITTING FREQUENCY for ENCODED DATA
For RS232 communications which take the form of one
start bit, eight data bits, no parity, and one stop bit, the SCI
will receive 10 bits of data to represent one actual data byte.
For our encoding scheme, 12 bits must be transmitted for
each data or control byte received. If the transmit pipeline is
set to a frequency of at least 1.2 times the SCI receive
pipeline, the receive bandwidth will not have to be reduced
(i.e. no stop or hold conditions would be required).
In actual practice, the transmit pipeline was set to a
frequency 25% greater than the receive pipeline. As a result,
at a minimum, there will be at least one idle byte transmitted
for every 24 real data bytes. This useful feature allows the
receiver to resynchronize from time to time.
ADDITIONAL FEATURES
As mentioned above, the opportunity presents itself to
transmit a control word (the idle byte just being a special case
of a control word) from time to time. With 255 control words
remaining, various special features can be built into the link,
all transparent to the actual RS232 data communications.
One of the more obvious features which can be
implemented is hardware (RTS/CTS) flow control. The RTS
signal (for the baseset) and CTS signal (for the handset) can
be monitored and transmitted/received and interpreted by the
link. The latency will mostly be a function of the overhead
bandwidth.
Other features which can be implemented include, but are
not limited to:
Remote channel changing
Adaptive channel selection
Acknowledgments
DCD/DSR, etc. commands
CRC or other error checking
Half duplex handshaking
Power conservation modes
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MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION
Figure 8. Decoder
A
B
C
D
ENP
ENT
CLK
CLR
3
4
5
6
7
10
2
1
U16
74HC163A
16XCK
J
CLK
K
U14B
10
9
PR
CL
Q
Q
74HC109
15
11
14
12
13
VCC
LOAD
QA
QB
QC
QD
RCO
9
14
13
12
11
15
16XCK
VCC
RCLK
(Recovered CK)
J
CLK
K
U14A
VCC
6
7
PR
CL
Q
Q
74HC109
1
5
2
4
3
VCC
16XCK
DIN
16XCK
A
B
C
D
ENP
ENT
CLK
CLR
3
4
5
6
7
10
2
1
U18
74HC163A
16XCK
J
CLK
K
U17B
10
9
PR
CL
Q
Q
74HC109
15
11
14
12
13
VCC
LOAD
QA
QB
QC
QD
RCO
9
14
13
12
11
15
RCLK
VCC
J
CLK
K
U17A
VCC
6
7
PR
CL
Q
Q
74HC109
1
5
2
4
3
VCC
RCLK
A
B
C
D
ENP
ENT
CLK
CLR
3
4
5
6
7
10
2
1
U21
74HC163A
VCC
LOAD
QA
QB
QC
QD
RCO
9
14
13
12
11
15
RCLK
VCC
J
CLK
K
U19A
6
7
PR
CL
Q
Q
74HC109
1
5
2
4
3
VCC
VCC
RCLK
SER
SRCLK
SRCLR
RCLK
G
14
11
10
12
13
U20
74HC595A
QA
QB
QC
QD
15
1
2
3
4
5
6
7
9
VCC
RCLK
J
CLK
K
U19B
VCC
10
9
PR
CL
Q
Q
74HC109
15
11
14
12
13
SER
SRCLK
SRCLR
RCLK
G
14
11
10
12
13
U22
74HC595A
QA
QB
QC
QD
QE
15
1
2
3
4
5
6
7
9
VCC
RCLK
74HC86A
5
4
6
U23B
74HC86A
2
1
3
U23A
VCC
74HC86A
10
9
8
U23C
74HC86A
13
12
11
U23D
74HC32A
5
4
6
U24B
FE
NRXA
I
D1
D0
QF
QG
QH
QH
D7
D6
D5
D4
D3
D2
D/C
RXR
D(0-7)
D(0-7)
3
8
2
1
74HC32A
U24A
10
9
74HC86A
U15C
74HC86A
5
4
6
U15B
74HC86A
2
1
3
U15A
RDAT
(Recovered Data)
QE
QF
QG
QH
QH
1
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MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION
Figure 8 illustrates a possible implementation of the digital
decoder section of the design.
Received data is "squared up" by the data slicer of the
MC33411 baseband IC. The transmitted data is generally
frequency limited in order to preserve bandwidth (i.e.
lowpass filtered). Because of this limiting, as well as noise
components and hysteresis in the data slicer, the duty cycle
of the received data stream can vary substantially from that
of the transmitted data. For this reason, a data and clock
recovery block is utilized which oversamples the incoming
data (digital noise filtering) and captures the embedded
clock.
Once the clock and data have been recovered, they are
presented to the SerialInput/ParallelOutput (SIPO)
register. Data is transferred into the register every 12 bits,
this representing the I, I, data byte, D/C and D/C bits. Another
circuit analyzes the serial data stream looking for ten
consecutive bits without a transition. If this condition is
observed, it indicates an idle byte has been received, and the
SIPO register clock can be synchronized.
When the SIPO register indicates that a byte has been
received (RXR asserted), the MCU asserts an
acknowledgement (NRXA), loads the data byte, the I bit and
D/C bit from the bus. At this time, a comparison is made
which verifies that the I bit is the complement of the I bit and
the D/C bit is the complement of the D/C bit. If either of these
conditions is not met, a framing error has occurred and the
received data is simply ignored.
If a valid byte has been received, the MCU checks the
status of the I bit. If the I bit is set, the byte, as well as the D/C
bit, is complemented. Next, the MCU checks the value of the
updated D/C bit; a logic zero indicates a control word, and the
MCU can take appropriate action.
If the D/C bit indicates real data has been received, the
data is placed on an internal FirstIn/FirstOut (FIFO)
memory stack. The SCI transmitter is checked: if empty, the
next data byte is placed into the SCI transmitter and if full, the
data will be transferred at a later time.
As can be seen, the decoding of the data is a relatively
simple task. If desired, the MCU can consider the lack of an
idle byte, within a given period of time or reception of some
number of bytes, an indication that the RF link has failed.
Again, this condition can be used to reinitialize the RF link,
or other courses of action can be taken.
SUMMARY
This application note has described a robust, full featured
RS232 wireless interface which can be implemented with
an inexpensive MCU. For slower data rates, it is possible to
eliminate all of the external "glue logic" shown in this note. A
plethora of additional features can be added by the use of
embedded control words which are transparent to the actual
data transceiver.
Motorola's inexpensive and easy to use ISM Band RF
chipset is easily capable of accomplishing the wireless
portion of the task as long as the digital information presented
to the transmitter and receiver have been properly
preconditioned prior to modulation and demodulation.
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Table 1.
Baseband
Register
Address
Handset
Value
Transmit
Frequency
(MHz)
Receive
Frequency
(MHz)
Baseset
Value
Transmit
Frequency
(MHz)
Receive
Frequency
(MHz)
Channel
Number
$h01
$h004822
925.0
$h004686
903.0
0
$h02
$h004C27
903.0
$h004E03
925.0
0
$h01
$h004827
925.5
$h00468B
903.5
1
$h02
$h004C2C
903.5
$h004E08
925.5
1
$h01
$h00482C
926.0
$h004690
904.0
2
$h02
$h004C31
904.0
$h004E0D
926.0
2
$h01
$h004831
926.5
$h004695
904.5
3
$h02
$h004C36
904.5
$h004E12
926.5
3
$h01
$h004836
927.0
$h00469A
905.0
4
$h02
$h004C3B
905.0
$h004E17
927.0
4
$h03
$h0E0276
$h0E0276
X
$h04
$h160070
$h160070
X
$h05
$h000010
$h000010
X
$h06
$h0000FF
$h0000FF
X
$h07
$h01C000
$h01C000
X
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MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION
NOTES
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MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION
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