MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

MC68HC705P6A

Advance Information

Motorola reserves the right to make changes without further notice to any products
herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. "Typical" parameters which may be provided in Motorola data sheets and/or
specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including "Typicals" must be vali1dated for
each customer application by customer's technical experts. Motorola does not convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use
Motorola products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Motorola and

are registered trademarks of Motorola, Inc.

DigitalDNA is a trademark of Motorola, Inc.

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

List of Sections

Advance Information -- MC68HC705P6A

List of Sections

Section 1. General Description . . . . . . . . . . . . . . . . . . . . 19

Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Section 3. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . 35

Section 4. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Section 5. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Section 6. Input/Output Ports . . . . . . . . . . . . . . . . . . . . . 51

Section 7. Serial Input/Output Port (SIOP) . . . . . . . . . . . 59

Section 8. Capture/Compare Timer . . . . . . . . . . . . . . . . . 65

Section 9. Analog Subsystem . . . . . . . . . . . . . . . . . . . . . 77

Section 10. EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Section 11. Mask Option Register (MOR) . . . . . . . . . . . . 91

Section 12. Central Processor Unit (CPU) Core . . . . . . . 95

Section 13. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . 101

Section 14. Electrical Specifications . . . . . . . . . . . . . . . 117

Section 15. Mechanical Specifications . . . . . . . . . . . . . 125

Section 16. Ordering Information . . . . . . . . . . . . . . . . . 127

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Table of Contents

Advance Information -- MC68HC705P6A

Table of Contents

Section 1. General Description

1.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.4

Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.4.1

and V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.4.2

OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

1.4.2.1

Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.4.2.2

Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.4.2.3

External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

1.4.3

RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

1.4.4

PA0PA7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

1.4.5

PB5/SDO, PB6/SDI, and PB7/SCK . . . . . . . . . . . . . . . . . . .24

1.4.6

PC0-PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0,

and PC7/V

REFH

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

1.4.7

PD5 and PD7/TCAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.4.8

TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.4.9

IRQ/V

(Maskable Interrupt Request) . . . . . . . . . . . . . . . . 25

Section 2. Memory

2.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.3

User Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.4

Bootloader Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . .28

2.5

Input/Output and Control Registers . . . . . . . . . . . . . . . . . . . . . 29

2.6

RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table of Contents

Advance Information

MC68HC705P6A -- Rev. 2.0

Table of Contents

MOTOROLA

2.7

EPROM/ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

2.8

Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.9

Computer Operating Properly (COP) Clear Register . . . . . . . . 34

Section 3. Operating Modes

3.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.3

User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.4

Bootloader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.5

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.5.1

STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

3.5.1.1

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.5.1.2

Halt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.5.2

WAIT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

3.6

COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . . . .40

Section 4. Resets

4.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.3

External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.4

Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.4.1

Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.4.2

Computer Operating Properly (COP) Reset . . . . . . . . . . . . . 42

Section 5. Interrupts

5.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table of Contents

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Table of Contents

5.3

Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5.3.1

Reset Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.3.2

Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.3.3

Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.3.3.1

External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.3.3.2

Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.3.3.3

Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . .49

5.3.3.4

Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 49

Section 6. Input/Output Ports

6.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.3

Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.4

Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.5

Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.6

Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.7

I/O Port Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Section 7. Serial Input/Output Port (SIOP)

7.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

7.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

7.3

SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

7.3.1

Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

7.3.2

Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

7.3.3

Serial Data Output (SDO). . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.4

SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.4.1

SIOP Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . .62

7.4.2

SIOP Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . .63

7.4.3

SIOP Data Register (SDR). . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table of Contents

Advance Information

MC68HC705P6A -- Rev. 2.0

Table of Contents

MOTOROLA

Section 8. Capture/Compare Timer

8.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.3

Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

8.3.1

Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

8.3.2

Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

8.4

Timer I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

8.4.1

Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

8.4.2

Timer Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

8.4.3

Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

8.4.4

Alternate Timer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 72

8.4.5

Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

8.4.6

Output Compare Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 74

8.5

Timer During Wait/Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.6

Timer During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Section 9. Analog Subsystem

9.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

9.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

9.3

Analog Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

9.3.1

Ratiometric Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

9.3.2

Reference Voltage (V

REFH

) . . . . . . . . . . . . . . . . . . . . . . . . . 78

9.3.3

Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

9.4

Conversion Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

9.5

Digital Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

9.5.1

Conversion Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

9.5.2

Internal versus External Oscillator . . . . . . . . . . . . . . . . . . . . 79

9.5.3

Multi-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

9.6

A/D Status and Control Register (ADSC) . . . . . . . . . . . . . . . . . 80

9.7

A/D Conversion Data Register (ADC). . . . . . . . . . . . . . . . . . . .82

9.8

A/D Subsystem Operation during Halt/Wait Modes . . . . . . . . . 82

9.9

A/D Subsystem Operation during Stop Mode. . . . . . . . . . . . . . 82

Table of Contents

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Table of Contents

Section 10. EPROM

10.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10.3

EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10.4

EPROM Programming Sequence. . . . . . . . . . . . . . . . . . . . . . . 84

10.5

EPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.6

EPROM Programming Register (EPROG) . . . . . . . . . . . . . . . . 84

10.7

EPROM Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

10.8

Programming from an External Memory Device. . . . . . . . . . . . 87

Section 11. Mask Option Register (MOR)

11.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

11.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

11.3

Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

11.4

MOR Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Section 12. Central Processor Unit (CPU) Core

12.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

12.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

12.3

Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

12.3.1

Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

12.3.2

Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

12.3.3

Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

12.3.4

Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

12.3.5

Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table of Contents

Advance Information

MC68HC705P6A -- Rev. 2.0

Table of Contents

MOTOROLA

Section 13. Instruction Set

13.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

13.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

13.3

Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

13.3.1

Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

13.3.2

Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

13.3.3

Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

13.3.4

Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

13.3.5

Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

13.3.6

Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

13.3.7

Indexed,16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

13.3.8

Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

13.4

Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

13.4.1

13.4.2

Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . 106

13.4.3

Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 107

13.4.4

Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .109

13.4.5

Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

13.5

Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

13.6

Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Section 14. Electrical Specifications

14.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

14.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

14.3

Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

14.4

Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . 118

14.5

Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

14.6

5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .119

14.7

3.3-Volt DC Electrical Charactertistics . . . . . . . . . . . . . . . . . .120

14.8

A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 121

Table of Contents

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Table of Contents

14.9

EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . 122

14.10 SIOP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

14.11 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Section 15. Mechanical Specifications

15.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

15.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

15.3

Plastic Dual In-Line Package (Case 710) . . . . . . . . . . . . . . . . 126

15.4

Small Outline Integrated Circuit Package (Case 751F) . . . . . 126

Section 16. Ordering Information

16.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

16.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

16.3

MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

List of Figures

Advance Information -- MC68HC705P6A

List of Figures

Figure

Title

Page

1-1

MC68HC705P6A Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 21

1-2

Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2-1

MC68HC705P6A User Mode Memory Map . . . . . . . . . . . . . . . 28

2-2

MC68HC705P6A I/O and Control

Registers Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2-3

I/O and Control Register Summary. . . . . . . . . . . . . . . . . . . . . . 30

2-4

Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2-5

COP Watchdog Timer Location . . . . . . . . . . . . . . . . . . . . . . . .34

3-1

User Mode Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3-2

STOP/WAIT Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4-1

Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4-2

Unused Vector and COP Watchdog Timer. . . . . . . . . . . . . . . . 43

5-1

Interrupt Processing Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . 47

6-1

Port A I/O and Interrupt Circuitry . . . . . . . . . . . . . . . . . . . . . . . 52

6-2

Port B I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6-3

Port C I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6-4

Port D I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

7-1

SIOP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

7-2

SIOP Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7-3

SIOP Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7-4

SIOP Status Register (SSR). . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7-5

Serial Port Data Register (SDR) . . . . . . . . . . . . . . . . . . . . . . . .64

List of Figures

Advance Information

MC68HC705P6A -- Rev. 2.0

List of Figures

MOTOROLA

Figure

Title

Page

8-1

Capture/Compare Timer Block Diagram. . . . . . . . . . . . . . . . . . 66

8-2

Timer Control Register (TCR). . . . . . . . . . . . . . . . . . . . . . . . . . 68

8-3

Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 70

8-4

Timer Registers (TRH and TRL). . . . . . . . . . . . . . . . . . . . . . . .71

8-5

Alternate Timer Registers (ATRH and ATRL). . . . . . . . . . . . . . 72

8-6

Input Capture Registers (ICRH and ICRL) . . . . . . . . . . . . . . . . 73

8-7

Output Compare Registers (OCRH and OCRL) . . . . . . . . . . . . 74

9-1

A/D Status and Control Register (ADSC) . . . . . . . . . . . . . . . . . 80

9-2

A/D Conversion Value Data Register (ADC) . . . . . . . . . . . . . . 82

10-1

EPROM Programming Register (EPROG) . . . . . . . . . . . . . . . . 85

10-2

MC68HC705P6A EPROM Programming Flowchart. . . . . . . . . 89

10-3

MC68HC705P6A EPROM Programming

Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

11-1

Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . . 92

12-1

MC68HC05 Programming Model . . . . . . . . . . . . . . . . . . . . . . . 96

14-1

SIOP Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

14-2

Power-On Reset and External Reset Timing Diagram . . . . . . 124

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

List of Tables

Advance Information -- MC68HC705P6A

List of Tables

Table

Title

Page

3-1

Operating Mode Conditions After Reset . . . . . . . . . . . . . . . . . . 35

5-1

Vector Addresses for Interrupts and Reset. . . . . . . . . . . . . . . . 46

6-1

Port A I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6-2

Port B I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6-3

Port C I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6-4

Port D I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

9-1

A/D Multiplexer Input Channel Assignments . . . . . . . . . . . . . . 81

10-1

EPROM Programming Routine. . . . . . . . . . . . . . . . . . . . . . . . . 86

10-2

Bootloader Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

11-1

SIOP Clock Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

11-2

MOR Programming Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

13-1

13-2

Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . .106

13-3

Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . 108

13-4

Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 109

13-5

Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

13-6

Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

13-7

Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

General Description

Advance Information -- MC68HC705P6A

Section 1. General Description

1.1 Contents

1.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.4

Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.4.1

and V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.4.2

OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

1.4.2.1

Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.4.2.2

Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.4.2.3

External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

1.4.3

RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

1.4.4

PA0PA7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

1.4.5

PB5/SDO, PB6/SDI, and PB7/SCK . . . . . . . . . . . . . . . . . . .24

1.4.6

PC0-PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0,

and PC7/V

REFH

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

1.4.7

PD5 and PD7/TCAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.4.8

TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.4.9

IRQ/V

(Maskable Interrupt Request) . . . . . . . . . . . . . . . . 25

1.2 Introduction

The MC68HC705P6A is an EPROM version of the MC68HC05P6
microcontroller. It is a low-cost combination of an M68HC05 Family
microprocessor with a 4-channel, 8-bit analog-to-digital (A/D) converter,
a 16-bit timer with output compare and input capture, a serial
communications port (SIOP), and a computer operating properly (COP)
watchdog timer. The M68HC05 CPU core contains 176 bytes of RAM,
4672 bytes of user EPROM, 239 bytes of bootloader ROM, and 21
input/output (I/O) pins (20 bidirectional, 1 input-only). This device is

General Description

Advance Information

MC68HC705P6A -- Rev. 2.0

General Description

MOTOROLA

available in either a 28-pin plastic dual in-line (PDIP) or a 28-pin small
outline integrated circuit (SOIC) package.

A functional block diagram of the MC68HC705P6A is shown in

Figure 1-1

1.3 Features

Features of the MC68HC705P6A include:

Low cost

M68HC05 core

28-pin SOIC, PDIP, or windowed DIP package

4672 bytes of user EPROM (including 48 bytes of page zero
EPROM and 16 bytes of user vectors)

239 bytes of bootloader ROM

176 bytes of on-chip RAM

4-channel 8-bit A/D converter

SIOP serial communications port

16-bit timer with output compare and input capture

20 bidirectional I/O lines and 1 input-only line

PC0 and PC1 high-current outputs

Single-chip, bootloader, and test modes

Power-saving stop, halt, and wait modes

Static EPROM mask option register (MOR) selectable options:

COP watchdog timer enable or disable

Edge-sensitive or edge- and level-sensitive external interrupt

SIOP most significant bit (MSB) or least significant bit (LSB)
first

SIOP clock rates: OSC divided by 8, 16, 32, or 64

Stop instruction mode, STOP or HALT

EPROM security external lockout

Programmable keyscan (pullups/interrupts) on PA0PA7

General Description

Features

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

General Description

Figure 1-1. MC68HC705P6A Block Diagram

NOTE:

A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET is active low.

Any reference to voltage, current, or frequency specified in the following
sections will refer to the nominal values. The exact values and their
tolerances or limits are specified in

Section 14. Electrical

Specifications

INTERNAL

CPU CLOCK

/
D

16-BIT TIMER

1 INPUT CAPTURE

1 OUTPUT COMPARE

PORT D LOGIC

COP

OSC

COND CODE REG

1 1 1

I N Z C

INDEX REG

CPU CONTROL

0 0 0

STK PNTR

÷4

RESET

OSC 1

OSC 2

PD7/TCAP

SRAM -- 176 BYTES

USER EPROM -- 4672 BYTES

TCMP

IRQ/V

ALU

M68HC05 CPU

ACCUM

PROGRAM COUNTER

CPU REGISTERS

÷2

PA7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

T
A

I
RE

PB5/SDO

PB6/SDI

PB7/SCK

PORT B AND

SIOP

REGISTERS

AND LOGIC

PD5

DIR

N RE

I
S

PC3/AD3

PC4/AD2

PC5/AD1

PC6/AD0

PC7/VR

EFH

PC2

PC1

PC0

BOOTLOADER ROM -- 239 BYTES

General Description

Advance Information

MC68HC705P6A -- Rev. 2.0

General Description

MOTOROLA

1.4 Functional Pin Description

The following paragraphs describe the functionality of each pin on the
MC68HC705P6A package. Pins connected to subsystems described in
other chapters provide a reference to the chapter instead of a detailed
functional description.

1.4.1 V

and V

Power is supplied to the MCU through V

and V

. V

is connected

to a regulated +5 volt supply and V

is connected to ground.

Very fast signal transitions occur on the MCU pins. The short rise and fall
times place very high short-duration current demands on the power
supply. To prevent noise problems, take special care to provide good
power supply bypassing at the MCU. Use bypass capacitors with good
high-frequency characteristics and position them as close to the MCU as
possible. Bypassing requirements vary, depending on how heavily the
MCU pins are loaded.

1.4.2 OSC1 and OSC2

The OSC1 and OSC2 pins are the control connections for the on-chip
oscillator. The OSC1 and OSC2 pins can accept the following:

1. A crystal as shown in

Figure 1-2

(a)

2. A ceramic resonator as shown in

Figure 1-2

(a)

3. An external clock signal as shown in

Figure 1-2

(b)

The frequency, f

osc

, of the oscillator or external clock source is divided

by two to produce the internal bus clock operating frequency, f

. The

oscillator cannot be turned off by software unless the MOR bit, SWAIT,
is clear when a STOP instruction is executed.

General Description

Functional Pin Description

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

General Description

Figure 1-2. Oscillator Connections

1.4.2.1 Crystal

The circuit in

Figure 1-2

(a) shows a typical oscillator circuit for an

AT-cut, parallel resonant crystal. Follow the crystal manufacturer's
recommendations, as the crystal parameters determine the external
component values required to provide maximum stability and reliable
startup. The load capacitance values used in the oscillator circuit design
should include all stray capacitances. Mount the crystal and components
as close as possible to the pins for startup stabilization and to minimize
output distortion.

1.4.2.2 Ceramic Resonator

In cost-sensitive applications, use a ceramic resonator in place of a
crystal. Use the circuit in

Figure 1-2

(a) for a ceramic resonator and

follow the resonator manufacturer's recommendations, as the resonator
parameters determine the external component values required for
maximum stability and reliable starting. The load capacitance values
used in the oscillator circuit design should include all stray capacitances.
Mount the resonator and components as close as possible to the pins for
startup stabilization and to minimize output distortion.

To V

(or STOP)

To V

(or STOP)

(a)

Crystal or Ceramic
Resonator Connections

(b)

External Clock Source
Connections

OSC1

OSC2

MCU

37 pF

4.7 M

MCU

OSC1

OSC2

UNCONNECTED

EXTERNAL CLOCK

General Description

Advance Information

MC68HC705P6A -- Rev. 2.0

General Description

MOTOROLA

1.4.2.3 External Clock

An external clock from another CMOS-compatible device can be
connected to the OSC1 input, with the OSC2 input not connected, as
shown in

Figure 1-2

(b).

1.4.3 RESET

Driving this input low will reset the MCU to a known startup state. The
RESET pin contains an internal Schmitt trigger to improve its noise
immunity. Refer to

Section 4. Resets

1.4.4 PA0PA7

These eight I/O pins comprise port A. The state of any pin is software
programmable and all port A lines are configured as inputs during
power-on or reset. Port A has mask-option register enabled interrupt
capability with internal pullup devices selectable for any pin. Refer to

Section 6. Input/Output Ports

1.4.5 PB5/SDO, PB6/SDI, and PB7/SCK

These three I/O pins comprise port B and are shared with the SIOP
communications subsystem. The state of any pin is software
programmable, and all port B lines are configured as inputs during
power-on or reset. Refer to

Section 6. Input/Output Ports

and

Section 7. Serial Input/Output Port (SIOP)

1.4.6 PC0-PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0, and PC7/V

REFH

These eight I/O pins comprise port C and are shared with the A/D
converter subsystem. The state of any pin is software programmable
and all port C lines are configured as inputs during power-on or reset.
Refer to

Section 6. Input/Output Ports

and

Section 9. Analog

Subsystem

General Description

Functional Pin Description

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

General Description

1.4.7 PD5 and PD7/TCAP

These two I/O pins comprise port D and one of them is shared with the
16-bit timer subsystem. The state of PD5 is software programmable and
is configured as an input during power-on or reset. PD7 is always an
input. It may be read at any time, regardless of which mode of operation
the 16-bit timer is in. Refer to

Section 6. Input/Output Ports

and

Section 8. Capture/Compare Timer

1.4.8 TCMP

This pin is the output from the 16-bit timer's output compare function. It
is low after reset. Refer to

Section 8. Capture/Compare Timer

1.4.9 IRQ/V

(Maskable Interrupt Request)

This input pin drives the asynchronous interrupt function of the MCU in
user mode and provides the V

programming voltage in bootloader

mode. The MCU will complete the current instruction being executed
before it responds to the IRQ interrupt request. When the IRQ/V

pin is

driven low, the event is latched internally to signify an interrupt has been
requested. When the MCU completes its current instruction, the interrupt
latch is tested. If the interrupt latch is set and the interrupt mask bit (I bit)
in the condition code register is clear, the MCU will begin the interrupt
sequence.

Depending on the MOR LEVEL bit, the IRQ/V

pin will trigger an

interrupt on either a negative edge at the IRQ/V

pin and/or while the

IRQ/V

pin is held in the low state. In either case, the IRQ/V

pin must

be held low for at least one t

ILIH

time period. If the edge- and level-

sensitive mode is selected (LEVEL bit set), the IRQ/V

input pin

requires an external resistor connected to V

for wired-OR operation.

If the IRQ/V

pin is not used, it must be tied to the V

supply. The

IRQ/V

pin input circuitry contains an internal Schmitt trigger to improve

noise immunity. Refer to

Section 5. Interrupts

NOTE:

If the voltage level applied to the IRQ/V

pin exceeds V

, it may affect

the MCU's mode of operation. See

Section 3. Operating Modes

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Memory

Advance Information -- MC68HC705P6A

Section 2. Memory

2.1 Contents

2.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.3

User Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.4

Bootloader Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . .28

2.5

Input/Output and Control Registers . . . . . . . . . . . . . . . . . . . . . 29

2.6

RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.7

EPROM/ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

2.8

Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.9

Computer Operating Properly (COP) Clear Register . . . . . . . . 34

2.2 Introduction

The MC68HC705P6A utilizes 13 address lines to access an internal
memory space covering 8 Kbytes. This memory space is divided into
I/O, RAM, ROM, and EPROM areas.

2.3 User Mode Memory Map

When the MC68HC705P6A is in the user mode, the 32 bytes of I/O,
176 bytes of RAM, 4608 bytes of user EPROM, 48 bytes of user page
zero EPROM, 239 bytes of bootloader ROM, and 16 bytes of user
vectors EPROM are all active as shown in

Figure 2-1

Memory

Advance Information

MC68HC705P6A -- Rev. 2.0

Memory

MOTOROLA

Figure 2-1. MC68HC705P6A User Mode Memory Map

2.4 Bootloader Mode Memory Map

Memory space is identical to the user mode. See

Figure 2-1

$1F01

7937

MASK OPTION REGISTERS

BOOTLOADER ROM

AND VECTORS 239 BYTES

RESET VECTOR (LOW BYTE)

RESET VECTOR (HIGH BYTE)

SWI VECTOR (LOW BYTE)

SWI VECTOR (HIGH BYTE)

IRQ VECTOR (LOW BYTE)

IRQ VECTOR (HIGH BYTE)

TIMER VECTOR (LOW BYTE)

TIMER VECTOR (HIGH BYTE)

UNUSED

$1FF6

$1FF7

$1FF8

$1FF9

$1FFA

$1FFB

$1FFC

$1FFD

$1FFE

$1FFF

UNUSED

$1FF5

UNUSED

$1FF4

UNUSED

$1FF3

UNUSED

$1FF2

UNUSED

$1FF1

COP CLEAR REGISTER

(1)

$1FF0

$001F

$0000

$0100

$00FF

0255
0256

STACK

64 BYTES

INTERNAL RAM

176 BYTES

I/O

32 BYTES

USER VECTORS EPROM

16 BYTES

8191

8176

8175

7936

7935

4864

4863

0192

0191

0080

0079

0032

0031

0000

$1FFF

$1FF0

$1FEF

$1F00

$1EFF

$1300

$12FF

$00C0

$00BF

$0050

$004F

$0020

$001F

$0000

UNIMPLEMENTED

3071 BYTES

USER EPROM

4608 BYTES

USER EPROM

48 BYTES

I/O REGISTERS

SEE

FIGURE 2-2

$1EFE

7934

Note 1. Writing zero to bit 0 of $1FF0 clears the COP watchdog timer. Reading $1FF0 returns user EPROM data.

Memory

Input/Output and Control Registers

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Memory

2.5 Input/Output and Control Registers

Figure 2-2

and

Figure 2-3

briefly describe the I/O and control registers

at locations $0000$001F. Reading unimplemented bits will return
unknown states, and writing unimplemented bits will be ignored.

PORT A DATA REGISTER

$0000

PORT B DATA REGISTER

$0001

PORT C DATA REGISTER

$0002

PORT D DATA REGISTER

$0003

PORT A DATA DIRECTION REGISTER

$0004

PORT B DATA DIRECTION REGISTER

$0005

PORT C DATA DIRECTION REGISTER

$0006

PORT D DATA DIRECTION REGISTER

$0007

UNIMPLEMENTED

$0008

UMIMPLEMENTED

$0009

SIOP CONTROL REGISTER

$000A

SIOP STATUS REGISTER

$000B

SIOP DATA REGISTER

$000C

RESERVED

$000D

UNIMPLEMENTED

$000E

UNIMPLEMENTED

$000F

UNIMPLEMENTED

$0010

UNIMPLEMENTED

$0011

TIMER CONTROL REGISTER

$0012

TIMER STATUS REGISTER

$0013

INPUT CAPTURE MSB

$0015

INPUT CAPTURE LSB

$0016

OUTPUT COMPARE MSB

$0017

OUTPUT COMPARE LSB

$0017

TIMER MSB

$0018

TIMER LSB

$0019

ALTERNATE COUNTER MSB

$001A

ALTERNATE COUNTER LSB

$001B

EPROM PROGRAMMING REGISTER

$001C

A/D CONVERTER DATA REGISTER

$001D

A/D CONVERTER CONTROL AND STATUS REGISTER

$001E

RESERVED

$001F

Figure 2-2. MC68HC705P6A I/O and Control

Registers Memory Map

Memory

Advance Information

MC68HC705P6A -- Rev. 2.0

Memory

MOTOROLA

Addr.

Register Name

Bit 7

Bit 0

$0000

Port A Data Register

(PORTA)

See page 52.

Read:

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

Write:

Reset:

Unaffected by reset

$0001

Port B Data Register

(PORTB)

See page 53.

Read:

PB7

PB6

PB5

Write:

Reset:

Unaffected by reset

$0002

Port C Data Register

(PORTC)

See page 54.

Read:

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

Write:

Reset:

Unaffected by reset

$0003

Port D Data Register

(PORTD)

See page 55.

Read:

PD7

PD5

Write:

Reset:

Unaffected by reset

$0004

Port A Data Direction

See page 52.

Read:

DDRA7

DDRA6

DDRA5

DDRA4

DDRA3

DDRA2

DDRA1

DDRA0

Write:

Reset:

$0005

Port B Data Direction

See page 53.

Read:

DDRB7

DDRB6

DDRB5

Write:

Reset:

$0006

Port C Data Direction

See page 54.

Read:

DDRC7

DDRC6

DDRC5

DDRC4

DDRC3

DDRC2

DDRC1

DDRC0

Write:

Reset:

$0007

Port D Data Direction

See page 55.

Read:

DDRD5

Write:

Reset:

$0008

Unimplemented

= Unimplemented

= Reserved

U = Undetermined

Figure 2-3. I/O and Control Register Summary (Sheet 1 of 4)

Memory

Input/Output and Control Registers

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Memory

$0009

Unimplemented

$000A

SIOP Control Register

(SCR)

See page 62.

Read:

SPE

MSTR

Write:

Reset:

$000B

SIOP Status Register

(SSR)

See page 63.

Read:

SPIF

DCOL

Write:

Reset:

$000C

SIOP Data Register

(SDR)

See page 64.

Read:

SDR7

SDR6

SDR5

SDR4

SDR3

SSDR2

SDR1

SDR0

Write:

Reset:

Unaffected by reset

$000D

Reserved for Test

$000E

Unimplemented

$000F

Unimplemented

$0010

Unimplemented

$0011

Unimplemented

$0012

Timer Control Register

(TCR)

See page 68.

Read:

ICIE

OCIE

TOIE

IEDG

OLVL

Write:

Reset:

$0013

Timer Status Register

(TSR)

See page 70.

Read:

ICF

OCF

TOF

Write:

Reset:

Addr.

Register Name

Bit 7

Bit 0

= Unimplemented

= Reserved

U = Undetermined

Figure 2-3. I/O and Control Register Summary (Sheet 2 of 4)

Memory

Advance Information

MC68HC705P6A -- Rev. 2.0

Memory

MOTOROLA

$0014

Input Capture Register

MSB (ICRH)

See page 73.

Read:

ICRH7

ICRH6

ICRH5

ICRH4

ICRH3

ICRH2

ICRH1

ICRH0

Write:

Reset:

Unaffected by reset

$0015

Input Capture Register

LSB (ICRL)

See page 73.

Read:

ICRL7

ICRL6

ICRL5

ICRL4

ICRL3

ICRL2

ICRL1

ICRL0

Write:

Reset:

Unaffected by reset

$0016

Output Compare

See page 74.

Read:

OCRH7

OCRH6

OCRH5

OCRH4

OCRH3

OCRH2

OCRH1

OCRH0

Write:

Reset:

Unaffected by reset

$0017

Output Compare

See page 74.

Read:

OCRL7

OCRL6

OCRL5

OCRL4

OCRL3

OCRL2

OCRL1

OCRL0

Write:

Reset:

Unaffected by reset

$0018

Timer Register MSB

(TRH)

See page 71.

Read:

TRH7

TRH6

TRH5

TRH4

TRH3

TRH2

TRH1

TRH0

Write:

Reset:

$0019

Timer Register LSB

(TRL)

See page 71.

Read:

TRL7

TRL6

TRL5

TRL4

TRL3

TRL2

TRL1

TRL0

Write:

Reset:

$001A

Alternate Timer

See page 72.

Read:

ACRH7

ACRH6

ACRH5

ACRH4

ACRH3

ACRH2

ACRH1

ACRH0

Write:

Reset:

$001B

Alternate Timer

See page 72.

Read:

ACRL7

ACRL6

ACRL5

ACRL4

ACRL3

ACRL2

ACRL1

ACRL0

Write:

Reset:

$001C

EPROM Programming

See page 85.

Read:

ELAT

EPGM

Write:

Reset:

Addr.

Register Name

Bit 7

Bit 0

= Unimplemented

= Reserved

U = Undetermined

Figure 2-3. I/O and Control Register Summary (Sheet 3 of 4)

Memory

RAM

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Memory

2.6 RAM

The user RAM consists of 176 bytes (including the stack) at locations
$0050 through $00FF. The stack begins at address $00FF. The stack
pointer can access 64 bytes of RAM from $00FF to $00C0.

NOTE:

Using the stack area for data storage or temporary work locations
requires care to prevent it from being overwritten due to stacking from an
interrupt or subroutine call.

2.7 EPROM/ROM

There are 4608 bytes of user EPROM at locations $0100 through
$12FF, plus 48 bytes in user page zero locations $0020 through $004F,
and 16 additional bytes for user vectors at locations $1FF0 through
$1FFF. The bootloader ROM and vectors are at locations $1F01 through
$1FEF.

$001D

A/D Conversion Value

Data Register (ADC)

See page 82.

Read:

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

Write:

Reset:

Unaffected by reset

$001E

A/D Status and Control

See page 80.

Read:

ADRC

ADON

CH2

CH1

CH0

Write:

Reset:

$001F

Reserved for Test

Addr.

Register Name

Bit 7

Bit 0

= Unimplemented

= Reserved

U = Undetermined

Figure 2-3. I/O and Control Register Summary (Sheet 4 of 4)

Memory

Advance Information

MC68HC705P6A -- Rev. 2.0

Memory

MOTOROLA

2.8 Mask Option Register

The mask option register (MOR) is a pair of EPROM bytes located at
$1EFF and $1F00. It controls the programmable options on the
MC68HC705P6A. See

Section 11. Mask Option Register (MOR)

for

additional information.

2.9 Computer Operating Properly (COP) Clear Register

The computer operating properly (COP) watchdog timer is located at
address $1FF0. Writing a logical 0 to bit zero of this location will clear the
COP watchdog counter as described in

4.4.2 Computer Operating

Properly (COP) Reset

$1EFF

Bit 7

Bit 0

Read:

PA7PU

PA6PU

PA5PU

PA4PU

PA3PU

PA2PU

PA1PU

PA0PU

Write:

Erased State:

$1F00

Bit 7

Bit 0

Read:

SECURE

SWAIT

SPR1

SPR0

LSBF

LEVEL

COP

Write:

Erased State:

= Unimplemented

Figure 2-4. Mask Option Register (MOR)

$1FF0

Bit 7

Bit 0

Read:

Write:

COPR

Reset:

= Unimplemented

Figure 2-5. COP Watchdog Timer Location

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Operating Modes

Advance Information -- MC68HC705P6A

Section 3. Operating Modes

3.1 Contents

3.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.3

User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.4

Bootloader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.5

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.5.1

STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

3.5.1.1

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.5.1.2

Halt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.5.2

WAIT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

3.6

COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . . . .40

3.2 Introduction

The MC68HC705P6A has two modes of operation that affect the pinout
and architecture of the MCU: user mode and bootloader mode. The user
mode is normally used for the application and the bootloader mode is
used for programming the EPROM. The conditions required to enter
each mode are shown in

Table 3-1

. The mode of operation is

determined by the voltages on the IRQ/V

and PD7/TCAP pins on the

rising edge of the external RESET pin.

Table 3-1. Operating Mode Conditions After Reset

RESET Pin

IRQ/V

PD7/TCAP

Mode

to V

Single chip

Bootloader

Operating Modes

Advance Information

MC68HC705P6A -- Rev. 2.0

Operating Modes

MOTOROLA

The mode of operation is also determined whenever the internal
computer operating properly (COP) watchdog timer resets the MCU.
When the COP timer expires, the voltage applied to the IRQ/V

controls the mode of operation while the voltage applied to PD7/TCAP is
ignored. The voltage applied to PD7/TCAP during the last rising edge on
RESET is stored in a latch and used to determine the mode of operation
when the COP watchdog timer resets the MCU.

3.3 User Mode

The user mode allows the MCU to function as a self-contained
microcontroller, with maximum use of the pins for on-chip peripheral
functions. All address and data activity occurs within the MCU and are
not available externally. User mode is entered on the rising edge of
RESET if the IRQ/V

pin is within the normal operating voltage range.

The pinout for the user mode is shown in

Figure 3-1

Figure 3-1. User Mode Pinout

In the user mode, there is an 8-bit I/O port, a second 8-bit I/O port shared
with the analog-to-digital (A/D) subsystem, one 3-bit I/O port shared with
the serial input/output port (SIOP), and a 3-bit port shared with the 16-bit
timer subsystem, which includes one general-purpose I/O pin.

RESET

IRQ/V

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

SDO/PB5

SDI/PB6

SCK/PB7

OSC1

OSC2

PD7/TCAP

TCMP

PD5

PC0

PC1

PC2

PC3/AD3

PC4/AD2

PC5/AD1

PC6/AD0

PC7/V

REFH

Operating Modes

Bootloader Mode

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Operating Modes

3.4 Bootloader Mode

The bootloader mode provides a means to program the user EPROM
from an external memory device or host computer. This mode is entered
on the rising edge of RESET if V

is applied to the IRQ/V

pin and V

is applied to the PD7/TCAP pin. The user code in the external memory
device must have data located in the same address space it will occupy
in the internal MCU EPROM, including the mask option register (MOR)
at $1EFF and $1F00.

3.5 Low-Power Modes

The MC68HC705P6A is capable of running in a low-power mode in each
of its configurations. The WAIT and STOP instructions provide three
modes that reduce the power required for the MCU by stopping various
internal clocks and/or the on-chip oscillator. The SWAIT bit in the MOR
is used to modify the behavior of the STOP instruction from stop mode
to halt mode. The flow of the stop, halt, and wait modes is shown in

Figure 3-2

3.5.1 STOP Instruction

The STOP instruction can result in one of two modes of operation
depending on the state of the SWAIT bit in the MOR. If the SWAIT bit is
clear, the STOP instruction will behave like a normal STOP instruction in
the M68HC05 Family and place the MCU in stop mode. If the SWAIT bit
in the MOR is set, the STOP instruction will behave like a WAIT
instruction (with the exception of a brief delay at startup) and place the
MCU in halt mode.

3.5.1.1 Stop Mode

Execution of the STOP instruction when the SWAIT bit in the MOR is
clear places the MCU in its lowest power consumption mode. In stop
mode, the internal oscillator is turned off, halting all internal processing,
including the COP watchdog timer. Execution of the STOP instruction
automatically clears the I bit in the condition code register so that the IRQ
external interrupt is enabled. All other registers and memory remain
unaltered. All input/output lines remain unchanged.

Operating Modes

Low-Power Modes

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Operating Modes

The MCU can be brought out of stop mode only by an IRQ external
interrupt or an externally generated RESET. When exiting stop mode,
the internal oscillator will resume after a 4064 internal clock cycle
oscillator stabilization delay.

NOTE:

Execution of the STOP instruction when the SWAIT bit in the MOR is
clear will cause the oscillator to stop, and, therefore, disable the COP
watchdog timer. To avoid turning off the COP watchdog timer, stop
mode should be changed to halt mode by setting the SWAIT bit in the
MOR. See

3.6 COP Watchdog Timer Considerations

for additional

information.

3.5.1.2 Halt Mode

NOTE:

Halt mode is NOT designed for intentional use. Halt mode is only
provided to keep the COP watchdog timer active in the event a STOP
instruction is executed inadvertently. This mode of operation is usually
achieved by invoking wait mode.

Execution of the STOP instruction when the SWAIT bit in the MOR is set
places the MCU in this low-power mode. Halt mode consumes the same
amount of power as wait mode (both halt and wait modes consume more
power than stop mode).

In halt mode, the internal clock is halted, suspending all processor and
internal bus activity. Internal timer clocks remain active, permitting
interrupts to be generated from the 16-bit timer or a reset to be
generated from the COP watchdog timer. Execution of the STOP
instruction automatically clears the I bit in the condition code register,
enabling the IRQ external interrupt. All other registers, memory, and
input/output lines remain in their previous states.

If the 16-bit timer interrupt is enabled, it will cause the processor to exit
the halt mode and resume normal operation. The halt mode also can be
exited when an IRQ external interrupt or external RESET occurs.
When exiting the halt mode, the internal clock will resume after a delay
of one to 4064 internal clock cycles. This varied delay time is the result
of the halt mode exit circuitry testing the oscillator stabilization delay

Operating Modes

Advance Information

MC68HC705P6A -- Rev. 2.0

Operating Modes

MOTOROLA

timer (a feature of the stop mode), which has been free-running (a
feature of the wait mode).

3.5.2 WAIT Instruction

The WAIT instruction places the MCU in a low-power mode which
consumes more power than stop mode. In wait mode, the internal clock
is halted, suspending all processor and internal bus activity. Internal
timer clocks remain active, permitting interrupts to be generated from the
16-bit timer and reset to be generated from the COP watchdog timer.
Execution of the WAIT instruction automatically clears the I bit in the
condition code register, enabling the IRQ external interrupt. All other
registers, memory, and input/output lines remain in their previous state.

If the 16-bit timer interrupt is enabled, it will cause the processor to exit
wait mode and resume normal operation. The 16-bit timer may be used
to generate a periodic exit from wait mode. Wait mode may also be
exited when an IRQ external interrupt or RESET occurs.

3.6 COP Watchdog Timer Considerations

The COP watchdog timer is active in user mode of operation when the
COP bit in the MOR is set. Executing the STOP instruction when the
SWAIT bit in the MOR is clear will cause the COP to be disabled.
Therefore, it is recommended that the STOP instruction be modified to
produce halt mode (set bit SWAIT in the MOR) if the COP watchdog
timer is required to function at all times.

Furthermore, it is recommended that the COP watchdog timer be
disabled for applications that will use the wait mode for time periods that
will exceed the COP timeout period.

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Resets

Advance Information -- MC68HC705P6A

Section 4. Resets

4.1 Contents

4.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.3

External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.4

Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.4.1

Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.4.2

Computer Operating Properly (COP) Reset . . . . . . . . . . . . . 42

4.2 Introduction

The MCU can be reset from three sources: one external input and two
internal reset conditions. The RESET pin is a Schmitt trigger input as
shown in

Figure 4-1

. The CPU and all peripheral modules will be reset

by the RST signal which is the logical OR of internal reset functions and
is clocked by PH1.

Figure 4-1. Reset Block Diagram

RST

POWER-ON

RESET

(POR)

RESET

COP

WATCHDOG

(COPR)

OSC

DATA

ADDRESS

DFF

TO CPU AND
PERIPHERALS

PH1

RES

Resets

Advance Information

MC68HC705P6A -- Rev. 2.0

Resets

MOTOROLA

4.3 External Reset (RESET)

The RESET input is the only external reset and is connected to an
internal Schmitt trigger. The external reset occurs whenever the RESET
input is driven below the lower threshold and remains in reset until the
RESET pin rises above the upper threshold. The upper and lower
thresholds are given in

Section 14. Electrical Specifications

4.4 Internal Resets

The two internally generated resets are the initial power-on reset (POR)
function and the computer operating properly (COP) watchdog timer
function.

4.4.1 Power-On Reset (POR)

The internal POR is generated at power-up to allow the clock oscillator
to stabilize. The POR is strictly for power turn-on conditions and should
not be used to detect a drop in the power supply voltage. There is a 4064
internal clock cycle oscillator stabilization delay after the oscillator
becomes active.

The POR will generate the RST signal and reset the MCU. If any other
reset function is active at the end of this 4064 internal clock cycle delay,
the RST signal will remain active until the other reset condition(s) end.

4.4.2 Computer Operating Properly (COP) Reset

When the COP watchdog timer is enabled (COP bit in the MOR is set),
the internal COP reset is generated automatically by a timeout of the
COP watchdog timer. This timer is implemented with an 18-stage ripple
counter that provides a timeout period of 65.5 ms when a 4-MHz
oscillator is used. The COP watchdog counter is cleared by writing a
logical 0 to bit zero at location $1FF0.

The COP watchdog timer can be disabled by clearing the COP bit in the
MOR or by applying 2 x V

to the IRQ/V

pin (for example, during

bootloader). When the IRQ/V

pin is returned to its normal operating

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Interrupts

Advance Information -- MC68HC705P6A

Section 5. Interrupts

5.1 Contents

5.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.3

Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5.3.1

Reset Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.3.2

Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.3.3

Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.3.3.1

External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.3.3.2

Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.3.3.3

Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . .49

5.3.3.4

Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.2 Introduction

The MCU can be interrupted six different ways:

1. Non-maskable software interrupt instruction (SWI)

2. External asynchronous interrupt (IRQ)

3. Input capture interrupt (TIMER)

4. Output compare interrupt (TIMER)

5. Timer overflow interrupt (TIMER)

6. Port A interrupt (if selected via mask option register)

Interrupts cause the processor to save the register contents on the stack
and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike
reset, hardware interrupts do not cause the current instruction execution
to be halted, but are considered pending until the current instruction is
completed.

Interrupts

Advance Information

MC68HC705P6A -- Rev. 2.0

Interrupts

MOTOROLA

When the current instruction is completed, the processor checks all
pending hardware interrupts. If interrupts are not masked (I bit in the
condition code register is clear) and the corresponding interrupt enable
bit is set, the processor proceeds with interrupt processing. Otherwise,
the next instruction is fetched and executed. The SWI is executed the
same as any other instruction, regardless of the I-bit state.

When an interrupt is to be processed, the CPU puts the register contents
on the stack, sets the I bit in the CCR, and fetches the address of the
corresponding interrupt service routine from the vector table at locations
$1FF8 through $1FFF. If more than one interrupt is pending when the
interrupt vector is fetched, the interrupt with the highest vector location
shown in

Table 5-1

will be serviced first.

An RTI instruction is used to signify when the interrupt software service
routine is completed. The RTI instruction causes the CPU state to be
recovered from the stack and normal processing to resume at the next
instruction that was to be executed when the interrupt took place.

Figure 5-1

shows the sequence of events that occurs during interrupt

processing.

Table 5-1. Vector Addresses for Interrupts and Reset

Register

Flag

Name

Interrupts

CPU

Interrupt

Vector

Address

N/A

Reset

RESET

$1FFE$1FFF

N/A

Software

SWI

$1FFC$1FFD

N/A

External Interrupt

IRQ

$1FFA$1FFB

TSR

ICF

Timer Input Capture

TIMER

$1FF8$1FF9

TSR

OCF

Timer Output Compare

TIMER

$1FF8$1FF9

TSR

TOF

Timer Overflow

TIMER

$1FF8$1FF9

Interrupts

Advance Information

MC68HC705P6A -- Rev. 2.0

Interrupts

MOTOROLA

5.3.1 Reset Interrupt Sequence

The reset function is not in the strictest sense an interrupt; however, it is
acted upon in a similar manner as shown in

Figure 5-1

. A low-level input

on the RESET pin or internally generated RST signal causes the
program to vector to its starting address which is specified by the
contents of memory locations $1FFE and $1FFF. The I bit in the
condition code register is also set. The MCU is configured to a known
state during this type of reset as previously described in

Section 4.

Resets

5.3.2 Software Interrupt (SWI)

The SWI is an executable instruction. It is also a non-maskable interrupt
since it is executed regardless of the state of the I bit in the CCR. As with
any instruction, interrupts pending during the previous instruction will be
serviced before the SWI opcode is fetched. The interrupt service routine
address for the SWI instruction is specified by the contents of memory
locations $1FFC and $1FFD.

5.3.3 Hardware Interrupts

All hardware interrupts are maskable by the I bit in the CCR. If the I bit is
set, all hardware interrupts (internal and external) are disabled. Clearing
the I bit enables the hardware interrupts. Four hardware interrupts are
explained in the following subsections.

5.3.3.1 External Interrupt (IRQ)

The IRQ/V

pin drives an asynchronous interrupt to the CPU. An edge

detector flip-flop is latched on the falling edge of IRQ/V

. If either the

output from the internal edge detector flip-flop or the level on the
IRQ/V

pin is low, a request is synchronized to the CPU to generate the

IRQ interrupt. If the LEVEL bit in the mask option register is clear (edge-
sensitive only), the output of the internal edge detector flip-flop is
sampled and the input level on the IRQ/V

pin is ignored. The interrupt

service routine address is specified by the contents of memory locations

Interrupts

Interrupt Types

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Interrupts

$1FFA and $1FFB. If the port A interrupts are enabled by the MOR, they
generate external interrupts identically to the IRQ/V

pin.

NOTE:

The internal interrupt latch is cleared nine internal clock cycles after the
interrupt is recognized (immediately after location $1FFA is read).
Therefore, another external interrupt pulse could be latched during the
IRQ service routine.

Another interrupt will be serviced if the IRQ pin is still in a low state when
the RTI in the service routine is executed.

5.3.3.2 Input Capture Interrupt

The input capture interrupt is generated by the 16-bit timer as described
in

Section 8. Capture/Compare Timer

. The input capture interrupt flag

is located in register TSR and its corresponding enable bit can be found
in register TCR. The I bit in the CCR must be clear for the input capture
interrupt to be enabled. The interrupt service routine address is specified
by the contents of memory locations $1FF8 and $1FF9.

5.3.3.3 Output Compare Interrupt

The output compare interrupt is generated by a 16-bit timer as described
in

Section 8. Capture/Compare Timer

. The output compare interrupt

flag is located in register TSR and its corresponding enable bit can be
found in register TCR. The I bit in the CCR must be clear for the output
compare interrupt to be enabled. The interrupt service routine address is
specified by the contents of memory locations $1FF8 and $1FF9.

5.3.3.4 Timer Overflow Interrupt

The timer overflow interrupt is generated by the 16-bit timer as described
in

Section 8. Capture/Compare Timer

. The timer overflow interrupt flag

is located in register TSR and its corresponding enable bit can be found
in register TCR. The I bit in the CCR must be clear for the timer overflow
interrupt to be enabled. This internal interrupt will vector to the interrupt
service routine located at the address specified by the contents of
memory locations $1FF8 and $1FF9.

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Input/Output Ports

Advance Information -- MC68HC705P6A

Section 6. Input/Output Ports

6.1 Contents

6.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.3

Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.4

Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.5

Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.6

Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.7

I/O Port Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.2 Introduction

In the user mode, 20 bidirectional I/O lines are arranged as two 8-bit I/O
ports (ports A and C), one 3-bit I/O port (port B), and one 1-bit I/O port
(port D). These ports are programmable as either inputs or outputs
under software control of the data direction registers (DDRs). Port D also
contains one input-only pin.

Input/Output Ports

Advance Information

MC68HC705P6A -- Rev. 2.0

Input/Output Ports

MOTOROLA

6.3 Port A

Port A is an 8-bit bidirectional port, which does not share any of its pins
with other subsystems (see

Figure 6-1

). The port A data register is

located at address $0000 and its data direction register (DDR) is located
at address $0004. The contents of the port A data register are
indeterminate at initial power up and must be initialized by user software.
Reset does not affect the data registers, but does clear the DDRs,
thereby setting all of the port pins to input mode. Writing a 1 to a DDR bit
sets the corresponding port pin to output mode. Port A has mask option
register enabled interrupt capability with an internal pullup device

NOTE:

The keyscan (pullup/interrupt) feature available on port A is NOT
available in the ROM device, MC68HC05P6.

Figure 6-1. Port A I/O and Interrupt Circuitry

READ $0000

WRITE $0000

READ $0004

DATA

I/O

OUTPUT

INTERNAL HC05

DATA BUS

RESET

(RST)

WRITE $0004

DATA DIRECTION

TO IRQ

INTERRUPT SYSTEM

PULLUP MASK

OPTION REGISTER

Input/Output Ports

Port B

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Input/Output Ports

6.4 Port B

Port B is a 3-bit bidirectional port which can share pins PB5PB7 with
the SIOP communications subsystem. The port B data register is located
at address $0001 and its data direction register (DDR) is located at
address $0005. The contents of the port B data register are
indeterminate at initial powerup and must be initialized by user software.
Reset does not affect the data registers, but clears the DDRs, thereby
setting all of the port pins to input mode. Writing a 1 to a DDR bit sets the
corresponding port pin to output mode (see

Figure 6-2

Port B may be used for general I/O applications when the SIOP
subsystem is disabled. The SPE bit in register SPCR is used to
enable/disable the SIOP subsystem. When the SIOP subsystem is
enabled, port B registers are still accessible to software. Writing to either
of the port B registers while a data transfer is under way could corrupt
the data. See

Section 7. Serial Input/Output Port (SIOP)

for a

discussion of the SIOP subsystem.

Figure 6-2. Port B I/O Circuitry

READ $0001

WRITE $0001

READ $0005

DATA

I/O

OUTPUT

INTERNAL HC05

DATA BUS

RESET

(RST)

WRITE $0005

DATA DIRECTION

Input/Output Ports

Advance Information

MC68HC705P6A -- Rev. 2.0

Input/Output Ports

MOTOROLA

6.5 Port C

Port C is an 8-bit bidirectional port which can share pins PC3PC7 with
the A/D subsystem. The port C data register is located at address $0002
and its data direction register (DDR) is located at address $0006. The
contents of the port C data register are indeterminate at initial powerup
and must be initialized by user software. Reset does not affect the data
registers, but clears the DDRs, thereby setting all of the port pins to input
mode. Writing a 1 to a DDR bit sets the corresponding port pin to output
mode (see

Figure 6-3

Port C may be used for general I/O applications when the A/D
subsystem is disabled. The ADON bit in register ADSC is used to
enable/disable the A/D subsystem. Care must be exercised when using
pins PC0PC2 while the A/D subsystem is enabled. Accidental changes
to bits that affect pins PC3PC7 in the data or DDR registers will produce
unpredictable results in the A/D subsystem. See

Section 9. Analog

Subsystem

Figure 6-3. Port C I/O Circuitry

READ $0002

WRITE $0002

READ $0006

DATA

I/O

OUTPUT

INTERNAL HC05

DATA BUS

RESET

(RST)

WRITE $0006

DATA DIRECTION

Input/Output Ports

Advance Information

MC68HC705P6A -- Rev. 2.0

Input/Output Ports

MOTOROLA

6.7 I/O Port Programming

Each pin on port A through port D (except pin 7 of port D) can be
programmed as an input or an output under software control as shown
in

Table 6-1

Table 6-2

Table 6-3

, and

Table 6-4

. The direction of a pin

is determined by the state of its corresponding bit in the associated port
data direction register (DDR). A pin is configured as an output if its
corresponding DDR bit is set to a logic 1. A pin is configured as an input
if its corresponding DDR bit is cleared to a logic 0.

Table 6-1. Port A I/O Functions

DDRA

I/O Pin Mode

Accesses to

DDRA @ $0004

Accesses to Data
Register @ $0000

Read/Write

Read

Write

IN, Hi-Z

DDRA0DDRA7

I/O Pin

See Note

OUT

DDRA0DDRA7

PA0PA7

Note: Does not affect input, but stored to data register

Table 6-2. Port B I/O Functions

DDRB

I/O Pin Mode

Accesses to

DDRB @ $0005

Accesses to Data
Register @ $0001

Read/Write

Read

Write

IN, Hi-Z

DDRB5DDRB7

I/O Pin

See Note

OUT

DDRB5DDRB7

PB5PB7

Note: Does not affect input, but stored to data register

Table 6-3. Port C I/O Functions

DDRC

I/O Pin Mode

Accesses to

DDRC @ $0006

Accesses to Data
Register @ $0002

Read/Write

Read

Write

IN, Hi-Z

DDRC0DDRC7

I/O Pin

See Note

OUT

DDRC0DDRC7

PC0PC7

Note: Does not affect input, but stored to data register

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Serial Input/Output Port (SIOP)

Advance Information -- MC68HC705P6A

Section 7. Serial Input/Output Port (SIOP)

7.1 Contents

7.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

7.3

SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

7.3.1

Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

7.3.2

Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

7.3.3

Serial Data Output (SDO). . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.4

SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.4.1

SIOP Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . .62

7.4.2

SIOP Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . .63

7.4.3

SIOP Data Register (SDR). . . . . . . . . . . . . . . . . . . . . . . . . . 64

7.2 Introduction

The simple synchronous serial I/O port (SIOP) subsystem is designed to
provide efficient serial communications between peripheral devices or
other MCUs. The SIOP is implemented as a 3-wire master/slave system
with serial clock (SCK), serial data input (SDI), and serial data output
(SDO). A block diagram of the SIOP is shown in

Figure 7-1

. A mask

programmable option determines whether the SIOP is MSB or LSB first.

The SIOP subsystem shares its input/output pins with port B. When the
SIOP is enabled (SPE bit set in register SCR), port B DDR and data
registers are modified by the SIOP. Although port B DDR and data
registers can be altered by application software, these actions could
affect the transmitted or received data.

Serial Input/Output Port (SIOP)

Advance Information

MC68HC705P6A -- Rev. 2.0

Serial Input/Output Port (SIOP)

MOTOROLA

Figure 7-1. SIOP Block Diagram

7.3 SIOP Signal Format

The SIOP subsystem is software configurable for master or slave
operation. No external mode selection inputs are available (for instance,
slave select pin).

7.3.1 Serial Clock (SCK)

The state of the SCK output normally remains a logic 1 during idle
periods between data transfers. The first falling edge of SCK signals the
beginning of a data transfer. At this time, the first bit of received data may
be presented at the SDI pin and the first bit of transmitted data is
presented at the SDO pin (see

Figure 7-2

). Data is captured at the SDI

pin on the rising edge of SCK. The transfer is terminated upon the eighth
rising edge of SCK.

The master and slave modes of operation differ only by the sourcing of
SCK. In master mode, SCK is driven from an internal source within the
MCU. In slave mode, SCK is driven from a source external to the MCU.
The SCK frequency is dependent upon the SPR0 and SPR1 bits located
in the mask option register. Refer to

11.3 Mask Option Register

for a

description of available SCK frequencies.

8-BIT

SHIFT

STATUS

BAUD

RATE

CONTROL

GENERATOR

HCO5 INTERNAL BUS

INTERNAL

CPU CLOCK

SCK

SDI

SDO

7 6 5 4 3 2 1 0

I/O

$0B

$0C

$0A

CONTROL

LOGIC

SPE

SDI/PB6

SCK/PB7

SDO/PB5

Serial Input/Output Port (SIOP)

SIOP Signal Format

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Serial Input/Output Port (SIOP)

Figure 7-2. SIOP Timing Diagram

7.3.2 Serial Data Input (SDI)

The SDI pin becomes an input as soon as the SIOP subsystem is
enabled. New data may be presented to the SDI pin on the falling edge
of SCK.However, valid data must be present at least 100 nanoseconds
before the rising edge of SCK and remain valid for 100 nanoseconds
after the rising edge of SCK. See

Figure 7-2

7.3.3 Serial Data Output (SDO)

The SDO pin becomes an output as soon as the SIOP subsystem is
enabled. Prior to enabling the SIOP, PB5 can be initialized to determine
the beginning state. While the SIOP is enabled, PB5 cannot be used as
a standard output since that pin is connected to the last stage of the
SIOP serial shift register. Mask option register bit LSBF permits data to
be transmitted in either the MSB first format or the LSB first format. Refer
to

11.3 Mask Option Register

for MOR LSBF programming information.

On the first falling edge of SCK, the first data bit will be shifted out to the
SDO pin. The remaining data bits will be shifted out to the SDO pin on
subsequent falling edges of SCK. The SDO pin will present valid data at
least 100 nanoseconds before the rising edge of the SCK and remain
valid for 100 nanoseconds after the rising edge of SCK. See

Figure 7-2

SCK

SDO

SDI

100 ns

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

Serial Input/Output Port (SIOP)

Advance Information

MC68HC705P6A -- Rev. 2.0

Serial Input/Output Port (SIOP)

MOTOROLA

7.4 SIOP Registers

The SIOP is programmed and controlled by the SIOP control register
(SCR) located at address $000A, the SIOP status register (SSR) located
at address $000B, and the SIOP data register (SDR) located at address
$000C.

7.4.1 SIOP Control Register (SCR)

This register is located at address $000A and contains two bits.

Figure

7-3

shows the position of each bit in the register and indicates the value

of each bit after reset.

SPE -- Serial Peripheral Enable

When set, the SPE bit enables the SIOP subsystem such that
SDO/PB5 is the serial data output, SDI/PB6 is the serial data input,
and SCK/PB7 is a serial clock input in the slave mode or a serial clock
output in the master mode. Port B DDR and data registers can be
manipulated as usual (except for PB5); however, these actions could
affect the transmitted or received data.

The SPE bit is readable at any time. However, writing to the SIOP
control register while a transmission is in progress will cause the SPIF
and DCOL bits in the SIOP status register (see below) to operate
incorrectly. Therefore, the SIOP control register should be written
once to enable the SIOP and then not written to until the SIOP is to
be disabled. Clearing the SPE bit while a transmission is in progress

Address:

$000A

Bit 7

Bit 0

Read:

SPE

MSTR

Write:

Reset:

= Unimplemented

Figure 7-3. SIOP Control Register (SCR)

Serial Input/Output Port (SIOP)

SIOP Registers

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Serial Input/Output Port (SIOP)

will 1) abort the transmission, 2) reset the serial bit counter, and 3)
convert the port B/SIOP port to a general-purpose I/O port. Reset
clears the SPE bit.

MSTR -- Master Mode Select

When set, the MSTR bit configures the serial I/O port for master
mode. A transfer is initiated by writing to the SDR. Also, the SCK pin
becomes an output providing a synchronous data clock dependent
upon the oscillator frequency. When the device is in slave mode, the
SDO and SDI pins do not change function. These pins behave exactly
the same in both the master and slave modes.

The MSTR bit is readable and writeable at any time regardless of the
state of the SPE bit. Clearing the MSTR bit will abort any transfers that
may have been in progress. Reset clears the MSTR bit as well as the
SPE bit, disabling the SIOP subsystem.

7.4.2 SIOP Status Register (SSR)

This register is located at address $000B and contains two bits.

Figure

7-4

shows the position of each bit in the register and indicates the value

of each bit after reset.

SPIF -- Serial Port Interface Flag

SPIF is a read-only status bit that is set on the last rising edge of SCK
and indicates that a data transfer has been completed. It has no effect
on any future data transfers and can be ignored. The SPIF bit is

Address:

$000B

Bit 7

Bit 0

Read:

SPIF

DCOL

Write:

Reset:

= Unimplemented

Figure 7-4. SIOP Status Register (SSR)

Serial Input/Output Port (SIOP)

Advance Information

MC68HC705P6A -- Rev. 2.0

Serial Input/Output Port (SIOP)

MOTOROLA

cleared by reading the SSR followed by a read or write of the SDR. If
the SPIF is cleared before the last rising edge of SCK, it will be set
again on the last rising edge of SCK. Reset clears the SPIF bit.

DCOL -- Data Collision

DCOL is a read-only status bit which indicates that an illegal access
of the SDR has occurred. The DCOL bit will be set when reading or
writing the SDR after the first falling edge of SCK and before SPIF is
set. Reading or writing the SDR during this time will result in invalid
data being transmitted or received.

The DCOL bit is cleared by reading the SSR (when the SPIF bit is set)
followed by a read or write of the SDR. If the last part of the clearing
sequence is done after another transfer has started, the DCOL bit will
be set again. Reset clears the DCOL bit.

7.4.3 SIOP Data Register (SDR)

This register is located at address $000C and serves as both the
transmit and receive data register. Writing to this register will initiate a
message transmission if the SIOP is in master mode. The SIOP
subsystem is not double buffered and any write to this register will
destroy the previous contents. The SDR can be read at any time;
however, if a transfer is in progress, the results may be ambiguous and
the DCOL bit will be set. Writing to the SDR while a transfer is in
progress can cause invalid data to be transmitted and/or received.

Figure 7-5

shows the position of each bit in the register. This register is

not affected by reset.

Address:

$000C

Bit 7

Bit 0

Read:

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

Write:

Reset:

Unaffected by reset

Figure 7-5. Serial Port Data Register (SDR)

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Capture/Compare Timer

Advance Information -- MC68HC705P6A

Section 8. Capture/Compare Timer

8.1 Contents

8.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.3

Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

8.3.1

Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

8.3.2

Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

8.4

Timer I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

8.4.1

Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

8.4.2

Timer Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

8.4.3

Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

8.4.4

Alternate Timer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 72

8.4.5

Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

8.4.6

Output Compare Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 74

8.5

Timer During Wait/Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.6

Timer During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.2 Introduction

This section describes the operation of the 16-bit capture/compare timer.

Figure 8-1

shows the structure of the capture/compare subsystem.

Capture/Compare Timer

Advance Information

MC68HC705P6A -- Rev. 2.0

Capture/Compare Timer

MOTOROLA

Figure 8-1. Capture/Compare Timer Block Diagram

8.3 Timer Operation

The core of the capture/compare timer is a 16-bit free-running counter.
The counter provides the timing reference for the input capture and
output compare functions. The input capture and output compare
functions provide a means to latch the times at which external events
occur, to measure input waveforms, and to generate output waveforms
and timing delays. Software can read the value in the 16-bit free-running
counter at any time without affecting the counter sequence.

Because of the 16-bit timer architecture, the I/O registers for the input
capture and output compare functions are pairs of 8-bit registers.

INPUT

CAPTURE

CLOCK

INTERNAL BUS

OUTPUT

COMPARE

HIGH

BYTE

LOW

BYTE

$16

$17

³³³

÷4

INTERNAL

PROCESSOR

16-BIT FREE

RUNNING
COUNTER

COUNTER

ALTERNATE

8-BIT

BUFFER

HIGH

BYTE

LOW

BYTE

$1A

$1B

$18

$19

HIGH

BYTE

LOW

BYTE

$14

$15

OUTPUT

COMPARE

CIRCUIT

OVERFLOW

DETECT

CIRCUIT

EDGE

DETECT

CIRCUIT

TIMER

STATUS

REG.

ICF OCF TOF $13

ICIE

IEDG OLVL

OUTPUT

LEVEL

REG.

RESET

TIMER

CONTROL

REG.

$12

OUTPUT

LEVEL

(TCMP)

INTERRUPT CIRCUIT

TOIE

OCIE

EDGE

INPUT

(TCAP)

D
CLK

Capture/Compare Timer

Timer Operation

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Capture/Compare Timer

Because the counter is 16 bits long and preceded by a fixed divide-by-4
prescaler, the counter rolls over every 262,144 internal clock cycles.
Timer resolution with a 4-MHz crystal is 2

µs.

8.3.1 Input Capture

The input capture function is a means to record the time at which an
external event occurs. When the input capture circuitry detects an active
edge on the TCAP pin, it latches the contents of the timer registers into
the input capture registers. The polarity of the active edge is
programmable.

Latching values into the input capture registers at successive edges of
the same polarity measures the period of the input signal on the TCAP
pin. Latching values into the input capture registers at successive edges
of opposite polarity measures the pulse width of the signal.

8.3.2 Output Compare

The output compare function is a means of generating an output signal
when the 16-bit counter reaches a selected value. Software writes the
selected value into the output compare registers. On every fourth
internal clock cycle the output compare circuitry compares the value of
the counter to the value written in the output compare registers. When a
match occurs, the timer transfers the programmable output level bit
(OLVL) from the timer control register to the TCMP pin.

The programmer can use the output compare register to measure time
periods, to generate timing delays, or to generate a pulse of specific
duration or a pulse train of specific frequency and duty cycle on the
TCMP pin.

Capture/Compare Timer

Timer I/O Registers

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Capture/Compare Timer

ICIE -- Input Capture Interrupt Enable

This read/write bit enables interrupts caused by an active signal on
the TCAP pin. Resets clear the ICIE bit.

1 = Input capture interrupts enabled
0 = Input capture interrupts disabled

OCIE -- Output Compare Interrupt Enable

This read/write bit enables interrupts caused by an active signal on
the TCMP pin. Resets clear the OCIE bit.

1 = Output compare interrupts enabled
0 = Output compare interrupts disabled

TOIE -- Timer Overflow Interrupt Enable

This read/write bit enables interrupts caused by a timer overflow.
Reset clear the TOIE bit.

1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled

IEDG -- Input Edge

The state of this read/write bit determines whether a positive or
negative transition on the TCAP pin triggers a transfer of the contents
of the timer register to the input capture register. Resets have no
effect on the IEDG bit.

1 = Positive edge (low to high transition) triggers input capture
0 = Negative edge (high to low transition) triggers input capture

OLVL -- Output Level

The state of this read/write bit determines whether a logic 1 or logic 0
appears on the TCMP pin when a successful output compare occurs.
Resets clear the OLVL bit.

1 = TCMP goes high on output compare
0 = TCMP goes low on output compare

Capture/Compare Timer

Advance Information

MC68HC705P6A -- Rev. 2.0

Capture/Compare Timer

MOTOROLA

8.4.2 Timer Status Register

The timer status register (TSR), shown in

Figure 8-3

, contains flags to

signal the following conditions:

An active signal on the TCAP pin, transferring the contents of the
timer registers to the input capture registers

A match between the 16-bit counter and the output compare
registers, transferring the OLVL bit to the TCMP pin

A timer roll over from $FFFF to $0000

ICF -- Input Capture Flag

The ICF bit is set automatically when an edge of the selected polarity
occurs on the TCAP pin. Clear the ICF bit by reading the timer status
register with ICF set and then reading the low byte ($0015) of the
input capture registers. Resets have no effect on ICF.

OCF -- Output Compare Flag

The OCF bit is set automatically when the value of the timer registers
matches the contents of the output compare registers. Clear the OCF
bit by reading the timer status register with OCF set and then reading
the low byte ($0017) of the output compare registers. Resets have no
effect on OCF.

TOF -- Timer Overflow Flag

The TOF bit is set automatically when the 16-bit counter rolls over
from $FFFF to $0000. Clear the TOF bit by reading the timer status
register with TOF set, and then reading the low byte ($0019) of the
timer registers. Resets have no effect on TOF.

Address:

$0013

Bit 7

Bit 0

Read:

ICF

OCF

TOF

Write:

Reset:

U = Undetermined

Figure 8-3. Timer Status Register (TSR)

Capture/Compare Timer

Advance Information

MC68HC705P6A -- Rev. 2.0

Capture/Compare Timer

MOTOROLA

8.4.6 Output Compare Registers

When the value of the 16-bit counter matches the value in the output
compare registers, the planned TCMP pin action takes place. Writing to
OCRH before writing to OCRL inhibits timer compares until OCRL is
written. Reading or writing to OCRL after the timer status register clears
the output compare flag (OCF).

To prevent OCF from being set between the time it is read and the time
the output compare registers are updated, use this procedure:

1. Disable interrupts by setting the I bit in the condition code register.

2. Write to OCRH. Compares are now inhibited until OCRL is written.

3. Clear bit OCF by reading timer status register (TSR).

4. Enable the output compare function by writing to OCRL.

5. Enable interrupts by clearing the I bit in the condition code register.

Address:

OCRH -- $0016

Bit 7

Bit 0

Write:

OCRH7

OCRH6

OCRH5

OCRH4

OCRH3

OCRH2

OCRH1

OCRH0

Read:

Unaffected by reset

Address:

OCRL -- $0017

Bit 7

Bit 0

Read:

Unaffected by reset

Figure 8-7. Output Compare Registers (OCRH and OCRL)

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Analog Subsystem

Advance Information -- MC68HC705P6A

Section 9. Analog Subsystem

9.1 Contents

9.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

9.3

Analog Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

9.3.1

Ratiometric Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

9.3.2

Reference Voltage (V

REFH

) . . . . . . . . . . . . . . . . . . . . . . . . . 78

9.3.3

Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

9.4

Conversion Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

9.5

Digital Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

9.5.1

Conversion Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

9.5.2

Internal versus External Oscillator . . . . . . . . . . . . . . . . . . . . 79

9.5.3

Multi-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

9.6

A/D Status and Control Register (ADSC) . . . . . . . . . . . . . . . . . 80

9.7

A/D Conversion Data Register (ADC). . . . . . . . . . . . . . . . . . . .82

9.8

A/D Subsystem Operation during Halt/Wait Modes . . . . . . . . . 82

9.9

A/D Subsystem Operation during Stop Mode. . . . . . . . . . . . . . 82

9.2 Introduction

The MC68HC705P6A includes a 4-channel, multiplexed input, 8-bit,
successive approximation analog-to-digital (A/D) converter. The A/D
subsystem shares its inputs with port C pins PC3PC7.

Analog Subsystem

Advance Information

MC68HC705P6A -- Rev. 2.0

Analog Subsystem

MOTOROLA

9.3 Analog Section

The following paragraphs describe the operation and performance of
analog modules within the analog subsystem.

9.3.1 Ratiometric Conversion

The A/D converter is ratiometric, with pin V

REFH

supplying the high

reference voltage. Applying an input voltage equal to V

REFH

produces a

conversion result of $FF (full scale). Applying an input voltage equal to
V

produces a conversion result of $00. An input voltage greater than

REFH

will convert to $FF with no overflow indication. For ratiometric

conversions, V

REFH

should be at the same potential as the supply

voltage being used by the analog signal being measured and referenced
to V

9.3.2 Reference Voltage (V

REFH

)

The reference supply for the A/D converter shares pin PC7 with port C.
The low reference is tied to the V

pin internally. V

REFH

can be any

voltage between V

and V

; however, the accuracy of conversions is

tested and guaranteed only for V

REFH

= V

9.3.3 Accuracy and Precision

The 8-bit conversion result is accurate to within

±1 1/2 LSB, including

quantization; however, the accuracy of conversions is tested and
guaranteed only with external oscillator operation.

9.4 Conversion Process

The A/D reference inputs are applied to a precision digital-to-analog
converter. Control logic drives the D/A and the analog output is
successively compared to the selected analog input which was sampled
at the beginning of the conversion cycle. The conversion process is
monotonic and has no missing codes.

Analog Subsystem

Digital Section

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Analog Subsystem

9.5 Digital Section

The following paragraphs describe the operation and performance of
digital modules within the analog subsystem.

9.5.1 Conversion Times

Each input conversion requires 32 internal clock cycles, which must be
at a frequency equal to or greater than 1 MHz.

9.5.2 Internal versus External Oscillator

If the internal clock is 1 MHz or greater (i.e., external oscillator 2 MHz or
greater), the internal RC oscillator must be turned off and the external
oscillator used as the conversion clock.

If the MCU internal clock frequency is less than 1 MHz (2 MHz external
oscillator), the internal RC oscillator (approximately 1.5 MHz) must be
used for the A/D converter clock. The internal RC clock is selected by
setting the ADRC bit in the ADSC register.

When the internal RC oscillator is being used, these limitations apply:

1. Since the internal RC oscillator is running asynchronously with

respect to the internal clock, the conversion complete bit (CC) in
register ADSC must be used to determine when a conversion
sequence has been completed.

2. Electrical noise will slightly degrade the accuracy of the A/D

converter. The A/D converter is synchronized to read voltages
during the quiet period of the clock driving it. Since the internal and
external clocks are not synchronized, the A/D converter will
occasionally measure an input when the external clock is making
a transition.

Analog Subsystem

Advance Information

MC68HC705P6A -- Rev. 2.0

Analog Subsystem

MOTOROLA

9.5.3 Multi-Channel Operation

An input multiplexer allows the A/D converter to select from one of four
external analog signals. Port C pins PC3 through PC6 are shared with
the inputs to the multiplexer.

9.6 A/D Status and Control Register (ADSC)

The ADSC register reports the completion of A/D conversion and
provides control over oscillator selection, analog subsystem power, and
input channel selection. See

Figure 9-1

CC -- Conversion Complete

This read-only status bit is set when a conversion sequence has
completed and data is ready to be read from the ADC register. CC is
cleared when the ADSC is written to or when data is read from the
ADC register. Once a conversion has been started, conversions of
the selected channel will continue every 32 internal clock cycles until
the ADSC register is written to again. During continuous conversion
operation, the ADC register will be updated with new data, and the CC
bit set every 32 internal clock cycles. Also, data from the previous
conversion will be overwritten regardless of the state of the CC bit.

ADRC -- RC Oscillator Control

When ADRC is set, the A/D subsystem operates from the internal RC
oscillator instead of the internal clock. The RC oscillator requires a
time, t

RCON

, to stabilize before accurate conversion results can be

Address: $001E

Bit 7

Bit 0

Read:

ADRC

ADON

CH2

CH1

CH0

Write:

Reset:

= Unimplemented

Figure 9-1. A/D Status and Control Register (ADSC)

Analog Subsystem

A/D Status and Control Register (ADSC)

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Analog Subsystem

obtained. See

9.3.2 Reference Voltage (VREFH)

for more

information.

ADON -- A/D Subsystem On

When the A/D subsystem is turned on (ADON = 1), it requires a time,
t

ADON

, to stabilize before accurate conversion results can be attained.

CH2CH0 -- Channel Select Bits

CH2, CH1, and CH0 form a 3-bit field which is used to select an input
to the A/D converter. Channels 03 correspond to port C input pins
PC6PC3. Channels 46 are used for reference measurements.
Channel 7 is reserved. If a conversion is attempted with channel 7
selected, the result will be $00.

Table 9-1

lists the inputs selected by

bits CH0-CH3.

If the ADON bit is set and an input from channels 04 is selected, the
corresponding port C pin's DDR bit will be cleared (making that port
C pin an input). If the port C data register is read while the A/D is on
and one of the shared input channels is selected using bit CH0CH2,
the corresponding port C pin will read as a logic 0. The remaining port
C pins will read normally. To digitally read a port C pin, the A/D
subsystem must be disabled (ADON = 0), or input channels 57 must
be selected.

Table 9-1. A/D Multiplexer Input

Channel Assignments

Channel

Signal

AD0 -- port C, bit 6

AD1 -- port C, bit 5

AD2 -- port C, bit 4

AD3 -- port C, bit 3

REFH

-- port C, bit 7

REFH

+ V

)/2

Reserved for factory test

Analog Subsystem

Advance Information

MC68HC705P6A -- Rev. 2.0

Analog Subsystem

MOTOROLA

9.7 A/D Conversion Data Register (ADC)

This register contains the output of the A/D converter. See

Figure 9-2

9.8 A/D Subsystem Operation during Halt/Wait Modes

The A/D subsystem continues normal operation during wait and halt
modes. To decrease power consumption during wait or halt mode, the
ADON and ADRC bits in the A/D status and control register should be
cleared if the A/D subsystem is not being used.

9.9 A/D Subsystem Operation during Stop Mode

When stop mode is enabled, execution of the STOP instruction will
terminate all A/D subsystem functions. Any pending conversion is
aborted. When the oscillator resumes operation upon leaving stop
mode, a finite amount of time passes before the A/D subsystem
stabilizes sufficiently to provide conversions at its rated accuracy. The
delays built into the MC68HC705P6A when coming out of stop mode are
sufficient for this purpose. No explicit delays need to be added to the
application software.

Address: $001D

Bit 7

Bit 0

Read:

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

Write:

Reset:

Unaffected by reset

= Unimplemented

Figure 9-2. A/D Conversion Value Data Register (ADC)

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

EPROM

Advance Information -- MC68HC705P6A

Section 10. EPROM

10.1 Contents

10.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10.3

EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10.4

EPROM Programming Sequence. . . . . . . . . . . . . . . . . . . . . . . 84

10.5

EPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.6

EPROM Programming Register (EPROG) . . . . . . . . . . . . . . . . 84

10.7

EPROM Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

10.8

Programming from an External Memory Device. . . . . . . . . . . . 87

10.2 Introduction

The user EPROM consists of 48 bytes of user page zero EPROM from
$0020 to $004F, 4608 bytes of user EPROM from $0100 to $12FF, the
two MOR reset values located at $1EFF and $1F00, and 16 bytes of user
vectors EPROM from $1FF0 to $1FFF. The bootloader ROM and
vectors are located from $1F01 to $1FEF.

10.3 EPROM Erasing

NOTE:

Only parts packaged in a windowed package may be erased. Others are
one-time programmable and may not be erased by UV exposure.

The MC68HC705P6A can be erased by exposure to a high-intensity
ultraviolet (UV) light with a wavelength of 2537 angstroms. The
recommended dose (UV intensity multiplied by exposure time) is
15 Ws/cm

. UV lamps without shortwave filters should be used, and the

EPROM

Advance Information

MC68HC705P6A -- Rev. 2.0

EPROM

MOTOROLA

EPROM device should be positioned about one inch from the UV lamp.
An erased EPROM byte will read as $00.

10.4 EPROM Programming Sequence

The bootloader software goes through a complete write cycle of the
EPROM including the MOR. This is followed by a verify cycle which
continually branches in a loop if an error is found. A sample routine to
program a byte of EPROM is shown in

Table 10-1

NOTE:

To avoid damage to the MCU, V

must be applied to the MCU before

10.5 EPROM Registers

Three registers are associated with the EPROM: the EPROM
programming register (EPROG) and the two mask option registers
(MOR). The EPROG register controls the actual programming of the
EPROM bytes and the MOR. The MOR registers control the six mask
options found on the ROM version of this MCU (MC68HC05P6), the
EPROM security feature, and eight additional port A interrupt options.

10.6 EPROM Programming Register (EPROG)

This register is used to program the EPROM array. Only the ELAT and
EPGM bits are available.

Table 10-1

shows the location of each bit in the

EPROG register and the state of these bits coming out of reset. All the
bits in the EPROG register are cleared by reset.

EPROM

EPROM Programming Register (EPROG)

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

EPROM

EPGM -- EPROM Program Control

If the EPGM bit is set, programming power is applied to the EPROM
array. If the EPGM bit is cleared, programming power is removed from
the EPROM array. The EPGM bit cannot be set unless the ELAT bit
is set already.

Whenever the ELAT bit is cleared, the EPGM bit is cleared also. Both
the EPGM and the ELAT bit cannot be set using the same write
instruction. Any attempt to set both the EPGM and ELAT bit on the
same write instruction cycle will result in the ELAT bit being set and
the EPGM bit being cleared. The EPGM bit is a read-write bit and can
be read at any time. The EPGM bit is cleared by reset.

ELAT-- EPROM Latch Control

If the ELAT bit is set, the EPROM address and data bus are
configured for programming to the array. If the ELAT bit is cleared, the
EPROM address and data bus are configured for normal reading of
data from the array. When the ELAT bit is set, the address and data
bus are latched in the EPROM array when a subsequent write to the
array is made. Data in the EPROM array cannot be read if the ELAT
bit is set.

Whenever the ELAT bit is cleared, the EPGM bit is cleared also. Both
the EPGM and the ELAT bit cannot be set using the same write
instruction. Any attempt to set both the EPGM and ELAT bit on the
same write instruction cycle will result in the ELAT bit being set and
the EPGM bit being cleared. The ELAT bit is a read-write bit and can
be read at any time. The ELAT bit is cleared by reset.

Address $001C

Bit 7

Bit 0

Read:

ELAT

EPGM

Write:

Reset:

= Unimplemented

Figure 10-1. EPROM Programming Register (EPROG)

EPROM

Advance Information

MC68HC705P6A -- Rev. 2.0

EPROM

MOTOROLA

To program a byte of EPROM, manipulate the EPROG register as
follows:

1. Set the ELAT bit in the EPROG register.

2. Write the desired data to the desired EPROM address.

3. Set the EPGM bit in the EPROG register for the specified

programming time, t

EPGM

4. Clear the ELAT and EPGM bits in the EPROG register.

This sequence is also shown in the sample program listing in

Table 10-1

10.7 EPROM Bootloader

Three port pins are associated with bootloader control functions: PC3,
PC4, and PC6.

Table 10-2

summarizes their functionality.

Table 10-1. EPROM Programming Routine

001C

0055

0700

0000

EPROG

DATA

EPROM

EPGM

EQU $1C

EQU $55

EQU $700

EQU $00

PROGRAMMING REG

DATA VALUE

A SAMPLE EPROM ADX

EPGM BIT IN EPROG REG

00D0

ORG

$D0

00D0

00D2

00D4

00D6

00D9

00DB

00DD

00DF

A6 02

B7 1C

A6 55

C7 07 00

10 1C

AD 03

3F 1C

LDA

#$04

STA

EPROG

LDA

#DATA

STA

EPROM

BSET

EPGM, EPROG

BSR

DELAY

CLR

EPROG

RTS

SET LAT BIT IN EPROG

DATA BYTE

WRITE IT TO EPROM LOC

TURN ON PGM VOLTAGE

WAIT 4 ms MINIMUM

CLR LAT AND PGM BITS

Table 10-2. Bootloader Control Pins

PC6

PC4

PC3

Mode

Program/verify

Verify only

Dump MCU EPROM to port A

EPROM

Programming from an External Memory Device

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

EPROM

10.8 Programming from an External Memory Device

In this programming mode, PC5 must be connected to V

. PC4 and

PC3 are used to select the programming mode. The programming circuit
shown in

Figure 10-2

uses an external 12-bit counter to address the

memory device containing the code to be copied. This counter requires
a clock and a reset function. The 12-bit counter can address up to
4 Kbytes of memory, which means that a port pin has to be used to
address the remaining 4 K of the 8-K memory space.

The following procedure explains how to use the programming circuit
shown in

Figure 10-2

to copy a user program from an external memory

device into the MCU's EPROM:

1. Program a 2764-type EPROM device with the desired instructions

and data. Code programmed into the 2764 must appear at the
same addresses desired in the MC68HC705P6A. Therefore, the
page zero code must start at $0020 and end at $004F, the main
body of code must start at $0100 and end at $12FF, and the user
vectors must start at $1FF0 and end at $1FFF.

NOTE:

The MOR data must appear at $1EFF and $1F00.

2. Install the programmed 2764 device into the programming circuit.

3. Install the MC68HC705P6A to be programmed into the

programming circuit.

4. Set the PROGRAM and/or VERIFY switches for the desired

operation (an open switch is the active state) and close the
RESET switch to hold the MCU in reset.

5. Make sure that the V

source is OFF.

6. Apply the V

source to the programming circuit.

7. Apply the V

source to the programming circuit.

8. Open the RESET switch to allow the MCU to come out of reset

and begin execution of the software in its internal bootloader
ROM.

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Mask Option Register (MOR)

Advance Information -- MC68HC705P6A

Section 11. Mask Option Register (MOR)

11.1 Contents

11.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

11.3

Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

11.4

MOR Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

11.2 Introduction

The mask option register (MOR) contains two bytes of EPROM used to
enable or disable each of the features controlled by mask options on the
MC68HC05P6 (a ROM version of the MC68HC705P6A).

The seven programmable options on the MC68HC705P6A are:

1. COP watchdog timer (enable

or disable)

2. IRQ triggering (edge- or edge- and level-sensitive)

3. SIOP data bit order (most significant bit or least significant bit first)

4. SIOP clock rate (OSC divided by 8, 16, 32, or 64)

5. Stop instruction mode (stop mode or halt mode)

6. Secure EPROM from external reading

7. Keyscan interrupt/pullups on PA0PA7

11.3 Mask Option Register

Mask options are programmed into the mask option register (MOR) by
the firmware in the bootloader ROM. See

Figure 11-1

Mask Option Register (MOR)

Advance Information

MC68HC705P6A -- Rev. 2.0

Mask Option Register (MOR)

MOTOROLA

COP -- COP Watchdog Enable

Setting the COP bit will enable the COP watchdog timer. The COP will
reset the MCU if the timeout period is reached before the COP
watchdog timer is cleared by the application software and the voltage
applied to the IRQ/V

pin is between V

and V

. Clearing the

COP bit will disable the COP watchdog timer regardless of the voltage
applied to the IRQ/V

pin.

LEVEL -- IRQ Edge Sensitivity

If the LEVEL bit is clear, the IRQ/V

pin will only be sensitive to the

falling edge of the signal applied to the IRQ/V

pin. If the LEVEL bit

is set, the IRQ/V

pin will be sensitive to both the falling edge of the

input signal and the logic low level of the input signal on the IRQ/V

pin.

LSBF -- SIOP Least Significant Bit First

If the LSBF bit is set, the serial data to and from the SIOP will be
transferred least significant bit first. If the LSBF bit is clear, the serial
data to and from the SIOP will be transferred most significant bit first.

Address: $1EFF

Bit 7

Bit 0

Read:

PA7PU

PA6PU

PA5PU

PA4PU

PA3PU

PA2PU

PA1PU

PA0PU

Write:

Erased State:

Address: $1F00

Bit 7

Bit 0

Read:

SECURE

SWAIT

SPR1

SPR0

LSBF

LEVEL

COP

Write:

Erased State:

= Unimplemented

Figure 11-1. Mask Option Register (MOR)

Mask Option Register (MOR)

Mask Option Register

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Mask Option Register (MOR)

SPR0 and SPR1 -- SIOP Clock Rate

The SPR0 and SPR1 bits determine the clock rate used to transfer the
serial data to and from the SIOP. The various clock rates available are
given in

Table 11-1

SWAIT -- STOP Instruction Mode

Setting the SWAIT bit will prevent the STOP instruction from stopping
the on-board oscillator. Clearing the SWAIT bit will permit the STOP
instruction to stop the on-board oscillator and place the MCU in stop
mode. Executing the STOP instruction when SWAIT is set will place
the MCU in halt mode. See

3.5.1 STOP Instruction

for additional

information.

SECURE -- Security State

(1)

If SECURE bit is set, the EPROM is locked.

PA(0:7)PU -- Port A Pullups/Interrupt Enable/Disable

If any PA(0:7)PU is selected, that pullup/interrupt is enabled. The
interrupt sensitivity will be selected via the LEVEL bit in the same way
as the IRQ pin.

NOTE:

The port A pullup/interrupt function is NOT available on the ROM device,
MC68HC05P6.

Table 11-1. SIOP Clock Rate

SPR1

SPR0

SIOP Master Clock

osc

÷ 64

osc

÷ 32

osc

÷ 16

osc

÷ 8

1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or

copying the EPROM/OTPROM difficult for unauthorized users.

Mask Option Register (MOR)

Advance Information

MC68HC705P6A -- Rev. 2.0

Mask Option Register (MOR)

MOTOROLA

11.4 MOR Programming

The contents of the MOR should be programmed in bootloader mode
using the hardware shown in

Figure 10-2

. In order to allow

programming, all the implemented bits in the MOR are essentially read-
write bits in bootloader mode as shown in

Figure 11-1

The programming of the MOR is the same as user EPROM.

1. Set the ELAT bit in the EPROG register.

2. Write the desired data to the desired MOR address.

3. Set the EPGM bit in the EPROG.

4. Wait for the programming time (t

EPGM

5. Clear the ELAT and EPGM bits in the EPROG.

6. Remove the programming voltage from the IRQ/V

pin.

A sample routine to program a byte of EPROM is shown in

Table 11-2

Once the MOR bits have been programmed, the options are not loaded
into the MOR registers until the part is reset.

Table 11-2. MOR Programming Routine

001C

00FF

0023

1EFF

1F00

0000

EPROG

DATA2

DATA1

MOR2

MOR1

EPGM

EQU

$1C

EQU

$FF

EQU

#23

EQU

$1EFF

EQU

$1F00

EQU

$00

PROGRAMMING REG

SAMPLE MOR VALUES

MOPR ADDRESSES

EPGM BIT IN EPROG REG

00E0

ORG

$E0

00E0

00E2

00E4

00E6

00E9

00EB

00ED

00EF

A6 04

B7 1C

A6 FF

C7 1E FF

12 1C

AD 03

3F 1C

LDA

#$04

STA

EPROG

LDA

#DATA2

STA

MOR2

BSET EPGM,EPROG

BSR

DELAY

CLR

EPROG

RTS

SET ELAT BIT

IN EPGM REG AT $1C

DATA BYTE

WRITE IT TO MOR LOC

TURN ON PGM VOLTAGE

WAIT 4 ms MINIMUM

CLR EPGM REGISTER

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Central Processor Unit (CPU) Core

Advance Information -- MC68HC705P6A

Section 12. Central Processor Unit (CPU) Core

12.1 Contents

12.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

12.3

Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

12.3.1

Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

12.3.2

Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

12.3.3

Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

12.3.4

Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

12.3.5

Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

12.2 Introduction

The MC68HC705P6A has an 8-K memory map. Therefore, it uses only
the lower 13 bits of the address bus. In the following discussion, the
upper three bits of the address bus can be ignored. Also, the STOP
instruction can be modified to place the MCU in either the normal stop
mode or the halt mode by means of a MOR bit. All other instructions and
registers behave as described in this section.

12.3 Registers

The MCU contains five registers which are hard-wired within the CPU
and are not part of the memory map. These five registers are shown in

Figure 12-1

and are described in the following paragraphs.

Central Processor Unit (CPU) Core

Advance Information

MC68HC705P6A -- Rev. 2.0

Central Processor Unit (CPU) Core

MOTOROLA

Figure 12-1. MC68HC05 Programming Model

12.3.1 Accumulator

The accumulator is a general-purpose 8-bit register as shown in

Figure

12-1

. The CPU uses the accumulator to hold operands and results of

arithmetic calculations or non-arithmetic operations. The accumulator is
unaffected by a reset of the device.

12.3.2 Index Register

The index register shown in

Figure 12-1

is an 8-bit register that can

perform two functions:

Indexed addressing

Temporary storage

In indexed addressing with no offset, the index register contains the low
byte of the operand address, and the high byte is assumed to be $00. In
indexed addressing with an 8-bit offset, the CPU finds the operand
address by adding the index register contents to an 8-bit immediate
value. In indexed addressing with a 16-bit offset, the CPU finds the

CONDITION CODE REGISTER

ACCUMULATOR

INDEX REGISTER

STACK POINTER

PROGRAM COUNTER

HALF-CARRY BIT (FROM BIT 3)

INTERRUPT MASK

NEGATIVE BIT

ZERO BIT

CARRY BIT

Central Processor Unit (CPU) Core

Registers

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Central Processor Unit (CPU) Core

operand address by adding the index register contents to a 16-bit
immediate value.

The index register can also serve as an auxiliary accumulator for
temporary storage. The index register is unaffected by a reset of the
device.

12.3.3 Stack Pointer

The stack pointer shown in

Figure 12-1

is a 16-bit register internally. In

devices with memory maps less than 64 Kbytes, the unimplemented
upper address lines are ignored. The stack pointer contains the address
of the next free location on the stack. During a reset or the reset stack
pointer (RSP) instruction, the stack pointer is set to $00FF. The stack
pointer is then decremented as data is pushed onto the stack and
incremented as data is pulled from the stack.

When accessing memory, the 10 most significant bits are permanently
set to 0000000011. The six least significant register bits are appended
to these 10 fixed bits to produce an address within the range of $00FF
to $00C0. Subroutines and interrupts may use up to 64 ($40) locations.
If 64 locations are exceeded, the stack pointer wraps around and writes
over the previously stored information. A subroutine call occupies two
locations on the stack and an interrupt uses five locations.

12.3.4 Program Counter

The program counter shown in

Figure 12-1

is a 16-bit register internally.

In devices with memory maps less than 64 Kbytes, the unimplemented
upper address lines are ignored. The program counter contains the
address of the next instruction or operand to be fetched.

Normally, the address in the program counter increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.

Central Processor Unit (CPU) Core

Advance Information

MC68HC705P6A -- Rev. 2.0

Central Processor Unit (CPU) Core

MOTOROLA

12.3.5 Condition Code Register

The CCR shown in

Figure 12-1

is a 5-bit register in which four bits are

used to indicate the results of the instruction just executed. The fifth bit
is the interrupt mask. These bits can be individually tested by a program,
and specific actions can be taken as a result of their state. The condition
code register should be thought of as having three additional upper bits
that are always ones. Only the interrupt mask is affected by a reset of the
device. The following paragraphs explain the functions of the lower five
bits of the condition code register.

H -- Half Carry Bit

When the half-carry bit is set, it means that a carry occurred between
bits 3 and 4 of the accumulator during the last ADD or ADC (add with
carry) operation. The half-carry bit is required for binary-coded
decimal (BCD) arithmetic operations.

I -- Interrupt Mask Bit

When the interrupt mask is set, the internal and external interrupts are
disabled. Interrupts are enabled when the interrupt mask is cleared.
When an interrupt occurs, the interrupt mask is automatically set after
the CPU registers are saved on the stack, but before the interrupt
vector is fetched. If an interrupt request occurs while the interrupt
mask is set, the interrupt request is latched. Normally, the interrupt is
processed as soon as the interrupt mask is cleared.

A return from interrupt (RTI) instruction pulls the CPU registers from
the stack, restoring the interrupt mask to its state before the interrupt
was encountered. After any reset, the interrupt mask is set and can
only be cleared by the clear I bit (CLI), STOP, or WAIT instructions.

N -- Negative Bit

The negative bit is set when the result of the last arithmetic operation,
logical operation, or data manipulation was negative. (Bit 7 of the
result was a logic one.)

The negative bit can also be used to check an often-tested flag by
assigning the flag to bit 7 of a register or memory location. Loading
the accumulator with the contents of that register or location then sets
or clears the negative bit according to the state of the flag.

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Instruction Set

101

Advance Information -- MC68HC705P6A

Section 13. Instruction Set

13.1 Contents

13.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

13.3

Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

13.3.1

Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

13.3.2

Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

13.3.3

Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

13.3.4

Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

13.3.5

Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

13.3.6

Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

13.3.7

Indexed,16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

13.3.8

Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

13.4

Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

13.4.1

13.4.2

Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . 106

13.4.3

Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 107

13.4.4

Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .109

13.4.5

Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

13.5

Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

13.6

Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

13.2 Introduction

The MCU instruction set has 62 instructions and uses eight addressing
modes. The instructions include all those of the M146805 CMOS Family
plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the
accumulator (A) and the index register (X). The high-order product is

Instruction Set

Advance Information

MC68HC705P6A -- Rev. 2.0

102

Instruction Set

MOTOROLA

stored in the index register, and the low-order product is stored in the
accumulator.

13.3 Addressing Modes

The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes provide eight different ways for the CPU to find
the data required to execute an instruction. The eight addressing modes
are:

Inherent

Immediate

Direct

Extended

Indexed, no offset

Indexed, 8-bit offset

Indexed, 16-bit offset

Relative

13.3.1 Inherent

Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.

13.3.2 Immediate

Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.

Instruction Set

Addressing Modes

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Instruction Set

103

13.3.3 Direct

Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.

13.3.4 Extended

Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.

When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.

13.3.5 Indexed, No Offset

Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000$00FF.

Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.

13.3.6 Indexed, 8-Bit Offset

Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000$01FE.

Instruction Set

Advance Information

MC68HC705P6A -- Rev. 2.0

104

Instruction Set

MOTOROLA

Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.

13.3.7 Indexed,16-Bit Offset

Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.

Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.

As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.

13.3.8 Relative

Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two's complement byte that gives
a branching range of 128 to +127 bytes from the address of the next
location after the branch instruction.

When using the Motorola assembler, the programmer does not need to
calculate the offset, because the assembler determines the proper offset
and verifies that it is within the span of the branch.

Instruction Set

Instruction Types

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Instruction Set

105

13.4 Instruction Types

The MCU instructions fall into the following five categories:

Read-modify-write instructions

Jump/branch instructions

Bit manipulation instructions

Control instructions

13.4.1 Register/Memory Instructions

These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.

Table 13-1. Register/Memory Instructions

Instruction

Mnemonic

Add Memory Byte and Carry Bit to Accumulator

ADC

Add Memory Byte to Accumulator

ADD

AND Memory Byte with Accumulator

AND

Bit Test Accumulator

BIT

Compare Accumulator

CMP

Compare Index Register with Memory Byte

CPX

EXCLUSIVE OR Accumulator with Memory Byte

EOR

Load Accumulator with Memory Byte

LDA

Load Index Register with Memory Byte

LDX

Multiply

MUL

OR Accumulator with Memory Byte

ORA

Subtract Memory Byte and Carry Bit from Accumulator

SBC

Store Accumulator in Memory

STA

Store Index Register in Memory

STX

Subtract Memory Byte from Accumulator

SUB

Instruction Set

Instruction Types

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Instruction Set

107

13.4.3 Jump/Branch Instructions

Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.

The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from 128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.

Instruction Set

Instruction Types

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Instruction Set

109

13.4.4 Bit Manipulation Instructions

The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.

13.4.5 Control Instructions

These instructions act on CPU registers and control CPU operation
during program execution.

Table 13-4. Bit Manipulation Instructions

Instruction

Mnemonic

Bit Clear

BCLR

Branch if Bit Clear

BRCLR

Branch if Bit Set

BRSET

Bit Set

BSET

Table 13-5. Control Instructions

Instruction

Mnemonic

Clear Carry Bit

CLC

Clear Interrupt Mask

CLI

No Operation

NOP

Reset Stack Pointer

RSP

Return from Interrupt

RTI

Return from Subroutine

RTS

Set Carry Bit

SEC

Set Interrupt Mask

SEI

Stop Oscillator and Enable IRQ Pin

STOP

Software Interrupt

SWI

Transfer Accumulator to Index Register

TAX

Transfer Index Register to Accumulator

TXA

Stop CPU Clock and Enable Interrupts

WAIT

Instruction Set

Advance Information

MC68HC705P6A -- Rev. 2.0

110

Instruction Set

MOTOROLA

13.5 Instruction Set Summary

Table 13-6. Instruction Set Summary (Sheet 1 of 6)

Source

Form

Operation

Description

Effect on

CCR

r
ess

eran

Cycl

H I N Z C

ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X

Add with Carry

(A) + (M) + (C)

IMM

DIR

EXT

IX2
IX1

A9
B9
C9
D9
E9
F9

hh ll

ee ff

2
3
4
5
4
3

ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X

Add without Carry

(A) + (M)

IMM

DIR

EXT

IX2
IX1

AB
BB
CB
DB
EB
FB

hh ll

ee ff

2
3
4
5
4
3

AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X

Logical AND

(A) (M)

-- --

IMM

DIR

EXT

IX2
IX1

A4
B4
C4
D4
E4
F4

hh ll

ee ff

2
3
4
5
4
3

ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X

Arithmetic Shift Left (Same as LSL)

-- --

DIR
INH
INH

IX1

38
48
58
68
78

5
3
3
6
5

ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X

Arithmetic Shift Right

-- --

DIR
INH
INH

IX1

37
47
57
67
77

5
3
3
6
5

BCC rel

Branch if Carry Bit Clear

(PC) + 2 + rel ? C = 0

-- -- -- -- --

REL

BCLR n opr

Clear Bit n

-- -- -- -- --

DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)

11
13
15
17
19

1B
1D
1F

dd
dd
dd
dd
dd
dd
dd
dd

5
5
5
5
5
5
5
5

BCS rel

Branch if Carry Bit Set (Same as BLO)

(PC) + 2 + rel ? C = 1

-- -- -- -- --

REL

BEQ rel

Branch if Equal

(PC) + 2 + rel ? Z = 1

-- -- -- -- --

REL

BHCC rel

Branch if Half-Carry Bit Clear

(PC) + 2 + rel ? H = 0

-- -- -- -- --

REL

BHCS rel

Branch if Half-Carry Bit Set

(PC) + 2 + rel ? H = 1

-- -- -- -- --

REL

BHI rel

Branch if Higher

(PC) + 2 + rel ? C Z = 0 -- -- -- -- --

REL

BHS rel

Branch if Higher or Same

(PC) + 2 + rel ? C = 0

-- -- -- -- --

REL

Instruction Set

Instruction Set Summary

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Instruction Set

111

BIH rel

Branch if IRQ Pin High

(PC) + 2 + rel ? IRQ = 1

-- -- -- -- --

REL

BIL rel

Branch if IRQ Pin Low

(PC) + 2 + rel ? IRQ = 0

-- -- -- -- --

REL

BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X

Bit Test Accumulator with Memory Byte

(A)

(M)

-- --

IMM

DIR

EXT

IX2
IX1

A5
B5
C5
D5
E5
F5

hh ll

ee ff

2
3
4
5
4
3

BLO rel

Branch if Lower (Same as BCS)

(PC) + 2 + rel ? C = 1

-- -- -- -- --

REL

BLS rel

Branch if Lower or Same

(PC) + 2 + rel ? C Z = 1 -- -- -- -- --

REL

BMC rel

Branch if Interrupt Mask Clear

(PC) + 2 + rel ? I = 0

-- -- -- -- --

REL

BMI rel

Branch if Minus

(PC) + 2 + rel ? N = 1

-- -- -- -- --

REL

BMS rel

Branch if Interrupt Mask Set

(PC) + 2 + rel ? I = 1

-- -- -- -- --

REL

BNE rel

Branch if Not Equal

(PC) + 2 + rel ? Z = 0

-- -- -- -- --

REL

BPL rel

Branch if Plus

(PC) + 2 + rel ? N = 0

-- -- -- -- --

REL

BRA rel

Branch Always

(PC) + 2 + rel ? 1 = 1

-- -- -- -- --

REL

BRCLR n opr rel Branch if Bit n Clear

(PC) + 2 + rel ? Mn = 0

-- -- -- --

DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)

01
03
05
07
09

0B
0D
0F

dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr

5
5
5
5
5
5
5
5

BRN rel

Branch Never

(PC) + 2 + rel ? 1 = 0

-- -- -- -- --

REL

BRSET n opr rel Branch if Bit n Set

(PC) + 2 + rel ? Mn = 1

-- -- -- --

DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)

00
02
04
06
08

0A
0C
0E

dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr

5
5
5
5
5
5
5
5

BSET n opr

Set Bit n

-- -- -- -- --

DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)

10
12
14
16
18

1A
1C
1E

dd
dd
dd
dd
dd
dd
dd
dd

5
5
5
5
5
5
5
5

BSR rel

Branch to Subroutine

(PC) + 2; push (PCL)

(SP) 1; push (PCH)

(SP) 1

(PC) + rel

-- -- -- -- --

REL

CLC

Clear Carry Bit

-- -- -- -- 0

INH

CLI

Clear Interrupt Mask

-- 0 -- -- --

INH

Table 13-6. Instruction Set Summary (Sheet 2 of 6)

Source

Form

Operation

Description

Effect on

CCR

r
ess

ode

cod

Ope

r
and

Cycl

H I N Z C

Instruction Set

Advance Information

MC68HC705P6A -- Rev. 2.0

112

Instruction Set

MOTOROLA

CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X

Clear Byte

$00

-- -- 0

1 --

DIR
INH
INH

IX1

3F
4F
5F
6F
7F

5
3
3
6
5

CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X

Compare Accumulator with Memory Byte

(A) (M)

-- --

IMM

DIR

EXT

IX2
IX1

A1
B1
C1
D1
E1
F1

hh ll

ee ff

2
3
4
5
4
3

COM opr
COMA
COMX
COM opr,X
COM ,X

Complement Byte (One's Complement)

(

) = $FF (M)

(

) = $FF (A)

(

) = $FF (X)

(

) = $FF (M)

(

) = $FF (M)

-- --

DIR
INH
INH

IX1

33
43
53
63
73

5
3
3
6
5

CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X

Compare Index Register with Memory Byte

(X) (M)

-- --

IMM

DIR

EXT

IX2
IX1

A3
B3
C3
D3
E3
F3

hh ll

ee ff

2
3
4
5
4
3

DEC opr
DECA
DECX
DEC opr,X
DEC ,X

Decrement Byte

(M) 1

(A) 1

(X) 1

(M) 1

-- --

DIR
INH
INH

IX1

3A
4A
5A
6A
7A

5
3
3
6
5

EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X

EXCLUSIVE OR Accumulator with Memory

Byte

(A) (M)

-- --

IMM

DIR

EXT

IX2
IX1

A8
B8
C8
D8
E8
F8

hh ll

ee ff

2
3
4
5
4
3

INC opr
INCA
INCX
INC opr,X
INC ,X

Increment Byte

(M) + 1

(A) + 1

(X) + 1

(M) + 1

-- --

DIR
INH
INH

IX1

3C
4C
5C
6C
7C

5
3
3
6
5

JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X

Unconditional Jump

Jump Address

-- -- -- -- --

DIR

EXT

IX2
IX1

BC
CC
DC
EC
FC

hh ll

ee ff

2
3
4
3
2

Table 13-6. Instruction Set Summary (Sheet 3 of 6)

Source

Form

Operation

Description

Effect on

CCR

r
ess

ode

cod

Ope

r
and

Cycl

H I N Z C

Instruction Set

Instruction Set Summary

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Instruction Set

113

JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X

Jump to Subroutine

(PC) + n (n = 1, 2, or 3)

Push (PCL); SP

(SP) 1

Push (PCH); SP

(SP) 1

Effective Address

-- -- -- -- --

DIR

EXT

IX2
IX1

BD
CD
DD
ED
FD

hh ll

ee ff

5
6
7
6
5

LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X

Load Accumulator with Memory Byte

(M)

-- --

IMM

DIR

EXT

IX2
IX1

A6
B6
C6
D6
E6
F6

hh ll

ee ff

2
3
4
5
4
3

LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X

Load Index Register with Memory Byte

(M)

-- --

IMM

DIR

EXT

IX2
IX1

AE
BE
CE
DE
EE
FE

hh ll

ee ff

2
3
4
5
4
3

LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X

Logical Shift Left (Same as ASL)

-- --

DIR
INH
INH

IX1

38
48
58
68
78

5
3
3
6
5

LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X

Logical Shift Right

-- -- 0

DIR
INH
INH

IX1

34
44
54
64
74

5
3
3
6
5

MUL

Unsigned Multiply

X : A

(X) × (A)

0 -- -- -- 0

INH

NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X

Negate Byte (Two's Complement)

(M) = $00 (M)

(A) = $00 (A)

(X) = $00 (X)

(M) = $00 (M)

-- --

DIR
INH
INH

IX1

30
40
50
60
70

5
3
3
6
5

NOP

No Operation

-- -- -- -- --

INH

ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X

Logical OR Accumulator with Memory

(A) (M)

-- --

IMM

DIR

EXT

IX2
IX1

AA
BA
CA
DA
EA

hh ll

ee ff

2
3
4
5
4
3

ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X

Rotate Byte Left through Carry Bit

-- --

DIR
INH
INH

IX1

39
49
59
69
79

5
3
3
6
5

Table 13-6. Instruction Set Summary (Sheet 4 of 6)

Source

Form

Operation

Description

Effect on

CCR

r
ess

ode

cod

Ope

r
and

Cycl

H I N Z C

Instruction Set

Advance Information

MC68HC705P6A -- Rev. 2.0

114

Instruction Set

MOTOROLA

ROR opr
RORA
RORX
ROR opr,X
ROR ,X

Rotate Byte Right through Carry Bit

-- --

DIR
INH
INH

IX1

36
46
56
66
76

5
3
3
6
5

RSP

Reset Stack Pointer

$00FF

-- -- -- -- --

INH

RTI

Return from Interrupt

(SP) + 1; Pull (CCR)

(SP) + 1; Pull (A)

(SP) + 1; Pull (X)

(SP) + 1; Pull (PCH)

(SP) + 1; Pull (PCL)

INH

RTS

Return from Subroutine

(SP) + 1; Pull (PCH)

(SP) + 1; Pull (PCL)

-- -- -- -- --

INH

SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X

Subtract Memory Byte and Carry Bit from

Accumulator

(A) (M) (C)

-- --

IMM

DIR

EXT

IX2
IX1

A2
B2
C2
D2
E2
F2

hh ll

ee ff

2
3
4
5
4
3

SEC

Set Carry Bit

-- -- -- -- 1

INH

SEI

Set Interrupt Mask

-- 1 -- -- --

INH

STA opr
STA opr
STA opr,X
STA opr,X
STA ,X

Store Accumulator in Memory

(A)

-- --

DIR

EXT

IX2
IX1

B7
C7
D7
E7
F7

hh ll

ee ff

4
5
6
5
4

STOP

Stop Oscillator and Enable IRQ Pin

-- 0 -- -- --

INH

STX opr
STX opr
STX opr,X
STX opr,X
STX ,X

Store Index Register In Memory

(X)

-- --

DIR

EXT

IX2
IX1

BF
CF
DF
EF
FF

hh ll

ee ff

4
5
6
5
4

SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X

Subtract Memory Byte from Accumulator

(A) (M)

-- --

IMM

DIR

EXT

IX2
IX1

A0
B0
C0
D0
E0
F0

hh ll

ee ff

2
3
4
5
4
3

SWI

Software Interrupt

(PC) + 1; Push (PCL)

(SP) 1; Push (PCH)

(SP) 1; Push (X)

(SP) 1; Push (A)

(SP) 1; Push (CCR)

(SP) 1; I 1

PCH

Interrupt Vector High Byte

PCL

Interrupt Vector Low Byte

-- 1 -- -- --

INH

Table 13-6. Instruction Set Summary (Sheet 5 of 6)

Source

Form

Operation

Description

Effect on

CCR

r
ess

ode

cod

Ope

r
and

Cycl

H I N Z C

Instruction Set

Opcode Map

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Instruction Set

115

13.6 Opcode Map

See

Table 13-7

TAX

Transfer Accumulator to Index Register

(A)

-- -- -- -- --

INH

TST opr
TSTA
TSTX
TST opr,X
TST ,X

Test Memory Byte for Negative or Zero

(M) $00

-- --

DIR
INH
INH

IX1

3D
4D
5D
6D
7D

4
3
3
5
4

TXA

Transfer Index Register to Accumulator

(X)

-- -- -- -- --

INH

WAIT

Stop CPU Clock and Enable Interrupts

-- 0 -- -- --

INH

Accumulator

opr

Operand (one or two bytes)

Carry/borrow flag

Program counter

CCR

Condition code register

PCH

Program counter high byte

Direct address of operand

PCL

Program counter low byte

dd rr

Direct address of operand and relative offset of branch instruction

REL

Relative addressing mode

DIR

Direct addressing mode

rel

Relative program counter offset byte

ee ff

High and low bytes of offset in indexed, 16-bit offset addressing

Relative program counter offset byte

EXT

Extended addressing mode

Stack pointer

Offset byte in indexed, 8-bit offset addressing

Index register

Half-carry flag

Zero flag

hh ll

High and low bytes of operand address in extended addressing

Immediate value

Interrupt mask

Logical AND

Immediate operand byte

Logical OR

IMM

Immediate addressing mode

Logical EXCLUSIVE OR

INH

Inherent addressing mode

( )

Contents of

Indexed, no offset addressing mode

( )

Negation (two's complement)

IX1

Indexed, 8-bit offset addressing mode

Loaded with

IX2

Indexed, 16-bit offset addressing mode

Memory location

Concatenated with

Negative flag

Set or cleared

Any bit

Not affected

Table 13-6. Instruction Set Summary (Sheet 6 of 6)

Source

Form

Operation

Description

Effect on

CCR

r
ess

ode

cod

Ope

r
and

Cycl

H I N Z C

Advance Information

MC68HC705P6A -- Rev. 2.0

116

Instruction Set

MOTOROLA

Instruction Set

l
e 1

-
7.

i
t
M

nip

t
i
on

r
a

-
M

-
W

r
it

t
r
ol

t
e

r
/M

I
R

I
N

I
X

I
N

I
M

I
R

IX2

I
X1

I
X

SET

I
R

SET

I
R

RCL

I
R

SET

I
R

SET

I
R

SBC

I
R

SBC

RCL

I
R

SET

I
R

SET

I
R

RCL

I
R

/
BL

I
R

SET

I
R

SET

I
R

RCL

I
R

ASR

I
R

SET

I
R

SET

I
R

HCC

L/LS

I
R

ASL

/
L

L/LS

I
R

RCL

I
R

HCS

I
R

SET

I
R

SET

I
R

RCL

I
R

SET

I
R

SET

I
R

INC

I
R

I
NCA

INCX

INC

I
R

RCL

I
R

BSR

I
R

SET

I
R

SET

I
R

RCL

I
R

I
T

I
R

her

ent

l
a

t
i
v

IMM

Imme

ate

I
X

ndex

ed, N

ffs

I
R

i
r
e

Index

ed, 8

-
B

i
t O

ffs

tende

I
X

Index

ed, 1

-
B

i
t
O

ffs

of O

dec

i
m

I
R

mber

l
es

ode

Mnem

oni

mber

tes

/
A

ddr

i
ng M

ode

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Electrical Specifications

117

Advance Information -- MC68HC705P6A

Section 14. Electrical Specifications

14.1 Contents

14.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

14.3

Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

14.4

Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . 118

14.5

Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

14.6

5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .119

14.7

3.3-Volt DC Electrical Charactertistics . . . . . . . . . . . . . . . . . .120

14.8

A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 121

14.9

EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . 122

14.10 SIOP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

14.11 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

14.2 Introduction

This section contains the electrical and timing specifications.

14.3 Maximum Ratings

Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.

Electrical Specifications

Advance Information

MC68HC705P6A -- Rev. 2.0

118

Electrical Specifications

MOTOROLA

The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table below. Keep V

and V

within the range

or V

)

. Connect unused inputs to the appropriate

voltage level, either V

or V

NOTE:

This device is not guaranteed to operate properly at the maximum
ratings. Refer to

14.6 5.0-Volt DC Electrical Characteristics

and

14.7 3.3-Volt DC Electrical Charactertistics

for guaranteed operating

conditions.

14.4 Operating Temperature Range

14.5 Thermal Characteristics

Rating

(1)

1. Voltages are referenced to V

Symbol

Value

Unit

Supply voltage

0.3 to +7.0

Input voltage

0.3 to

+0.3

Bootloader mode (IRQ/V

pin only)

0.3 to

2 x V

+0.3

Current drain per pin excluding V

and V

Storage temperature range

stg

65 to +150

°C

Characteristic

Symbol

Value

Unit

Operating temperature range

MC68HC705P6A (standard)
MC68HC705P6AC (extended)

to T

0 to +70

40 to +85

°C

Characteristic

Symbol

Value

Unit

Thermal resistance

PDIP
SOIC

60
60

°C/W

Electrical Specifications

5.0-Volt DC Electrical Characteristics

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Electrical Specifications

119

14.6 5.0-Volt DC Electrical Characteristics

Characteristic

(1)

Symbol

Min

Typ

(2)

Max

Unit

Output voltage

ILoad = 10.0 µA
ILoad = 10.0 µA

0.1

--
--

0.1

Output high voltage

(ILoad = 0.8 mA) PA0:7, PB5:7, PC2:7, PD5, TCMP
(ILoad = 5.0 mA) PC0:1

0.8

--
--

Output low voltage

(ILoad = 1.6 mA) PA0:7, PB5:7, PC2:7, PD5, TCMP
(ILoad = 10 mA) PC0:1

--
--

0.4
0.4

Input high voltage

PA0:7, PB5:7, PC0:7, PD5, TCAP/PD7, IRQ/V

RESET, OSC1

0.7 x V

Input low voltage

PA0:7, PB5:7, PC0:7, PD5, TCAP/PD7, IRQ/V

RESET, OSC1

0.2 x V

Supply current

(3),

(4)

Run

Wait

(5)

(A/D converter on)

Wait

(5)

(A/D converter off)

Stop

(6)

°C

°C to +70°C (standard)

°C to +85°C (extended)

--
--
--

4.0
2.0
1.3

--
--

7.0
4.0
2.0

30
50

100

mA
mA
mA

µA

I/O ports high-z leakage current

PA0:7, PB5:7, PC0:7, PD5, TCAP/PD7

±10.0

µA

A/D ports hi-z leakage current

PC3:7

±1.0

µA

Input current

RESET, IRQ/V

, OSC1, PD7/TCAP

±1.0

µA

Input pullup current

PA0:7 (with pullup enabled)

175

385

750

µA

Capaitance

Ports (as input or output)
RESET, IRQ/V

Out

--
--

1. V

= 5.0 Vdc

± 10%, V

= 0 Vdc, T

= 40

°C to +85°C, unless otherwise noted. All values shown refelect pre-silicon

estimates.

2. Typical values at midpoint of voltage range, 25

°C only.

3. Run (Operating) I

, Wait I

: To be measured using external square wave clock source (f

osc

= 4.2 MHz), all inputs 0.2 V

from rail; no dc loads, less than 50 pF on all outputs, C

= 20 pF on OSC2.

4. Wait, Stop I

: All ports configured as inputs, V

= 0.2 V, V

= V

0.2 V.

5. Wait I

will be affected linearly by the OSC2 capacitance.

6. Stop I

to be measured with OSC1 = V

Electrical Specifications

Advance Information

MC68HC705P6A -- Rev. 2.0

120

Electrical Specifications

MOTOROLA

14.7 3.3-Volt DC Electrical Charactertistics

Characteristic

(1)

Symbol

Min

Typ

(2)

Max

Unit

Output voltage

ILoad = 10.0 µA
ILoad = 10.0 µA

0.1

--
--

0.1

Output high voltage

(ILoad = 0.2 mA) PA0:7, PB5:7, PC2:7, PD5, TCMP
(ILoad = 1.2 mA) PC0:1

0.3

--
--

Output low voltage

(ILoad = 0.4 mA) PA0:7, PB5:7, PC2:7, PD5, TCMP
(ILoad = 2.5 mA) PC0:1

--
--

0.3
0.3

Input high voltage

PA0:7, PB5:7, PC0:7, PD5, TCAP/PD7, IRQ/V

RESET, OSC1

0.7 x V

Input low voltage

PA0:7, PB5:7, PC0:7, PD5, TCAP/PD7, IRQ/V

RESET, OSC1

0.2 x V

Supply current

(3),

(4)

Run

Wait

(5)

(A/D converter on)

Wait

(5)

(A/D converter off)

Stop

(6)

°C

°C to +70°C (standard)

°C to +85°C (extended)

--
--
--

1.8
1.0
0.6

--
--

2.5
1.4
1.0

20
40
50

mA
mA
mA

µA

I/O ports high-z leakage current

PA0:7, PB5:7, PC0:7, PD5, TCAP/PD7

±10.0

µA

A/D ports hi-z leakage current

PC3:7

±1.0

µA

Input current

RESET, IRQ/V

, OSC1, PD7/TCAP

±1.0

µA

Input pullup current

PA0:7 (with pullup enabled)

175

350

µA

Capaitance

Ports (as input or output)
RESET, IRQ/V

Out

--
--

1. V

= 3.3 Vdc

± 0.3 Vdc, V

= 0 Vdc, T

= 40

°C to +85°C, unless otherwise noted. All values shown reflect pre-silicon

estimates.

2. Typical values at midpoint of voltage range, 25

°C only.

3. Run (Operating) I

, Wait I

: To be measured using external square wave clock source (f

osc

= 4.2 MHz), all inputs 0.2 V

from rail; no dc loads, less than 50 pF on all outputs, C

= 20 pF on OSC2.

4. Wait, Stop I

: All ports configured as inputs, V

= 0.2 V, V

= V

0.2 V.

5. Wait I

will be affected linearly by the OSC2 capacitance.

6. Stop I

to be measured with OSC1 = V

Electrical Specifications

A/D Converter Characteristics

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Electrical Specifications

121

14.8 A/D Converter Characteristics

Characteristic

(1)

1. V

= 5.0 Vdc

± 10%, V

= 0 Vdc, T

= 40

°C to +85°C, unless otherwise noted.

Min

Max

Unit

Comments

Resolution

Bits

Absolute accuacy

REFH

> 4.0)

± 1 1/2

LSB

Including quanitization

Conversion range

REFH

A/D accuracy may decrease

proportionately as V

REFH

reduced below 4.0

Input leakage

AD0, AD1, AD2, AD3
V

REFH

--
--

± 1

µA

Conversion time

MCU external oscillator
Internal RC oscillator

--
--

32
32

cyc

µs

Includes sampling time

Monotonicity

Inherent (within total error)

Zero input reading

Hex

= 0 V

Full-scale reading

Hex

= V

REFH

Sample time

MCU external oscillator
Internal RC oscillator

--
--

12
12

cyc

µs

Input capacitance

Analog input voltage

REFH

A/D on current stabilization time

100

µs

ADON

A/D ports hi-z leakage current (PC3:7)

± 1

µA

Electrical Specifications

Control Timing

MC68HC705P6A -- Rev. 2.0

Advance Information

MOTOROLA

Electrical Specifications

123

14.11 Control Timing

Characteristic

(1)

1. V

= 5.0 Vdc ± 10%, V

= 0 Vdc, T

= 40

°C to +125°C, unless otherwise noted

Symbol

Min

Max

Unit

Frequency of operation

Crystal option
External clock option

OSC

4.2
4.2

MHz

Internal operating frequency

Crystal (f

OSC

÷ 2)

External clock (f

OSC

÷ 2)

2.1
2.1

MHz

Cycle time

CYC

476

Crystal oscillator startup time

OXOV

100

Stop mode recovery startup time (crystal oscillator)

ILCH

100

RESET pulse width

1.5

CYC

Interrupt pulse width low (edge-triggered)

ILIH

125

Interrupt pulse period

(2)

2. The minimum period, t

ILIL

, should not be less than the number of cycle times it takes to execute the interrupt service routine

plus 19 t

CYC

ILIL

Note 2

CYC

OSC1 pulse width

, t

200

A/D On current stabilization time

ADON

100

µs

Advance Information

MC68HC705P6A -- Rev. 2.0

124

Electrical Specifications

MOTOROLA

Electrical Specifications

i
gu

r
e

-2.

wer

-
On

eset

and

ter

al R

eset

i
n

i
ag

r
a

OSC

)

SET

ESS

(1)

1
FFE

1
FFF

ESH

(1-2 V

YPI

t VD

4064 t

t cy

(1)

1
FFE

W P

1
FFF

t
e

I
n

t
e

r
n

l
t

i
m

i
n

and

s in

f
o

r
m

t
i
o

t
av

e ex

t
e

r
n

l
l
y

l
i
ne i

t

m

t

t
o

r
e

t

f
r
e

enc

t
is

onl

y u

epr

t
t

i
me

t

ri

i
n

f
th

t
e

l
c

l
o

l
l
o

i
n

f
R

ESET

i
t
i
a

t
e

s t

e r

set

ce.

W P

)

Mechanical Specifications

Advance Information

MC68HC705P6A -- Rev. 2.0

126

Mechanical Specifications

MOTOROLA

15.3 Plastic Dual In-Line Package (Case 710)

15.4 Small Outline Integrated Circuit Package (Case 751F)

0.100 BSC

0.600 BSC

2.54 BSC

15.24 BSC

MIN

MAX

MILLIMETERS

INCHES

DIM

36.45

13.72

3.94

0.36

1.02

1.65

0.20

2.92

0°

0.51

37.21

14.22

5.08

0.56

1.52

2.16

0.38

3.43

15°

1.02

1.435

0.540

0.155

0.014

0.040

0.065

0.008

0.115

0°

0.020

1.465

0.560

0.200

0.022

0.060

0.085

0.015

0.135

15°

0.040

NOTES:

1. POSITIONAL TOLERANCE OF LEADS (D),

SHALL BE WITHIN 0.25mm (0.010) AT

MAXIMUM MATERIAL CONDITION, IN

RELATION TO SEATING PLANE AND

EACH OTHER.

2. DIMENSION L TO CENTER OF LEADS

WHEN FORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE

MOLD FLASH.

SEATING

PLANE

MIN

MAX

MILLIMETERS

INCHES

DIM

17.80

7.40

2.35

0.35

0.41

0.23

0.13

0°

10.05

0.25

18.05

7.60

2.65

0.49

0.90

0.32

0.29

8°

10.55

0.75

0.701

0.292

0.093

0.014

0.016

0.009

0.005

0°

0.395

0.010

0.711

0.299

0.104

0.019

0.035

0.013

0.011

8°

0.415

0.029

1.27 BSC

0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15

(0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.13

(0.005) TOTAL IN EXCESS OF D

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

-A-

-B-

-T-

SEATING

PLANE

0.010 (0.25)

-T-

26X

28X

14X

X 45

0.010 (0.25)

T A

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: C05M68HC05M

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: C05M68HC05M