MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

DSP56002

Order this document by:

DSP56002/D, Rev. 3

24-BIT DIGITAL SIGNAL PROCESSOR

The DSP56002 is a MPU-style general purpose Digital Signal Processor (DSP) composed of an
efficient 24-bit DSP core, program and data memories, various peripherals, and support
circuitry. The DSP56000 core is fed by on-chip Program RAM, and two independent data RAMs.
The DSP56002 contains a Serial Communication Interface (SCI), Synchronous Serial Interface (SSI),
parallel Host Interface (HI), Timer/Event Counter, Phase Lock Loop (PLL), and an On-Chip
Emulation (OnCETM) port. This combination of features, illustrated in

Figure 1

, makes the

DSP56002 a cost-effective, high-performance solution for high-precision general purpose digital
signal processing.

Figure 1

DSP56002 Block Diagram

Y Data

Memory

256

24 RAM

256

24 ROM

(sine)

X Data

Memory

256

24 RAM

256

24 ROM

(A-law/

-law)

Program

Memory

512

24 RAM

24 ROM

(boot)

Program Control Unit

24-bit

56000 DSP

Core

OnCETM

PLL

Clock

Gen.

24-bit

Timer/

Event

Counter

Sync.
Serial

(SSI)

or I/O

Serial

Comm.

(SCI)

or I/O

Host

Interface

(HI)

or I/O

16-bit Bus
24-bit Bus

External
Address

Bus

Switch

External

Data

Bus

Switch

Bus

Control

Data ALU

24 + 56

56-bit MAC

Two 56-bit Accumulators

IRQ

Internal

Data

Bus

Switch

Address

Generation

Unit

PAB

XAB

YAB

GDB

PDB

XDB

YDB

Address

Data

Control

Port

AA0604

Program

Address

Generator

Program

Decode

Controller

Interrupt

Control

DSP56002/D, Rev. 3

MOTOROLA

SECTION 1

PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

SECTION 2

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

SECTION 3

PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

SECTION 4

DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

SECTION 5

ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

FOR TECHNICAL ASSISTANCE:

Telephone:

1 (800) 521-6274

Email:

dsphelp@dsp.sps.mot.com

Internet:

http://www.motorola-dsp.com

Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR

Used to indicate a signal that is active when pulled low (For example, the RESET
pin is active when low.)

"asserted"

Means that a high true (active high) signal is high or that a low true (active low)
signal is low

"deasserted"

Means that a high true (active high) signal is low or that a low true (active low)
signal is high

Examples:

Signal/Symbol

Logic State

Signal State

Voltage

True

Asserted

False

Deasserted

True

Asserted

False

Deasserted

Note:

Values for V

, V

, and V

are defined by individual product specifications.

DSP56002

Features

MOTOROLA

DSP56002/D, Rev. 3

iii

FEATURES

Digital Signal Processing Core

Efficient 24-bit DSP56000 core

Up to 40 Million Instructions Per Second (MIPS), 25 ns instruction cycle at
80 MHz; up to 33 MIPS, 30.3 ns instruction cycle at 66 MHz

Up to 240 Million Operations Per Second (MOPS) at 80 MHz; up to 198 MOPS
at 66 MHz

Performs a 1024-point complex Fast Fourier Transform (FFT) in 59,898 clocks

Highly parallel instruction set with unique DSP addressing modes

Two 56-bit accumulators including extension bits

Parallel 24

24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)

Double precision 48

48-bit multiply with 96-bit result in 6 instruction cycles

56-bit addition/subtraction in 1 instruction cycle

Fractional and integer arithmetic with support for multiprecision arithmetic

Hardware support for block-floating point FFT

Hardware nested DO loops

Zero-overhead fast interrupts (2 instruction cycles)

Four 24-bit internal data buses and three 16-bit internal address buses for
maximum information transfer on-chip

Memory

On-chip Harvard architecture permitting simultaneous accesses to program
and two data memories

512

24-bit on-chip Program RAM and 64

24-bit bootstrap ROM

Two 256

24-bit on-chip data RAMs

Two 256

24-bit on-chip data ROMs containing sine, A-law, and

-law tables

External memory expansion with 16-bit address and 24-bit data buses

Bootstrap loading from external data bus, Host Interface, or Serial
Communications Interface

DSP56002/D, Rev. 3

MOTOROLA

Features

Peripheral and Support Circuits

Byte-wide host interface (HI) with Direct Memory Access (DMA) support (or
fifteen Port B GPIO lines)

SSI support:

Supports serial devices with one or more industry-standard codecs, other
DSPs, microprocessors, and Motorola-SPI-compliant peripherals

Asynchronous or synchronous transmit and receive sections with separate
or shared internal/external clocks and frame syncs

Network mode using frame sync and up to 32 software-selectable time
slots

8-bit, 12-bit, 16-bit, and 24-bit data word lengths

SCI for full duplex asynchronous communications (or three additional Port C
GPIO lines)

One 24-bit timer/event counter (or one additional GPIO line)

Double-buffered peripherals

Up to twenty-five General Purpose Input/Output (GPIO) pins

One non-maskable and two maskable external interrupt/mode control pins

On-Chip Emulation (OnCE

) port for unobtrusive, processor speed-

independent debugging

Software-programmable, Phase Lock Loop-based (PLL) frequency synthesizer
for the DSP core clock with a wide input frequency range (12.2 KHz to 80
MHz)

Miscellaneous Features

Power-saving Wait and Stop modes

Fully static, HCMOS design for specified operating frequency down to dc

Three packages available:

132-pin Plastic Quad Flat Pack (PQFP); 1.1

1.1

0.19 inches

144-pin Thin Quad Flat Pack (TQFP); 20

1.5 mm

132-pin Ceramic Pin Grid Array (PGA); 1.36

1.35

0.125 inches

DSP56002

Product Documentation

MOTOROLA

DSP56002/D, Rev. 3

PRODUCT DOCUMENTATION

The three documents listed in the following table are required for a complete description of the
DSP56002 and are necessary to design properly with the part. Documentation is available from
one of the following locations (see back cover for detailed information):

A local Motorola distributor

A Motorola semiconductor sales office

A Motorola Literature Distribution Center

The World Wide Web (WWW)

Table 1

DSP56002 Documentation

Name

Description

Order Number

DSP56000
Family Manual

Detailed description of the DSP56000 family
processor core and instruction set

DSP56KFAMUM/AD

DSP56002
User's Manual

Detailed functional description of the DSP56002
memory configuration, operation, and register
programming

DSP56002UM/AD

DSP56002
Technical Data

DSP56002 features list and physical, electrical, timing,
and package specifications

DSP56002/D

MOTOROLA

DSP56002/D, Rev. 3

1-1

SECTION

SIGNAL/PIN DESCRIPTIONS

INTRODUCTION

DSP56002 signals are organized into twelve functional groups, as summarized in

Table 1-1

Figure 1-1

is a diagram of DSP56002 signals by functional group.

Table 1-1

Signal Functional Group Allocations

Functional Group

Number

Signals

Detailed

Description

Power (V

CCX

)

Table 1-2

Ground (GND

)

Table 1-3

PLL and Clock

Table 1-4

Address Bus

Port A

Table 1-5

Data Bus

Table 1-6

Bus Control

Table 1-7

Interrupt and Mode Control

Table 1-8

Host Interface (HI) Port

Port B

Table 1-9

Serial Communications Interface (SCI) Port

Port C

Table 1-10

Synchronous Serial Interface (SSI) Port

Table 1-11

Timer/Event Counter or General Purpose Input/Output (GPIO)

Table 1-12

On-Chip Emulation (OnCE) Port

Table 1-13

Note:

Port A signals define the External Memory Interface port.

Port B signals are the HI signals multiplexed on the external pins with the GPIO signals.

Port C signals are the SCI and SSI signals multiplexed on the external pins with the GPIO signals.

1-2

DSP56002/D, Rev. 3

MOTOROLA

Signal/Pin Descriptions

Introduction

Figure 1-1

Signals Identified by Functional Group

DSP56002

Synchronous

Serial

Interface (SSI)

Port

Timer/

Event Counter

OnCE

Port

Serial

Communications

Interface (SCI)

Port

4
5

Interrupt/

Mode

Control

Host

Interface

(HI) Port

8
3

Note:

The Host Interface port signals are multiplexed with the Port B GPIO signals (PB0PB15).

The SCI and SSI signals are multiplexed with the Port C GPIO signals (PC0PC8).

Power and Ground lines are indicated for the 144-pin TQFP package.

AA1081G

CCP

CCCK

CCQ

CCA

CCD

CCC

CCH

CCS

GND

EXTAL

XTAL

CKOUT

CKP

PCAP

PINIT

PLOCK

A0A15

D0D23

X/Y

MODA
MODB
MODC
RESET

H0H7
HA0HA2
HR/W
HEN
HREQ
HACK

RXD
TXD
SCLK

SC0SC2
SCK
SRD
STD

TIO

DSCK
DSI
DSO
DR

Power Inputs:
PLL
Clock Output
Internal Logic
Address Bus
Data Bus
Bus Control
HI
SSI/SCI

Grounds:
PLL
Clock
Internal Logic
Address Bus
Data Bus
Bus Control
HI
SSI/SCI

PLL and
Clock

External
Address Bus

External
Data Bus

External
Bus
Control

PB0PB7
PB8PB10
PB11
PB12
PB13
PB14

PC0
PC1
PC2

PC3PC5
PC6
PC7
PC8

Port B

Port C

OS1
OS0

Status

IRQA
IRQB
NMI

Interrupt

Signal/Pin Descriptions

Power

MOTOROLA

DSP56002/D, Rev. 3

1-3

POWER

Table 1-2

Power

Power Names

Description

CCP

Analog PLL Circuit Power

--This line is dedicated to the analog PLL circuits

and must remain noise-free to ensure stable PLL frequency and performance.
Ensure that the input voltage to this line is well-regulated and uses an extremely
low impedance path to tie to the V

power rail. Use a 0.1

F capacitor and a

0.01

F capacitor located as close as possible to the chip package to connect

between the V

CCP

line and the GND

line.

CCCK

Clock Output Power

--This line supplies a quiet power source for the CKOUT

output. Ensure that the input voltage to this line is well-regulated and uses an
extremely low impedance path to tie to the V

power rail. Use a 0.1

F bypass

capacitor located as close as possible to the chip package to connect between the
V

CCCK

line and the GND

line.

CCQ

(4)

Oscillator Power

--These lines supply a quiet power source to the oscillator

circuits and the mode control and interrupt lines. Ensure that the input voltage
to this line is well-regulated and uses an extremely low impedance path to tie to
the V

power rail. Use a 0.1

F bypass capacitor located as close as possible to

the chip package to connect between the V

CCQ

lines and the GND

lines.

CCA

(3)

Address Bus Power

--These lines supply power to the address bus.

CCD

(3)

Data Bus Power

--These lines supply power to the data bus.

CCC

Bus Control Power

--This line supplies power to the bus control logic.

CCH

(2)

Host Interface Power

--These lines supply power to the Host Interface logic.

CCS

Serial Interface Power

--This line supplies power to the serial interface logic

(SCI and SSI).

1-4

DSP56002/D, Rev. 3

MOTOROLA

Signal/Pin Descriptions

Ground

GROUND

Table 1-3

Ground

Ground Names

Description

GND

Analog PLL Circuit Ground

--This line supplies a dedicated quiet ground

connection for the analog PLL circuits and must remain relatively noise-free to
ensure stable PLL frequency and performance. Ensure that this line connects
through an extremely low impedance path to ground. Use a 0.1

F capacitor and

a 0.01

F capacitor located as close as possible to the chip package to connect

between the V

CCP

line and the GND

line.

GND

Clock Output Ground

--This line supplies a quiet ground connection for the

CKOUT output. Ensure that this line connects through an extremely low
impedance path to ground. Use a 0.1

F bypass capacitor located as close as

possible to the chip package to connect between the V

CCCK

line and the GND

line.

GND

(4)

Oscillator Ground

--These lines supply a quiet ground connection for the

oscillator circuits and the mode control and interrupt lines. Ensure that this line
connects through an extremely low impedance path to ground. Use a 0.1

bypass capacitor located as close as possible to the chip package to connect
between the V

CCQ

line and the GND

line.

GND

(5)

Address Bus Ground

--These lines connect system ground to the address bus.

GND

(6)

Data Bus Ground

--These lines connect system ground to the data bus.

GND

Bus Control Ground

--This line connects ground to the bus control logic.

GND

(4)

Host Interface Ground

--These lines supply ground connections for the Host

Interface logic.

GND

(2)

Serial Interface Ground

--These lines supply ground connections for the serial

interface logic (SCI and SSI).

Signal/Pin Descriptions

PLL and Clock

MOTOROLA

DSP56002/D, Rev. 3

1-5

PLL AND CLOCK

Table 1-4

PLL and Clock Signals

Signal

Name

Signal

Type

State

during

Reset

Signal Description

EXTAL

Input

External Clock/Crystal Input

--This input connects the internal

oscillator input to an external crystal or to an external oscillator.

XTAL

Output

Chip-

driven

Crystal Output

--This output connects the internal crystal oscillator

output to an external crystal. If an external oscillator is used, XTAL
should be left unconnected.

CKOUT

Output

Chip-

driven

PLL Output Clock

--When the PLL is enabled and locked, this

signal provides a 50% duty cycle output clock signal synchronized
to the internal processor clock.

When the PLL is enabled and the Multiplication Factor is less than
or equal to 4, then CKOUT is synchronized to EXTAL.

When the PLL is disabled, the output clock at CKOUT is derived
from, and has the same frequency and duty cycle as, EXTAL.

Note:

For information about using the PLL Multiplication Factor,
see the

DSP56002 User's Manual

CKP

Input

PLL Output Clock Polarity Control

--The value of this signal at

reset defines the polarity of the CKOUT output relative to EXTAL. If
CKP is pulled low by connecting through a resistor to ground,
CKOUT and EXTAL have the same polarity. Pulling CKP high by
connecting it through a resistor to V

causes CKOUT and EXTAL

to be inverse polarities. The polarity of CKOUT is latched at the end
of reset; therefore, any changes to CKP after deassertion of RESET
do not affect CKOUT polarity.

PCAP

Input/

Output

Indeter-

minate

PLL Capacitor

--This signal is used to connect the required external

filter capacitor to the PLL filter. Connect one end of the capacitor to
PCAP and the other to V

CCP

. The value of the capacitor is specified

in Section 2 of this data sheet.

1-6

DSP56002/D, Rev. 3

MOTOROLA

Signal/Pin Descriptions

PLL and Clock

PINIT

Input

PLL Initialization Source

--The value of this signal at reset defines

the value written into the PLL Enable (PEN) bit in the PLL control
register.

If PINIT is pulled high during reset, the PEN bit is written as a 1,
enabling the PLL and causing the DSP internal clocks to be derived
from the PLL VCO.

If PINIT is pulled low during reset, the PEN bit is written as a 0,
disabling the PLL and causing DSP internal clocks to be derived
from the clock connected to EXTAL.

PEN is written only at the deassertion of RESET and; therefore, the
value of PINIT is ignored after that time.

PLOCK

Output

Indeter-

minate

Phase and Frequency Lock

--This output is generated by an

internal Phase Detector circuit. This circuit drives the output high
when:

the PLL is disabled (the output clock is EXTAL and is
therefore in phase with itself), or

the PLL is enabled and is locked onto the proper phase
(based on the CKP value) and frequency of EXTAL.

The circuit drives the output low (deasserted) whenever the PLL is
enabled, but has not locked onto the proper phase and frequency.

Note:

PLOCK is a reliable indicator of the PLL lock state only after
the chip has exited the Reset state. During hardware reset,
the PLOCK state is determined by PINIT and the current
PLL lock condition.

Table 1-4

PLL and Clock Signals (Continued)

Signal

Name

Signal

Type

State

during

Reset

Signal Description

Signal/Pin Descriptions

Address Bus

MOTOROLA

DSP56002/D, Rev. 3

1-7

ADDRESS BUS

DATA BUS

Table 1-5

Address Bus Signals

Signal

Names

Signal

Type

State

during

Reset

Signal Description

A0A15

Output

Tri-stated Address Bus--These signals specify the address for external

program and data memory accesses. If there is no external bus
activity, A0A15 remain at their previous values to reduce
power consumption. A0A15 are tri-stated when the bus grant
signal is asserted.

Table 1-6

Data Bus Signals

Signal

Names

Signal

Type

State

during

Reset

Signal Description

D0D23

Input/

Output

Tri-stated Data Bus--These signals provide the bidirectional data bus for

external program and data memory accesses. D0D23 are tri-
stated when the BG or RESET signal is asserted.

1-8

DSP56002/D, Rev. 3

MOTOROLA

Signal/Pin Descriptions

Bus Control

BUS CONTROL

Table 1-7

Bus Control Signals

Signal

Name

Signal

Type

State

during

Reset

Signal Description

Output Tri-stated

Program Memory Select

--PS is asserted low for external program

memory access. PS is tri-stated when the BG or RESET signal is
asserted.

Output Tri-stated

Data Memory Select

--DS is asserted low for external data memory

access. DS is tri-stated when the BG or RESET signal is asserted.

X/Y

Output Tri-stated

X/Y External Memory Select

--This output is driven low during

external Y data memory accesses. It is also driven low during external
exception vector fetches when operating in the Development mode.
X/Y is tri-stated when the BG or RESET signal is asserted.

Output Pulled

high

Bus Select--

BS is asserted when the DSP accesses the external bus,

and it acts as an early indication of imminent external bus access by
the DSP56002. It may also be used with the bus wait input WT to
generate wait states. BS is pulled high when the BG or RESET signal is
asserted.

Input

Bus Request

--When the Bus Request input (BR) is asserted, it allows

an external device, such as another processor or DMA controller, to
become the master of the external address and data buses. While the
bus is released, the DSP may continue internal operations using
internal memory spaces. When BR is deasserted, the DSP56002 is the
bus master.When BR is asserted, the DSP56002 will release Port A,
including A0A15, D0D23, and the bus control signals (PS, DS, X/Y,
RD, WR, and BS) by placing them in the high-impedance state after
execution of the current instruction has been completed.

Note:

To prevent erroneous operation, pull up the BR signal when it
is not in use.

Output Pulled

high

Bus Grant

--When this output is asserted, it grants an external

device's request for access to the external bus. This output is
deasserted during hardware reset.

Signal/Pin Descriptions

Bus Control

MOTOROLA

DSP56002/D, Rev. 3

1-9

Output Pulled

low

Bus Not Required

--The BN signal is asserted whenever the chip

requires mastership of the external bus. During instruction cycles
where the external bus is not required, BN is deasserted. If the BN
signal is asserted when the DSP is not the bus master, processing has
stopped and the chip is waiting to acquire bus ownership. An external
arbiter may use this signal to help determine when to return bus
ownership to the DSP.

Note:

The BN signal cannot be used as an early indication of
imminent external bus access because it is valid later than the
other bus control signals BS and WT.

Input

Bus Wait

--An external device may insert wait states by asserting WT

during external bus cycles.

Note:

To prevent erroneous operation, pull up the WT signal when
it is not in use.

Output Tri-stated

Write Enable

--WR is asserted low during external memory write

cycles. WR is tri-stated when the BG or RESET signal is asserted.

Output Tri-stated

Read Enable

--RD is asserted low during external memory read

cycles. RD is tri-stated when the BG or RESET signal is asserted.

Table 1-7

Bus Control Signals (Continued)

Signal

Name

Signal

Type

State

during

Reset

Signal Description

1-10

DSP56002/D, Rev. 3

MOTOROLA

Signal/Pin Descriptions

Interrupt and Mode Control

INTERRUPT AND MODE CONTROL

Table 1-8

Interrupt and Mode Control Signals

Signal Name

Signal

Type

State

during

Reset

Signal Description

MODA/IRQA

Input

Mode Select A/External Interrupt Request A

--This input has

two functions:

to select the initial chip operating mode, and

after synchronization, to allow an external device to
request a DSP interrupt.

MODA is read and internally latched in the DSP when the
processor exits the Reset state. MODA, MODB, and MODC
select the initial chip operating mode. Several clock cycles
(depending on PLL stabilization time) after leaving the Reset
state, the MODA signal changes to external interrupt request
IRQA. The chip operating mode can be changed by software
after reset. The IRQA input is a synchronized external
interrupt request that indicates that an external device is
requesting service. It may be programmed to be level-sensitive
or negative-edge-sensitive. If level-sensitive triggering is
selected, an external pull up resistor is required for wired-OR
operation. If the processor is in the Stop state and IRQA is
asserted, the processor will exit the Stop state.

MODB/IRQB Input

Input

Mode Select B/External Interrupt Request B

--This input has

two functions:

to select the initial chip operating mode, and

after internal synchronization, to allow an external
device to request a DSP interrupt.

MODB is read and internally latched in the DSP when the
processor exits the Reset state. MODA, MODB, and MODC
select the initial chip operating mode. Several clock cycles
(depending on PLL stabilization time) after leaving the Reset
state, the MODB signal changes to external interrupt request
IRQB. After reset, the chip operating mode can be changed by
software. The IRQB input is an external interrupt request that
indicates that an external device is requesting service. It may
be programmed to be level-sensitive or negative-edge-
triggered. If level-sensitive triggering is selected, an external
pull up resistor is required for wired-OR operation.

Signal/Pin Descriptions

Interrupt and Mode Control

MOTOROLA

DSP56002/D, Rev. 3

1-11

MODC/NMI

Input

Mode Select C/Non-maskable Interrupt Request

--This input

has two functions:

to select the initial chip operating mode, and

after internal synchronization, to allow an external
device to request a non-maskable DSP interrupt.

MODC is read and internally latched in the DSP when the
processor exits the Reset state. MODA, MODB, and MODC
select the initial chip operating mode. Several clock cycles
(depending on PLL stabilization time) after leaving the Reset
state, the MODC signal changes to the nonmaskable external
interrupt request NMI. After reset, the chip operating mode
can be changed by software. The NMI input is an external
interrupt request that indicates that an external device is
requesting service. It may be programmed to be level-sensitive
or negative-edge-triggered. If level-sensitive triggering is
selected, an external pull up resistor is required for wired-OR
operation.

RESET

Input

Reset

--This input is a direct hardware reset on the processor.

When RESET is asserted low, the DSP is initialized and placed
in the Reset state. A Schmitt trigger input is used for noise
immunity. When the RESET signal is deasserted, the initial
chip operating mode is latched from the MODA, MODB, and
MODC signals. The internal reset signal is deasserted
synchronous with the internal clocks. In addition, the PINIT
pin is sampled and written into the PEN bit of the PLL Control
Register and the CKP pin is sampled to determine the polarity
of the CKOUT signal.

Table 1-8

Interrupt and Mode Control Signals (Continued)

Signal Name

Signal

Type

State

during

Reset

Signal Description

1-12

DSP56002/D, Rev. 3

MOTOROLA

Signal/Pin Descriptions

Host Interface (HI) Port

HOST INTERFACE (HI) PORT

Table 1-9

HI Signals

Signal

Name

Signal

Type

State

during

Reset

Signal Description

H0H7

PB0PB7

Input

Output

Tri-stated Host Data Bus (H0H7)--This data bus transfers data between

the host processor and the DSP56002.

When configured as a Host Interface port, the H0H7signals are
tri-stated as long as HEN is deasserted. The signals are inputs
unless HR/W is high and HEN is asserted, in which case H0H7
become outputs, allowing the host processor to read the
DSP56002 data. H0H7 become outputs when HACK is asserted
during HREQ assertion.

Port B GPIO 07 (PB0PB7)

--These signals are General Purpose

I/O signals (PB0PB7) when the Host Interface is not selected.

After reset, the default state for these signals is GPIO input.

HA0HA2

PB8PB10

Input

Output

Tri-stated Host Address 0--Host Address 2 (HA0HA2)--These inputs

provide the address selection for each Host Interface register.

Port B GPIO 810 (PB8PB10)

--These signals are General

Purpose I/O signals (PB8PB10) when the Host Interface is not
selected.

After reset, the default state for these signals is GPIO input.

HR/W

PB11

Input

Output

Tri-stated Host Read/Write--This input selects the direction of data

transfer for each host processor access. If HR/W is high and HEN
is asserted, H0H7 are outputs and DSP data is transferred to the
host processor. If HR/W is low and HEN is asserted, H0H7 are
inputs and host data is transferred to the DSP. HR/W must be
stable when HEN is asserted.

Port B GPIO 11 (PB11)

--This signal is a General Purpose I/O

signal called PB11 when the Host Interface is not being used.

After reset, the default state for this signal is GPIO input.

Signal/Pin Descriptions

Host Interface (HI) Port

MOTOROLA

DSP56002/D, Rev. 3

1-13

HEN

PB12

Input

Output

Tri-stated Host Enable--This input enables a data transfer on the host data

bus. When HEN is asserted and HR/W is high, H0H7 become
outputs and the host processor may read DSP56002/L002 data.
When HEN is asserted and HR/W is low, H0H7 become
inputs. Host data is latched inside the DSP on the rising edge of
HEN. Normally, a chip select signal derived from host address
decoding and an enable strobe are used to generate HEN.

Port B GPIO 12 (PB12)

--This signal is a General Purpose I/O

signal called PB12 when the Host Interface is not being used.

After reset, the default state for this signal is GPIO input.

HREQ

PB13

Open

drain

Output

Input

Output

Tri-stated Host Request--This signal is used by the Host Interface to

request service from the host processor, DMA controller, or a
simple external controller.

Note:

HREQ should always be pulled high when it is not in
use.

Port B GPIO 13 (PB13)

--This signal is a General Purpose (not

open-drain) I/O signal (PB13) when the Host Interface is not
selected.

After reset, the default state for this signal is GPIO input.

HACK

PB14

Input

Output

Tri-stated Host Acknowledge--This input has two functions. It provides a

host acknowledge handshake signal for DMA transfers and it
receives a host interrupt acknowledge compatible with MC68000
family processors.

Note:

HACK should always be pulled high when it is not in
use.

Port B GPIO 14 (PB14)

--This signal is a General Purpose I/O

signal (PB14) when the Host Interface is not selected.

After reset, the default state for this signal is GPIO input.

Table 1-9

HI Signals (Continued)

Signal

Name

Signal

Type

State

during

Reset

Signal Description

1-14

DSP56002/D, Rev. 3

MOTOROLA

Signal/Pin Descriptions

Serial Communications Interface Port

SERIAL COMMUNICATIONS INTERFACE PORT

Table 1-10

Serial Communications Interface (SCI+) Signals

Signal Name

Signal

Type

State

during

Reset

Signal Description

RXD

PC0

Input

Output

Tri-stated Receive Data (RXD)--This input receives byte-oriented data and

transfers the data to the SCI receive shift register. Input data can be
sampled on either the positive edge or on the negative edge of the
receive clock, depending on how the SCI control register is
programmed.

Port C GPIO 0 (PC0)

--This signal is a GPIO signal called PC0

when the SCI RXD function is not being used.

After reset, the default state is GPIO input.

TXD

PC1

Output

Input

Output

Tri-stated Transmit Data (TXD)--This output transmits serial data from

the SCI transmit shift register. In the default configuration, the
data changes on the positive clock edge and is valid on the
negative clock edge. The user can reverse this clock polarity by
programming the SCI control register appropriately.

Port C GPIO 1 (PC1)

--This signal is a GPIO signal called PC1

when the SCI TXD function is not being used.

After reset, the default state is GPIO input.

SCLK

PC2

Input

Output

Tri-stated SCI Clock (SCLK)--This signal provides an input or output

clock from which the receive or transmit baud rate is derived in
the Asynchronous mode, and from which data is transferred in
the Synchronous mode. The direction and function of the signal
is defined by the RCM bit in the SCI+ Clock Control Register
(SCCR).

Port C GPIO 2 (PC2)

--This signal is a GPIO signal called PC2

when the SCI SCLK function is not being used.

After reset, the default state is GPIO input.

Signal/Pin Descriptions

Synchronous Serial Interface Port

MOTOROLA

DSP56002/D, Rev. 3

1-15

SYNCHRONOUS SERIAL INTERFACE PORT

Table 1-11

Synchronous Serial Interface (SSI) Signals

Signal Name

Signal

Type

State

during

Reset

Signal Description

SC0

PC3

Input

Output

Tri-
stated

Serial Clock 0 (SC0)--

This signal's function is determined by

whether the SCLK is in Synchronous or Asynchronous mode.

In Synchronous mode, this signal is used as a serial I/O
flag.

In Asynchronous mode, this signal receives clock I/O.

Port C GPIO 3 (PC3)

--This signal is a GPIO signal called PC3

when the SSI SC0 function is not being used.

After reset, the default state is GPIO input.

SC1

PC4

Input

Output

Tri-
stated

Serial Clock 1 (SC1)--

The SSI uses this bidirectional signal to

control flag or frame synchronization. This signal's function is
determined by whether the SCLK is in Synchronous or
Asynchronous mode.

In Asynchronous mode, this signal is frame sync I/O.

For Synchronous mode with continuous clock, this
signal is a serial I/O flag and operates like the SC0.

SC0 and SC1 are independent serial I/O flags but may be used
together for multiple serial device selection.

Port C GPIO 4 (PC4)

--This signal is a GPIO signal called PC4

when the SSI SC1 function is not being used.

After reset, the default state is GPIO input.

SC2

PC5

Input

Output

Tri-
stated

Serial Clock 2 (SC2)--

The SSI uses this bidirectional signal to

control frame synchronization only. As with SC0 and SC1, its
function is defined by the SSI operating mode.

Port C GPIO 5 (PC5)

--This signal is a GPIO signal called PC5

when the SSI SC1 function is not being used.

After reset, the default state is GPIO input.

1-16

DSP56002/D, Rev. 3

MOTOROLA

Signal/Pin Descriptions

Synchronous Serial Interface Port

SCK

PC6

Input

Output

Tri-
stated

SSI Serial Receive Clock

--This bidirectional signal provides the

serial bit rate clock for the SSI when only one clock is being used.

Port C GPIO 6 (PC6)

--This signal is a GPIO signal called PC6

when the SSI function is not being used.

After reset, the default state is GPIO input.

SRD

PC7

Input

Output

Tri-
stated

SSI Receive Data

--This input signal receives serial data and

transfers the data to the SSI Receive Shift Register.

Port C GPIO 7 (PC7)

--This signal is a GPIO signal called PC7

when the SSI SRD function is not being used.

After reset, the default state is GPIO input.

STD

PC8

Output

Input

Output

Tri-
stated

SSI Transmit Data (STD)

--This output signal transmits serial

data from the SSI Transmitter Shift Register.

Port C GPIO 8 (PC8)

--This signal is a GPIO signal called PC8

when the SSI STD function is not being used.

After reset, the default state is GPIO input.

Table 1-11

Synchronous Serial Interface (SSI) Signals (Continued)

Signal Name

Signal

Type

State

during

Reset

Signal Description

Signal/Pin Descriptions

Timers

MOTOROLA

DSP56002/D, Rev. 3

1-17

TIMERS

Table 1-12

Timer Signals

Signal Name

Signal

Type

State

during

Reset

Signal Description

TIO

Input

Output

Tri-
stated

Timer Input/Output

--The TIO signal provides an interface to the

timer/event counter module. When the module functions as an
external event counter or is used to measure external pulse width/
signal period, the TIO is an input. When the module functions as a
timer, the TIO is an output, and the signal on the TIO signal is
the timer pulse.

When not used by the timer module, the TIO can be
programmed through the Timer Control/Status Register
(TCSR) to be a General Purpose I/O signal.

TIO is effectively disconnected upon leaving reset.

1-18

DSP56002/D, Rev. 3

MOTOROLA

Signal/Pin Descriptions

On-Chip Emulation Port

On-CHIP EMULATION PORT

Table 1-13

On-Chip Emulation (OnCE) Signals

Signal Name

Signal

Type

State

during

Reset

Signal Description

DSI/OS0

Input

Output

Low

Output

Debug Serial Input/Chip Status 0

--Serial data or commands

are provided to the OnCE controller through the DSI/OS0 signal
when it is an input. The data received on the DSI signal will be
recognized only when the DSP has entered the Debug mode of
operation. Data is latched on the falling edge of the DSCK serial
clock. Data is always shifted into the OnCE serial port Most
Significant Bit (MSB) first. When the DSI/OS0 signal is an
output, it works in conjunction with the OS1 signal to provide
chip status information. The DSI/OS0 signal is an output when
the processor is not in Debug mode. When switching from
output to input, the signal is tri-stated.

Note:

Connect an external pull-down resistor to this signal.

DSCK/OS1

Input

Output

Low

Output

Debug Serial Clock/Chip Status 1

--The DSCK/OS1 signal

supplies the serial clock to the OnCE when it is an input. The
serial clock provides pulses required to shift data into and out of
the OnCE serial port. (Data is clocked into the OnCE on the
falling edge and is clocked out of the OnCE serial port on the
rising edge.) The debug serial clock frequency must be no
greater than

of the processor clock frequency. When

switching from input to output, the signal is tri-stated.

When it is an output, this signal works with the OS0 signal to
provide information about the chip status. The DSCK/OS1 signal
is an output when the chip is not in Debug mode.

Note:

Connect an external pull-down resistor to this signal.

Signal/Pin Descriptions

On-Chip Emulation Port

MOTOROLA

DSP56002/D, Rev. 3

1-19

DSO

Output

Pulled

high

Debug Serial Output

--Data contained in one of the OnCE

controller registers is provided through the DSO output signal,
as specified by the last command received from the external
command controller. Data is always shifted out the OnCE serial
port Most Significant Bit (MSB) first. Data is clocked out of the
OnCE serial port on the rising edge of DSCK.

The DSO signal also provides acknowledge pulses to the
external command controller. When the chip enters the Debug
mode, the DSO signal will be pulsed low to indicate
(acknowledge) that the OnCE is waiting for commands. After
the OnCE receives a read command, the DSO signal will be
pulsed low to indicate that the requested data is available and
the OnCE serial port is ready to receive clocks in order to deliver
the data. After the OnCE receives a write command, the DSO
signal will be pulsed low to indicate that the OnCE serial port is
ready to receive the data to be written; after the data is written,
another acknowledge pulse will be provided.

Note:

Connect an external pull-up resistor to this signal.

Input

Debug Request

--The debug request input (DR) allows the user

to enter the Debug mode of operation from the external
command controller. When DR is asserted, it causes the DSP to
finish the current instruction being executed, save the instruction
pipeline information, enter the Debug mode, and wait for
commands to be entered from the DSI line. While in Debug
mode, the DR signal lets the user reset the OnCE controller by
asserting it and deasserting it after receiving acknowledge. It
may be necessary to reset the OnCE controller in cases where
synchronization between the OnCE controller and external
circuitry is lost. DR must be deasserted after the OnCE responds
with an acknowledge on the DSO signal and before sending the
first OnCE command. Asserting DR will cause the chip to exit
the Stop or Wait state. Having DR asserted during the
deassertion of RESET will cause the DSP to enter Debug mode.

Note:

Connect an external pull-up resistor to this signal.

Table 1-13

On-Chip Emulation (OnCE) Signals (Continued)

Signal Name

Signal

Type

State

during

Reset

Signal Description

MOTOROLA

DSP56002/D, Rev. 3

2-1

SECTION

SPECIFICATIONS

GENERAL CHARACTERISTICS

The DSP56002 is fabricated in high-density HCMOS with TTL compatible inputs and
outputs.

MAXIMUM RATINGS

Note:

In the calculation of timing requirements, adding a maximum value of one
specification to a minimum value of another specification does not yield a
reasonable sum. A maximum specification is calculated using a worst case
variation of process parameter values in one direction. The minimum
specification is calculated using the worst case for the same parameters in the
opposite direction. Therefore, a "maximum" value for a specification will
never occur in the same device that has a "minimum" value for another
specification; adding a maximum to a minimum represents a condition that
can never exist.

CAUTION

This device contains circuitry protecting
against damage due to high static voltage or
electrical fields; however, normal precautions
should be taken to avoid exceeding maximum
voltage ratings. Reliability is enhanced if
unused inputs are tied to an appropriate logic
voltage level (e.g., either GND or V

2-2

DSP56002/D, Rev. 3

MOTOROLA

Specifications

Thermal characteristics

THERMAL CHARACTERISTICS

Table 2-1

Absolute Maximum Ratings (GND = 0 V)

Rating

Symbol

Value

Unit

Supply Voltage

0.3 to +7.0

All Input Voltages

(GND 0.5) to (V

+ 0.5)

Current Drain per Pin excluding V

and GND

Operating Temperature Range

40 to +105

Storage Temperature

stg

55 to +150

Table 2-2

Thermal Characteristics

Characteristic

Symbol

PQFP

Value

TQFP

Value

TQFP

Value

PGA

Value

Unit

Junction-to-ambient
thermal resistance

40.6

C/W

Junction-to-case
thermal resistance

12.4

10.8

6.5

C/W

Thermal
characterization
parameter

4.0

0.16

N/A

C/W

Notes:

Junction-to-ambient thermal resistance is based on measurements on a horizontal-single-sided
Printed Circuit Board per SEMI G38-87 in natural convection.(SEMI is Semiconductor Equipment and
Materials International, 805 East Middlefield Rd., Mountain View, CA 94043, (415) 964-5111)
Measurements were made with the parts installed on thermal test boards meeting the specification
EIA/JEDECSI-3.

Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88,
with the exception that the cold plate temperature is used for the case temperature.

These are measured values. See note 1 for test board conditions.

These are measured values; testing is not complete. Values were measured on a non-standard four-
layer thermal test board (two internal planes) at one watt in a horizontal configuration.

Specifications

DC Electrical Characteristics

MOTOROLA

DSP56002/D, Rev. 3

2-3

DC ELECTRICAL CHARACTERISTICS

Table 2-3

DC Electrical Characteristics

Characteristics

Symbol

Min

Typ

Max

Units

Supply Voltage

4.5

5.0

5.5

Input High Voltage

EXTAL

RESET

MODA, MODB, MODC

All other inputs

IHC

IHR

IHM

4.0
2.5
3.5
2.0

--
--
--
--

V
V
V
V

Input Low Voltage

EXTAL

MODA, MODB, MODC

All other inputs

ILC

ILM

0.5
0.5
0.5

--
--
--

0.6
2.0
0.8

V
V
V

Input Leakage Current

EXTAL, RESET, MODA/IRQA, MODB/IRQB,
MODC/NMI, DR, BR, WT, CKP, PINIT, MCBG,
MCBCLR, MCCLK, D20IN

Tri-state (Offstate) Input Current (@ 2.4 V/0.4 V)

TSI

Output High Voltage (I

= 0.4 mA)

2.4

Output Low Voltage (I

= 3.0 mA)

HREQ I

= 6.7 mA, TXD I

= 6.7 mA

0.4

Internal Supply Current at 40 MHz

In Wait mode

In Stop mode

CCI

CCW

CCS

--
--
--

90
12

105

20
95

mA
mA

Internal Supply Current at 66 MHz

In Wait mode

In Stop mode

CCI

CCW

CCS

--
--
--

95
15

130

25
95

mA
mA

Internal Supply Current at 80 MHz

In Wait mode

In Stop mode

CCI

CCW

CCS

--
--
--

115

160

30
95

mA
mA

PLL Supply Current

40 MHz

66 MHz

80 MHz

--
--
--

1.0
1.1
1.2

1.5
1.5
1.8

mA
mA
mA

CKOUT Supply Current

40 MHz

66 MHz

80 MHz

--
--
--

14
28
34

20
35
42

mA
mA
mA

Input Capacitance

Notes:

Section 4 Design Considerations

describes how to calculate the external supply current.

In order to obtain these results all inputs must be terminated (i.e., not allowed to float).

Values are given for PLL enabled.

Values are given for CKOUT enabled.

Periodically sampled and not 100% tested

2-4

DSP56002/D, Rev. 3

MOTOROLA

Specifications

AC Electrical Characteristics

AC ELECTRICAL CHARACTERISTICS

The timing waveforms in the AC Electrical Characteristics are tested with a V

maximum of 0.5 V and a V

minimum of 2.4 V for all pins, except EXTAL,

RESET

MODA, MODB, and MODC. These pins are tested using the input levels set forth in
the DC Electrical Characteristics. AC timing specifications that are referenced to a
device input signal are measured in production with respect to the 50% point of the
respective input signal's transition. DSP56002 output levels are measured with the
production test machine V

and V

reference levels set at 0.8 V and 2.0 V,

respectively.

Figure 2-1 Signal Measurement Reference

Fall Time

Input

Signal

Note:

The midpoint is V

+ (V

)/2.

Midpoint1

Low

High

Pulse Width

90%

50%

10%

Rise Time

AA0179

Specifications

Internal Clocks

MOTOROLA

DSP56002/D, Rev. 3

2-5

INTERNAL CLOCKS

For each occurrence of T

, T

or I

CYC

, substitute with the numbers in

Table 2-4

DF and MF are PLL division and multiplication factors set in registers.

Table 2-4

Internal Clocks

Characteristics

Symbol

Expression

Internal Operation Frequency

Internal Clock High Period
· With PLL disabled
· With PLL enabled and MF

· With PLL enabled and MF > 4

(Min) 0.48

(Max) 0.52

(Min) 0.467

(Max) 0.533

Internal Clock Low Period
· With PLL disabled
· With PLL enabled and MF

· With PLL enabled and MF > 4

(Min) 0.48

(Max) 0.52

(Min) 0.467

(Max) 0.533

Internal Clock Cycle Time

DF/MF

Instruction Cycle Time

CYC

2-6

DSP56002/D, Rev. 3

MOTOROLA

Specifications

External Clock (EXTAL Pin)

EXTERNAL CLOCK (EXTAL PIN)

The DSP56002 system clock may be derived from the on-chip crystal oscillator as
shown in

Figure 2-2

, or it may be externally supplied. An externally supplied square

wave voltage source should be connected to EXTAL, leaving XTAL physically
unconnected to the board or socket. The rise and fall times of this external clock
should be 4 ns maximum.

Figure 2-2 Crystal Oscillator Circuits

Suggested Component Values
R = 680 k

10%

C = 20 pf

20%

Fundamental Frequency

Crystal Oscillator

3rd Overtone

Crystal Oscillator

Suggested Component Values
R1 = 470 k

10%

R2 = 330

10%

C1 = 0.1

20%

C2 = 26 pf

20%

C3 = 20 pf

10%

L1 = 2.37

10%

XTAL = 40 MHz, AT cut, 20 pf load,
50

max series resistance

Note:

The suggested crystal source is
ICM, # 433163 - 4.00
(4 MHz fundamental, 20 pf load) or
# 436163 - 30.00
(30 MHz fundamental, 20 pf load).

To reduce system cost, a ceramic
resonator may be used instead of
the crystal. Suggested source:
Murata-Erie #CST4.00MGW040
(4 MHz with built-in load
capacitors)

Note:

overtone crystal.

The suggested crystal source is ICM,
# 471163 - 40.00 (40 MHz 3

overtone,

20 pf load).

R2 limits crystal current.

Reference Benjamin Parzen, The Design
of Crystal and Other Harmonic
Oscillators, John Wiley & Sons, 1983.

XTAL EXTAL

XTAL1

XTAL1*

EXTAL

XTAL

AA0211

Specifications

External Clock (EXTAL Pin)

MOTOROLA

DSP56002/D, Rev. 3

2-7

Figure 2-3 External Clock Timing

Table 2-5

Clock Operation

Num

Characteristics

Symbol

40 MHz

66 MHz

80 MHz

Unit

Min Max

Frequency of Operation
(EXTAL Pin)

MHz

Clock Input High
·

With PLL disabled

(46.7% 53.3% duty cycle)

With PLL enabled

(42.5% 57.5% duty cycle)

11.7

10.5

235.5

7.09

6.36

235.5

5.8

5.3

235.5

Clock Input Low
·

With PLL disabled

(46.7% 53.3% duty cycle)

With PLL enabled

(42.5% 57.5% duty cycle)

11.7

10.5

235.5

7.09

6.36

235.5

5.8

5.3

235.5

Clock Cycle Time
·

With PLL disabled

With PLL enabled

25
25

409.6

15.15
15.15

409.6

12.5
12.5

409.6

Instruction Cycle Time =

CYC

= 2T

With PLL disabled

With PLL enabled

CYC

50
50

819.2

30.3
30.3

819.2

25
25

819.2

Note:

External Clock Input High and External Clock Input Low are measured at 50% of the input
transition.

EXTAL

IHC

ILC

Midpoint

NOTE: The midpoint is V

ILC

+ 0.5 (V

IHC

ILC

AA0360

2-8

DSP56002/D, Rev. 3

MOTOROLA

Specifications

Phase Lock Loop (PLL) Characteristics

PHASE LOCK LOOP (PLL) CHARACTERISTICS

RESET, STOP, MODE SELECT, AND INTERRUPT TIMING

= 50 pF + 2 TTL loads

WS = number of Wait States (015) programmed into the external bus access using BCR
1 Wait State = T

Table 2-6

Phase Lock Loop (PLL) Characteristics

Characteristics

Expression

Min

Max

Unit

VCO frequency when PLL enabled

1,2,3

MHz

PLL external capacitor

(PCAP pin to V

CCP

)

Cpcap

@ MF

@ MF > 4

340

380

480

970

pF
pF

Notes:

The E in ET

, ET

, and ET

means external.

MF is the PCTL Multiplication Factor bits (MF0MF11).

The maximum VCO frequency is limited to the internal operation frequency.

Cpcap is the value of the PLL capacitor (connected between PCAP pin and V

CCP

) for MF = 1.

The recommended value for Cpcap is: 400 pF for MF

4 and 540 pF for MF > 4.

Table 2-7

Reset, Stop, Mode Select, and Interrupt Timing (All Frequencies)

Num

Characteristics

Min

Max

Unit

Delay from RESET Assertion to Address High Impedance
(periodically sampled and not 100% tested).

Minimum Stabilization Duration

Internal Oscillator PLL Disabled

External clock PLL Disabled

External clock PLL Enabled

75000T

25T

2500T

--
--
--

ns
ns
ns

Delay from Asynchronous RESET Deassertion to First
External Address Output (Internal Reset Deassertion)

+ 20

Synchronous Reset Setup Time from RESET Deassertion to
first CKOUT transition

8.5

Synchronous Reset Delay Time from the first CKOUT
transition to the First External Address Output

+ 6

Mode Select Setup Time

Mode Select Hold Time

Minimum Edge-Triggered Interrupt Request Assertion
Width

Specifications

RESET, Stop, Mode Select, and Interrupt Timing

MOTOROLA

DSP56002/D, Rev. 3

2-9

16a Minimum Edge-Triggered Interrupt Request Deassertion

Width

Delay from IRQA, IRQB, NMI Assertion to External Memory
Access Address Out Valid

Caused by First Interrupt Instruction Fetch

Caused by First Interrupt Instruction Execution

+ T

--
--

ns
ns

Delay from IRQA, IRQB, NMI Assertion to General Purpose
Transfer Output Valid caused by First Interrupt Instruction
Execution

11T

+ T

Delay from Address Output Valid caused by First Interrupt
Instruction Execute to Interrupt Request
Deassertion for Level Sensitive Fast Interrupts

2 T

+ T

WS) 23

Delay from RD Assertion to Interrupt Request
Deassertion for Level Sensitive Fast Interrupts

WS) 21

Delay from WR Assertion to Interrupt Request Deassertion
for Level Sensitive Fast Interrupts

WS = 0

WS > 0

--
--

+ T

WS) 21

ns
ns

Delay from General-Purpose Output Valid to Interrupt
Request Deassertion for Level Sensitive Fast Interrupts

--If Second Interrupt Instruction is:

Single Cycle

Two Cycles

--
--

+ T

ns
ns

Synchronous Interrupt Setup Time from IRQA, IRQB, NMI
Assertion to the second CKOUT transition

Synchronous Interrupt Delay Time from the second CKOUT
transition to the First External Address Output Valid caused
by the First Instruction Fetch after coming out of Wait State

13T

+ T

13T

+ T

+ 6

Duration for IRQA Assertion to Recover from Stop State

Delay from IRQA Assertion to Fetch of First Interrupt
Instruction (when exiting `Stop')

Internal Crystal Oscillator Clock, OMR bit 6 = 0

Stable External Clock, OMR Bit 6 = 1

Stable External Clock, PCTL Bit 17 = 1

65548T

20T

13T

--
--
--

ns
ns
ns

Duration of Level Sensitive IRQA Assertion to ensure
interrupt service (when exiting `Stop')

Internal Crystal Oscillator Clock, OMR bit 6 = 0

Stable External Clock, OMR Bit 6 = 1

Stable External Clock, PCTL Bit 17 = 1

65534T

+ T

--
--
--

ns
ns
ns

Table 2-7

Reset, Stop, Mode Select, and Interrupt Timing (All Frequencies) (Continued)

Num

Characteristics

Min

Max

Unit

2-10

DSP56002/D, Rev. 3

MOTOROLA

Specifications

RESET, Stop, Mode Select, and Interrupt Timing

Delay from Level Sensitive IRQA Assertion to Fetch of First
Interrupt Instruction (when exiting `Stop')

Internal Crystal Oscillator Clock, OMR bit 6 = 0

Stable External Clock, OMR bit 6 = 1

Stable External Clock, PCTL bit 17= 1

65548T

20T

13T

--
--
--

ns
ns
ns

Notes:

A clock stabilization delay is required when using the on-chip crystal oscillator in two cases:
· after power-on reset, and
· when recovering from Stop mode.
During this stabilization period, T

, T

and T

will not be constant. Since this stabilization period

varies, a delay of 75,000

is typically allowed to assure that the oscillator is stable before executing

programs.

Circuit stabilization delay is required during reset when using an external clock in two cases:
· after power-on reset, and
· when recovering from Stop mode.

When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timings 19 through
22 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-
triggered mode is recommended when using fast interrupt. Long interrupts are recommended when
using Level-sensitive mode.

Figure 2-4 Reset Timing

Figure 2-5 Synchronous Reset Timing

Table 2-7

Reset, Stop, Mode Select, and Interrupt Timing (All Frequencies) (Continued)

Num

Characteristics

Min

Max

Unit

IHR

First Fetch

RESET

A0A15

AA0356

CKOUT

RESET

A0-A15,

DS, PS

X/Y

AA0357

Specifications

RESET, Stop, Mode Select, and Interrupt Timing

MOTOROLA

DSP56002/D, Rev. 3

2-11

Figure 2-6 Operating Mode Select Timing

Figure 2-7 External Level-Sensitive Fast Interrupt Timing

IHM

ILM

IHR

RESET

MODA, MODB

MODC

IRQA, IRQB,
NMI

AA0358

First Interrupt Instruction Execution/Fetch

a) First Interrupt Instruction Execution

b) General Purpose I/O

A0A15

IRQA
IRQB

NMI

General

Purpose

I/O

IRQA
IRQB

NMI

AA0359

2-12

DSP56002/D, Rev. 3

MOTOROLA

Specifications

RESET, Stop, Mode Select, and Interrupt Timing

Figure 2-8 External Interrupt Timing (Negative Edge-Triggered)

Figure 2-9 Synchronous Interrupt from Wait State Timing

Figure 2-10 Recovery from Stop State Using IRQA

Figure 2-11 Recovery from Stop State Using IRQA Interrupt Service

16A

IRQA, IRQB

NMI

IRQA, IRQB

NMI

AA0361

T0, T2

T1, T3

CKOUT

IRQA, IRQB

NMI

AA0362

A0A15,

DS, PS

X/Y

First Instruction Fetch

IRQA

AA0363

A0A15,

DS, PS

X/Y

IRQA

A0A15,

DS, PS

X/Y

First IRQA Interrupt

Instruction Fetch

AA0364

Specifications

Host I/O (HI) Timing

MOTOROLA

DSP56002/D, Rev. 3

2-13

HOST I/O (HI) TIMING

= 50 pF + 2 TTL loads

Note:

Active low lines should be "pulled up" in a manner consistent with the ac and
dc specifications.

Table 2-8

Host I/O Timing (All Frequencies)

Num

Characteristics

Min Max

Unit

HEN/HACK Assertion Width

CVR, ICR, ISR, RXL Read

IVR, RXH/M Read

Write

+ 31

26
13

--
--
--

HEN/HACK Deassertion Width

Between Two TXL Writes

Between Two CVR, ICR, ISR, RXL Reads

+ 31

--
--
--

ns
ns
ns

Host Data Input Setup Time Before HEN/HACK
Deassertion

Host Data Input Hold Time After HEN/HACK
Deassertion

HEN/HACK Assertion to Output Data
Active from High Impedance

HEN/HACK Assertion to Output Data Valid

HEN/HACK Deassertion to Output Data High
Impedance

Output Data Hold Time After HEN/HACK
Deassertion

2.5

HR/W Low Setup Time Before HEN Assertion

HR/W Low Hold Time After HEN Deassertion

HR/W High Setup Time to HEN Assertion

HR/W High Hold Time After HEN/HACK
Deassertion

HA0HA2 Setup Time Before HEN Assertion

HA0HA2 Hold Time After HEN Deassertion

DMA HACK Assertion to HREQ Deassertion

DMA HACK Deassertion to HREQ Assertion

4,5

For DMA RXL Read

For DMA TXL Write

All other cases

+ T

--
--
--

ns
ns
ns

2-14

DSP56002/D, Rev. 3

MOTOROLA

Specifications

Host I/O (HI) Timing

Delay from HEN Deassertion to HREQ
Assertion for RXL Read

4,5

+ T

Delay from HEN Deassertion to HREQ
Assertion for TXL Write

4,5

+ T

Delay from HEN Assertion to HREQ
Deassertion for RXL Read, TXL Write

4,5

Notes:

See

Host Port Considerations

Section 4

This timing must be adhered to only if two consecutive writes to the TXL are executed without polling
TXDE or HREQ.

This timing must be adhered to only if two consecutive reads from one of these registers are executed
without polling the corresponding status bits or HREQ

HREQ is pulled up by a 1 k

resistor.

Specifications are periodically sampled and not 100% tested.

May decrease to 0 ns for future versions.

Figure 2-12 Host Interrupt Vector Register (IVR) Read

Table 2-8

Host I/O Timing (Continued)(All Frequencies) (Continued)

Num

Characteristics

Min Max

Unit

HREQ

(Output)

HACK

(Input)

HR/W

(Input)

H0H7

(Output)

AA1084

Data Valid

Specifications

Host I/O (HI) Timing

MOTOROLA

DSP56002/D, Rev. 3

2-15

Figure 2-13 Host Read Cycle (Non-DMA Mode)

Figure 2-14 Host Write Cycle (Non-DMA Mode)

HREQ

(Output)

HEN

(Input)

HA2HA0

(Input)

HR/W

(Input)

H0H7

(Output)

AA1113

Data

Valid

Address Valid

Data

Valid

Data

Valid

RXH

Read

RXM

Read

RXL

Read

HREQ

(Output)

HEN

(Input)

HA2HA0

(Input)

HR/W

(Input)

H0H7

(Output)

AA1114

Data

Valid

Address Valid

TXH

Write

TXM

Write

TXL

Write

Data

Valid

Data

Valid

Specifications

Serial Communication Interface (SCI) Timing

MOTOROLA

DSP56002/D, Rev. 3

2-17

SERIAL COMMUNICATION INTERFACE (SCI) TIMING

= 50 pF + 2 TTL loads

SCC

= Synchronous Clock Cycle Time (For internal clock, t

SCC

is determined by the SCI Clock

Control Register and T

) The minimum t

SCC

value is 8

Table 2-9

SCI Synchronous Mode Timing (All Frequencies)

Num

Characteristics

Min Max

Unit

Synchronous Clock Cycle--t

SCC

Clock Low Period

SCC

/2 10.5

Clock High Period

SCC

/2 10.5

< intentionally blank >

Output Data Setup to Clock Falling Edge
(Internal Clock)

SCC

/4 + T

Output Data Hold After Clock Rising Edge
(Internal Clock)

SCC

/4 T

Input Data Setup Time Before Clock
Rising Edge (Internal Clock)

SCC

/4 + T

+ 23

Input Data Not Valid Before Clock Rising
Edge (Internal Clock)

SCC

/4 + T

5.5

Clock Falling Edge to Output Data Valid
(External Clock)

32.5

Output Data Hold After Clock Rising Edge
(External Clock)

+ 3

Input Data Setup Time Before Clock
Rising Edge (External Clock)

Input Data Hold Time After Clock Rising
Edge (External Clock)

Table 2-10

SCI Asynchronous Mode Timing--1X Clock

Num

Characteristics

Min Max

Unit

Asynchronous Clock Cycle--t

ACC

64T

Clock Low Period

ACC

/2 11

Clock High Period

ACC

/2 11

< intentionally blank >

Output Data Setup to Clock Rising Edge (Internal
Clock)

ACC

/2 51

Output Data Hold After Clock Rising Edge
(Internal Clock)

ACC

/2 51

2-18

DSP56002/D, Rev. 3

MOTOROLA

Specifications

Serial Communication Interface (SCI) Timing

Figure 2-17 SCI Synchronous Mode Timing

Figure 2-18 SCI Asynchronous Mode Timing

a) Internal Clock

Data Valid

Data

Valid

b) External Clock

Data Valid

RCLK

TCLK

(Output)

TXD

RXD

RCLK

TCLK

(Input)

TXD

RXD

Data Valid

AA0388

1X TCLK

(Output)

TXD

Data Valid

Note:

In the wire-OR mode, TXD can be pulled up by 1 k

AA0389

Specifications

Synchronous Serial Interface (SSI) Timing

MOTOROLA

DSP56002/D, Rev. 3

2-19

SYNCHRONOUS SERIAL INTERFACE (SSI) TIMING

= 50 pF + 2 TTL loads

SSICC

= SSI clock cycle time

TXC (SCK Pin) = Transmit Clock
RXC (SC0 or SCK Pin) = Receive Clock
FST (SC2 Pin) = Transmit Frame Sync
FSR (SC1 or SC2 Pin) = Receive Frame Sync
i ck = Internal Clock
x ck = External Clock
g ck = Gated Clock
i ck a = Internal Clock, Asynchronous Mode (Asynchronous implies that

STD and SRD are two different clocks)

i ck s = Internal Clock, Synchronous Mode (Synchronous implies that

STD and SRD are the same clock)

bl = bit

length

wl = word length

Table 2-11

SSI Timing

Num

Characteristics

40 MHZ or 66 MHz

80 MHz

Case Unit

Min Max

Clock Cyclet

SSICC

--
--

i ck

x ck

Clock High Period

SSICC

/2 10.8

+ T

--
--

+ 5

--
--

i ck

x ck

Clock Low Period

SSICC

/2 10.8

+ T

--
--

+ 5

--
--

i ck

x ck

RXC Rising Edge to
FSR Out (bl) High

--
--

40.8
25.8

--
--

25.8

x ck

i ck a

RXC Rising Edge to
FSR Out (bl) Low

--
--

35.8
25.8

--
--

25.8

x ck

i ck a

RXC Rising Edge to
FSR Out (wl) High

--
--

35.8
20.8

--
--

20.8

x ck

i ck a

RXC Rising Edge to
FSR Out (wl) Low

--
--

35.8
20.8

--
--

20.8

x ck

i ck a

Data In Setup Time
Before RXC (SCK in
Synchronous Mode)
Falling Edge

3.3

15.8

--
--
--

3.3

15.8

--
--
--

x ck

i ck a

i ck s

2-20

DSP56002/D, Rev. 3

MOTOROLA

Specifications

Synchronous Serial Interface (SSI) Timing

Data In Hold Time
After RXC Falling
Edge

3.3

--
--

3.3

--
--

x ck

i ck

FSR Input (bl) High
Before RXC Falling
Edge

0.8

17.4

--
--

0.8

17.4

--
--

x ck

i ck a

FSR Input (wl) High
Before RXC Falling
Edge

3.3

18.3

--
--

3.3

18.3

--
--

x ck

i ck a

FSR Input Hold
Time After RXC
Falling Edge

18.3

3.3

--
--

18.3

3.3

--
--

x ck

i ck

Flags Input Setup
Before RXC Falling
Edge

0.8

16.7

--
--

0.8

16.7

--
--

x ck

i ck s

Flags Input Hold
Time After RXC
Falling Edge

18.3

3.3

--
--

18.3

3.3

--
--

x ck

i ck s

TXC Rising Edge to
FST Out (bl) High

--
--

31.6
15.8

--
--

15.8

x ck

i ck

TXC Rising Edge to
FST Out (bl) Low

--
--

33.3
18.3

--
--

18.3

x ck

i ck

TXC Rising Edge to
FST Out (wl) High

--
--

30.8
18.3

--
--

18.3

x ck

i ck

TXC Rising Edge to
FST Out (wl) Low

--
--

33.3
18.3

--
--

18.3

x ck

i ck

TXC Rising Edge to
Data Out Enable
from High
Impedance

33.3 +

20.8

x ck

i ck

100

TXC Rising Edge to
Data Out Valid

33.3 +

22.4

x ck

i ck

101

TXC Rising Edge to
Data Out High
Impedance

--
--

35.8
20.8

--
--

20.8

x ck

i ck

Table 2-11

SSI Timing (Continued)

Num

Characteristics

40 MHZ or 66 MHz

80 MHz

Case Unit

Min Max

Specifications

Synchronous Serial Interface (SSI) Timing

MOTOROLA

DSP56002/D, Rev. 3

2-21

101A TXC Falling Edge to

Data Out High
Impedance

+ T

g ck

102

FST Input (bl) Setup
Time Before TXC
Falling Edge

0.8

18.3

0.8

18.3

x ck

i ck

103

FST Input (wl) to
Data Out Enable
from High
Impedance

30.8

104

FST Input (wl)
Setup Time Before
TXC Falling Edge

0.8

20.0

--
--

0.8

20.0

--
--

x ck

i ck

105

FST Input Hold
Time After TXC
Falling Edge

18.3

3.3

--
--

18.3

3.3

--
--

x ck

i ck

106

Flag Output Valid
After TXC Rising
Edge

--
--

32.5
20.8

--
--

20.8

x ck

i ck

Notes:

For internal clock, External Clock Cycle is defined by I

cyc

and SSI control register.

Periodically sampled and not 100% tested

Table 2-11

SSI Timing (Continued)

Num

Characteristics

40 MHZ or 66 MHz

80 MHz

Case Unit

Min Max

2-22

DSP56002/D, Rev. 3

MOTOROLA

Specifications

Synchronous Serial Interface (SSI) Timing

Figure 2-19 SSI Transmitter Timing

Last Bit

See Note

TXC

(Input/

Output)

FST (Bit)

Out

FST (Word)

Out

Data Out

FST (Bit) In

FST (Word)

Flags Out

Note:

In the Network mode, output flag transitions can occur at the start of each time slot within the
frame. In the Normal mode, the output flag state is asserted for the entire frame period.

First Bit

101

100

105

102

103

105

106

101A

104

AA0390

2-24

DSP56002/D, Rev. 3

MOTOROLA

Specifications

External Bus Asynchronous Timing

EXTERNAL BUS ASYNCHRONOUS TIMING

= 50 pF + 2 TTL loads

WS = Number of Wait States (0 to 15), as determined by BCR register

Capacitance Derating:

The DSP56002 External Bus Timing Specifications are designed and

tested at the maximum capacitive load of 50 pF, including stray capacitance. Typically, the drive
capability of the External Bus pins (A0A15, D0D23, PS, DS, RD, WR, X/Y, EXTP) derates
linearly at 1 ns per 12 pF of additional capacitance from 50 pF to 250 pF of loading. Port B and C
pins (HI, SCI, SSI, and Timer) derate linearly at 1 ns per 5 pF of additional capacitance from 50
pF to 250 pF of loading. Active low lines should be "pulled up" in a manner consistent with the
AC and DC specifications.

Table 2-12

External Bus Asynchronous Timing

No.

Characteristics

40 MHz

66 MHz

80 MHz

Unit

Min

Max

Min

Max

Min

Max

115 Delay from BR

Assertion to BG
Assertion

With no
external access
from the DSP

During external
read or write
access

During external
read-modify-
write access

During Stop
mode--
external bus
will not be
released and
BG will not go
low

During Wait
mode

+ T

+ 14

+ T

WS) + 14

+ T

(2T

WS) +14

+ T

+ 15

+ T

+ 14

+ T

WS) + 14

+ T

(2T

WS) +14

+ T

+ 15

+ T

+ 14

+ T

WS) + 14

+ T

(2T

WS) +14

+ T

+ 15

116 Delay from BR

Deassertion to BG
Deassertion

+ 12.5

Specifications

External Bus Asynchronous Timing

MOTOROLA

DSP56002/D, Rev. 3

2-25

117 BG Deassertion

Duration

During Wait
mode

All other cases

5.5

118 Delay from Address,

Data, and Control Bus
High Impedance to BG
Assertion

119 Delay from BG

Deassertion to Address
and Control Bus
Enabled

120 Address Valid to

WR Assertion

WS = 0

WS > 0

--
--

4.5

--
--

4.5

--
--

ns
ns

121 WR Assertion Width

WS = 0

WS > 0

+ T

--
--

+ T

--
--

+ T

--
--

ns
ns

122 WR Deassertion to

Address Not Valid

123 WR Assertion to Data

Out Active From High
Impedance

WS = 0

WS > 0

--
--

ns
ns

124 Data Out Hold Time

from WR Deassertion
(the maximum
specification is
periodically sampled,
and not 100% tested)

2.5

1.5

125 Data Out Setup Time

to WR Deassertion

WS = 0

WS > 0

0.8

+ T

0.8

--
--

0.4

+ T

0.4

--
--

0.5

+ T

0.5

--
--

ns
ns

Table 2-12

External Bus Asynchronous Timing (Continued)

No.

Characteristics

40 MHz

66 MHz

80 MHz

Unit

Min

Max

Min

Max

Min

Max

2-26

DSP56002/D, Rev. 3

MOTOROLA

Specifications

External Bus Asynchronous Timing

126 RD Deassertion to

Address Not Valid

127 Address Valid to RD

Deassertion

WS = 0

WS > 0

((WS +

) +

((WS +

) +

((WS +

) +

128 Input Data Hold Time

to RD Deassertion

129 RD Assertion Width

WS = 0

WS > 0

((WS +

) 4

--
--

((WS +

) 4

--
--

((WS +

) 4

--
--

ns
ns

130 Address Valid to Input

Data Valid

WS = 0

WS > 0

--
--

+ T

9.5

((WS+1)

) +

9.5

--
--

+ T

((WS+1)

) +

--
--

+ T

((WS+1)

)

+ T

ns
ns

131 Address Valid to

RD Assertion

4.5

132 RD Assertion to Input

Data Valid

WS = 0

WS > 0

--
--

7.5

((WS+1)

)

7.5

--
--

5.5

((WS+1)

)

5.5

--
--

5.5

((WS+1)

)

5.5

ns
ns

133 WR Deassertion to

RD Assertion

134 RD Deassertion to

RD Assertion

2.5

135 WR Deassertion to

WR Assertion

WS = 0

WS > 0

--
--

ns
ns

Table 2-12

External Bus Asynchronous Timing (Continued)

No.

Characteristics

40 MHz

66 MHz

80 MHz

Unit

Min

Max

Min

Max

Min

Max

Specifications

External Bus Asynchronous Timing

MOTOROLA

DSP56002/D, Rev. 3

2-27

136 RD Deassertion to

WR Assertion

WS = 0

WS > 0

--
--

2.5

--
--

2.5

--
--

ns
ns

Figure 2-21 Bus Request / Bus Grant Timing

Table 2-12

External Bus Asynchronous Timing (Continued)

No.

Characteristics

40 MHz

66 MHz

80 MHz

Unit

Min

Max

Min

Max

Min

Max

A0A15, PS

DS, X/Y,

RD, WR

D0D23

115

116

117

118

119

AA0392

Specifications

External Bus Synchronous Timing

MOTOROLA

DSP56002/D, Rev. 3

2-29

EXTERNAL BUS SYNCHRONOUS TIMING

= 50 pF + 2 TTL loads

Capacitance Derating

: The DSP56002 external bus timing specifications are designed and tested

at the maximum capacitive load of 50 pF, including stray capacitance. Typically, the drive
capability of the external bus pins (A0A15, D0D23, PS, DS, RD, WR, X/Y) derates linearly at 1
ns per 12 pF of additional capacitance from 50 pF to 250 pF of loading. Port B and C pins (HI,
SCI, SSI, and Timer) derate linearly at 1 ns per 5 pF of additional capacitance from 50 pF to 250
pF of loading. Active-low lines should be "pulled up" in a manner consistent with the ac and dc
specifications.

Table 2-13

External Bus Synchronous Timing

Num

Characteristics

40 MHz

66 MHz

80 MHz

Unit

Min

Max

Min

Max

Min

Max

140

First CKOUT transition to Address Valid

6.2

141

Second CKOUT transition to WR
Assertion

WS = 0

WS > 0

4.4

+ 4.4

+ 4

--
--

+ 4

ns
ns

142

Second CKOUT transition to WR
Deassertion

1.3

9.1

143

Second CKOUT transition to RD
Assertion

3.9

144

Second CKOUT transition to RD
Deassertion

3.4

145

First CKOUT transition to Data-Out Valid

5.4

4.5

146

First CKOUT transition to Data-Out
Invalid

147

Data-In Valid to second CKOUT transition
(Setup)

3.4

148

Second CKOUT transition to Data-In
Invalid (Hold)

149

First CKOUT transition to Address
Invalid

Notes:

AC timing specifications which are referenced to a device input signal are measured in production
with respect to the 50% point of the respective input signal's transition.

WS are wait state values specified in the BCR.

First CKOUT transition to data-out invalid (specification # T146) and first CKOUT transition to
address invalid (specification # T149) indicate the time after which data/address are no longer
guaranteed to be valid.

Timings are given from CKOUT midpoint to V

or V

of the corresponding pin(s).

First CKOUT transition is a falling edge of CKOUT for CKP = 0.

Specifications

External Bus Synchronous Timing

MOTOROLA

DSP56002/D, Rev. 3

2-31

Table 2-14

Bus Strobe/Wait Timing

No.

Characteristics

40 MHz

66 MHz

80 MHz

Unit

Min Max

150 First CKOUT transition

to BS Assertion

5.6

151 WT Assertion to first

CKOUT transition
(setup time)

5.3

152 First CKOUT transition

to WT Deassertion for
Minimum Timing

7.9

153 WT Deassertion to first

CKOUT transition for
Maximum Timing
(2 wait states)

7.9

154 Second CKOUT

transition to BS
Deassertion

5.2

155 BS Assertion to Address

Valid

2.4

156 BS Assertion to WT

Assertion

10.9

8.8

157 BS Assertion to WT

Deassertion

1,3

(WS1)

13.5

(WS1)

13.5

(WS1)

10.9

158 WT Deassertion to BS

Deassertion

+ T

3.3

7.8

+ T

3.3

7.8

+ T

3.3

7.8

159 Minimum BS

Deassertion Width for
Consecutive External
Accesses

160 BS Deassertion to

Address Invalid

4.6

161 Data-In Valid to RD

Deassertion (Set Up)

3.4

162 BR

Assertion to second

CKOUT transition for
Minimum Timing

9.5

2-32

DSP56002/D, Rev. 3

MOTOROLA

Specifications

External Bus Synchronous Timing

163 BR

Deassertion to

second CKOUT
transition for
Minimum Timing

164 First CKOUT transition

to BG Assertion

8.8

165 First CKOUT transition

to BG Deassertion

5.3

170 EXTAL to CKOUT with

PLL Disabled
EXTAL to CKOUT

with

PLL Enabled and
MF < 5

0.3

9.7

3.7

0.3

9.7

3.7

0.3

9.7

3.7

171 Second CKOUT

transition to BN
Assertion

5.7

172 Second CKOUT

transition to BN
Deassertion

Notes:

If wait states are also inserted using the BCR and if the number of wait states is greater than 2, then
specification numbers T156 and T157 can be increased accordingly.

BS deassertion to address invalid indicates the time after which the address are no longer guaranteed to
be valid.

The minimum number of wait states when using BS/WT is two (2).

For read-modify-write instructions, the address lines will not change states between the read and the
write cycle. However, BS will deassert before asserting again for the write cycle. If wait states are
desired for each of the read and write cycle, the WT pin must be asserted once for each cycle.

When EXTAL frequency is less than 33 MHz, then timing T170 is not guaranteed for a period of 1000

after PLOCK assertion following the events below:

· when enabling the PLL operation by software,
· when changing the Multiplication Factor,
· when recovering from the Stop state if the PLL was turned off and it is supposed to turn, on
· when exiting the Stop state.

Table 2-14

Bus Strobe/Wait Timing (Continued)

No.

Characteristics

40 MHz

66 MHz

80 MHz

Unit

Min Max

2-36

DSP56002/D, Rev. 3

MOTOROLA

Specifications

OnCE Port Timing

OnCE PORT TIMING

= 50 pF + 2 TTL loads

Table 2-15

OnCE Port Timing

Num

Characteristics

Min Max

Unit

230

DSCK Low

231

DSCK High

232

DSCK Cycle Time

200

233

DR Asserted to DSO (ACK) Asserted

234

DSCK High to DSO Valid

235

DSCK High to DSO Invalid

236

DSI Valid to DSCK Low (Setup)

237

DSCK Low to DSI Invalid (Hold)

238

Last DSCK Low to OS0OS1, ACK Active

+ T

239

DSO (ACK) Asserted to First DSCK High

240

DSO (ACK) Assertion Width

+ T

+ 7

241

DSO (ACK) Asserted to OS0OS1 High Impedance

242

OS0OS1 Valid to second CKOUT transition

243

Second CKOUT transition to OS0OS1 Invalid

244

Last DSCK Low of Read Register to First DSCK
High of Next Command

+ 10

245

Last DSCK Low to DSO Invalid (Hold)

246

DR Assertion to second CKOUT transition for Wake
Up from Wait state

247

Second CKOUT transition to DSO after Wake Up
from Wait state

17T

248

DR Assertion Width

To recover from Wait state

To recover from Wait state and enter Debug
mode

13T

+ 15

12T

249

DR Assertion to DSO (ACK) Valid (enter Debug
mode) After Asynchronous Recovery from Wait State

17T

250A

DR Assertion Width to Recover from Stop state

Stable External Clock, OMR Bit 6 = 0

Stable External Clock, OMR Bit 6 = 1

Stable External Clock, PCTL Bit 17= 1

15
15
15

65548T

+ T

20T

+ T

13T

+ T

ns
ns
ns

Specifications

OnCE Port Timing

MOTOROLA

DSP56002/D, Rev. 3

2-37

250B

DR Assertion Width to Recover from Stop state and
enter Debug mode

Stable External Clock,OMR Bit 6 = 0

Stable External Clock,OMR Bit 6 = 1

Stable External Clock,PCTL Bit 17= 1

65549T

+ T

21T

+ T

14T

+ T

--
--
--

ns
ns
ns

251

DR Assertion to DSO (ACK) Valid (enter Debug
mode) after recovery from Stop state

Stable External Clock, OMR Bit 6 = 0

Stable External Clock, OMR Bit 6 = 1

Stable External Clock, PCTL Bit 17= 1

65553T

+ T

25T

+ T

18T

+ T

--
--
--

ns
ns
ns

Notes:

A clock stabilization delay is required when using the on-chip crystal oscillator in two cases:

· after power-on Reset, and
· when recovering from Stop mode.

During this stabilization period, T

, T

, and T

will not be constant. Since this stabilization period

varies, a delay of 75,000

is typically allowed to assure that the oscillator is stable before executing

programs. While it is possible to set OMR bit 6 = 1 when using the internal crystal oscillator, it is not
recommended and these specifications do not guarantee timings for that case.

The maximum specified is periodically sampled and not 100% tested.

Figure 2-27 OnCE Serial Clock Timing

Figure 2-28 OnCE Acknowledge Timing

Table 2-15

OnCE Port Timing

Num

Characteristics

Min Max

Unit

DSCK

(Input)

230

231

232

AA0399

(Input)

DSO

(Output)

(ACK)

233

AA0400

2-38

DSP56002/D, Rev. 3

MOTOROLA

Specifications

OnCE Port Timing

Figure 2-29 OnCE Data I/O To Status Timing

Figure 2-30 OnCE Read Timing

Figure 2-31 OnCE Data I/O To Status Timing

Note:

High Impedance, external pull-down resistor

DSCK

(Input)

DSO

(Output)

(ACK)

(OS1)

DSI

(Input)

(OS0)

(See Note)

(Last)

236

237

238

AA0501

Note:

High Impedance, external pull-down resistor

DSCK

(Input)

DSO

(Output)

(See Note)

(Last)

234

235

245

AA0502

Note:

High Impedance, external pull-down resistor

(DSCK Input)

(DSO Output)

(DSI Input)

OS1

(Output)

DSO

(Output)

OS0

(Output)

(See Note)

239

241

240

241

236

237

AA0503

Specifications

OnCE Port Timing

MOTOROLA

DSP56002/D, Rev. 3

2-39

Figure 2-32 OnCE CKOUT To Status Timing

Figure 2-33 OnCE Read Register to Next Command Timing

Figure 2-34 Synchronous Recovery from Wait State

Figure 2-35 Asynchronous Recovery from Wait State

Note:

High Impedance, external pull-down resistor

CKOUT

OS0OS1

(Output)

(See Note)

242

243

AA0504

DSCK

(Input)

(Next Command)

244

AA0505

T0, T2

T1, T3

CKOUT

(Input)

DSO

(Output)

248

246

247

AA0506

(Input)

DSO

(Output)

248

249

AA0507

Specifications

Timer Timing

MOTOROLA

DSP56002/D, Rev. 3

2-41

TIMER TIMING

= 50 pF + 2 TTL loads

Table 2-16

Timer Timing

Num

Characteristics

Min Max

Unit

260

TIO Low

+ 7

261

TIO High

+ 7

262

Synchronous Timer Setup Time from TIO (input)
Assertion to CKOUT Rising Edge

263

Synchronous Timer Delay Time from CKOUT Rising Edge
to the External Memory Access Address Out Valid Caused
by First Interrupt Instruction Execution

+ T

264

CKOUT Rising Edge to TIO (output) Assertion

265

CKOUT Rising Edge to TIO (output) Deassertion

266

CKOUT Rising Edge to TIO (General Purpose Output)

Figure 2-37 TIO Timer Event Input

Figure 2-38 Timer Interrupt Generation

TIO

261

260

AA0509

CKOUT

TIO (Input)

First Interrupt Instruction Execution

ADDRESS

262

263

AA0510

MOTOROLA

DSP56002/D, Rev. 3

3-1

SECTION

PACKAGING

PIN-OUT AND PACKAGE INFORMATION

This sections provides information about the available packages for this product,
including diagrams of the package pinouts and tables describing how the signals
described in

Section 1

are allocated for each package.

The DSP56002 is available in three package types:

132-pin Plastic Quad Flat Pack (PQFP)

144-pin Thin Quad Flat Pack (TQFP)

132-pin Ceramic Pin Grid Array (PGA)

3-2

DSP56002/D, Rev. 3

MOTOROLA

Packaging

Pin-out and Package Information

PQFP Package Description

Top and bottom views of the PQFP package are shown in

Figure 3-1

and

Figure 3-2

with their pin-outs.

Figure 3-1

Top View of the 132-pin Plastic Quad Flat Pack (PQFP) Package

Note:

"NC" are No Connection pins that are reserved for possible future enhancements. Do not
connect these pins to any power, ground, signal traces, or vias.

An OVERBAR indicates the signal is asserted when the voltage = ground (active low).

To simplify locating the pins, each fifth pin is shaded in the illustration.

Orientation Mark

(Chamfered Edge)

117

(Top View)

H4/PB4
H3/PB3

CCH

H2/PB2

GND

H1/PB1
H0/PB0

RXD/PC0

TXD/PC1

GND

SCLK/PC2

SC0/PC3

CCS

SCK/PC6

SC2/PC5

STD/PC8

GND

SC1/PC4

GND

CCQ

SRD/PC7

TIO

CCC

GND

DSCK/OS1

GND

D21
D20
V

CCD

D19
D18
GND

D17
D16
D15
D14
GND

D13
D12
V

CCD

D11
D10
GND

GND

CCQ

D9
D8
D7
D6
GND

D5
D4
V

CCD

D3
D2
GND

D1
D0

H5/PB5

GND

H6/PB6

H7/PB7

HREQ

/PB13

HR/W

/PB11

GND

HEN

/PB12

CCH

/PB14

HA0/PB8

HA1/PB9

GND

HA2/PB10

GND

CCQ

EXT

PINIT

PLOCK

GND

PCAP

CCP

CKP

RESET

CCCK

OUT

GND

MOD

A/IRQA

MODB/IRQB

MODC/NMI

D23

D22

DSO

DSI/OS0

X/Y

GND

CCA

GND

CCQ

GND

CCA

GND

A10

A11

A12

CCA

A13

GND

A14

A15

AA0611

Packaging

Pin-out and Package Information

MOTOROLA

DSP56002/D, Rev. 3

3-3

Figure 3-2

Bottom View of the 132-pin Plastic Quad Flat Pack (PQFP) Package

Note:

"NC" are No Connection pins that are reserved for possible future enhancements. Do not
connect these pins to any power, ground, signal traces, or vias.

An OVERBAR indicates the signal is asserted when the voltage = ground (active low).

To simplify locating the pins, each fifth pin is shaded in the illustration.

Orientation Mark

(Chamfered Edge

117

(Bottom View)

H4/PB4
H3/PB3
V

CCH

H2/PB2
GND

H1/PB1
H0/PB0
RXD/PC0
TXD/PC1
GNDS
SCLK/PC2
SC0/PC3
V

CCS

SCK/PC6
SC2/PC5
STD/PC8
GNDS
SC1/PC4
GND

CCQ

SRD/PC7
TIO
NC
BN
WT
BG
BR
V

CCC

WR
RD
GND

NC
DSCK/OS1

GND

D21
D20

CCD

D19
D18

GND

D17
D16
D15
D14

GND

D13
D12

CCD

D11
D10

GND

CCQ

D9
D8
D7
D6

GND

D5
D4

CCD

D3
D2

GND

D1
D0

H5/PB5

GND

H6/PB6

H7/PB7

HREQ

/PB13

HR/W

/PB11

GND

HEN

/PB12

CCH

/PB14

HA0/PB8

HA1/PB9

GND

HA2/PB10

GND

CCQ

EXT

PINIT

PLOCK

GND

PCAP

CCP

CKP

RESET

CCCK

OUT

GND

MOD

A/IRQA

MODB/IRQB

MODC/NMI

D23

D22

DSO

DSI/OS0

X/Y

GND

CCA

GND

CCQ

GND

CCA

GND

A10

A11

A12

CCA

A13

GND

A14

A15

AA0612

on Top Side)

3-4

DSP56002/D, Rev. 3

MOTOROLA

Packaging

Pin-out and Package Information

The DSP56002 signals that may be programmed as General Purpose I/O are listed
with their primary function in

Table 3-9

Table 3-1

DSP56002 General Purpose I/O Pin Identification in PQFP Package

Pin Number

Primary Function

Port

GPIO ID

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

HA0

PB8

HA1

PB9

HA2

PB10

HR/W

PB11

HEN

PB12

HREQ

PB13

HACK

PB14

RXD

PC0

TXD

PC1

SCLK

PC2

SC0

PC3

SC1

PC4

SC2

PC5

SCK

PC6

SRD

PC7

STD

PC8

TIO

No port assigned

Packaging

Pin-out and Package Information

MOTOROLA

DSP56002/D, Rev. 3

3-5

Table 3-2

DSP56002 Signal Identification by PQFP Pin Number

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

EXTAL

TXD/PC1

CCQ

GND

DSO

GND

SCLK/PC2

DSI/OS0

HA2/PB10

SC0/PC3

GND

CCS

X/Y

HA1/PB9

SCK/PC6

GND

HA0/PB8

SC2/PC5

HACK/PB14

STD/PC8

CCA

CCH

GND

HEN/PB12

SC1/PC4

GND

HR/W/PB11

CCQ

GND

HREQ/PB13

SRD/PC7

H7/PB7

TIO*

H6/PB6

GND

CCQ

H5/PB5

GND

H4/PB4

H3/PB3

CCA

CCH

CCC

GND

H2/PB2

GND

H1/PB1

GND

H0/PB0

RXD/PC0

DSCK/OS1

GND

3-6

DSP56002/D, Rev. 3

MOTOROLA

Packaging

Pin-out and Package Information

A10

114

D20

A11

115

D21

A12

CCQ

116

GND

CCA

GND

117

D22

A13

GND

118

D23

GND

100

D10

119

MODC/NMI

A14

101

D11

120

MODB/IRQB

A15

102

CCD

121

MODA/IRQA

103

D12

122

GND

104

D13

123

CKOUT

GND

105

GND

124

CCCK

106

D14

125

RESET

107

D15

126

CKP

CCD

108

D16

127

CCP

109

D17

128

PCAP

110

GND

129

GND

111

D18

130

PLOCK

112

D19

131

PINIT

113

CCD

132

XTAL

Note:

"NC" are No Connection pins that are reserved for possible future enhancements.
Do not connect these pins to any power, ground, signal traces, or vias.

An OVERBAR indicates the signal is asserted when the voltage = ground (active
low).

Table 3-2

DSP56002 Signal Identification by PQFP Pin Number (Continued)

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

Packaging

Pin-out and Package Information

MOTOROLA

DSP56002/D, Rev. 3

3-7

Table 3-3

DSP56002 PQFP Pin Identification by Signal Name

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

114

DSO

116

EXTAL

117

GND

119

GND

D10

100

GND

D11

101

GND

122

D12

103

GND

A10

D13

104

GND

A11

D14

106

GND

A12

D15

107

GND

105

A13

D16

108

GND

110

A14

D17

109

GND

116

A15

D18

111

GND

D19

112

GND

D20

114

GND

D21

115

GND

D22

117

GND

129

CKOUT

123

D23

118

GND

CKP

126

GND

DSCK

GND

DSI

GND

3-8

DSP56002/D, Rev. 3

MOTOROLA

Packaging

Pin-out and Package Information

GND

PB1

PLOCK

130

PB2

PB3

PB4

RESET

125

PB5

RXD

PB6

SC0

PB7

SC1

PB8

SC2

PB9

SCK

HA0

PB10

SCLK

HA1

PB11

SRD

HA2

PB12

STD

HACK

PB13

TIO

HEN

PB14

TXD

HR/W

PC0

CCA

HREQ

PC1

CCA

IRQA

121

PC2

CCA

IRQB

120

PC3

CCC

MODA

121

PC4

CCCK

124

MODB

120

PC5

CCD

MODC

119

PC6

CCD

102

NMI

119

PC7

CCD

113

OS0

PC8

CCH

OS1

PCAP

128

CCH

PB0

PINIT

131

CCP

127

CCQ

CCS

XTAL

132

CCQ

X/Y

Table 3-3

DSP56002 PQFP Pin Identification by Signal Name (Continued)

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

Packaging

Pin-out and Package Information

MOTOROLA

DSP56002/D, Rev. 3

3-9

Power and ground pins have special considerations for noise immunity.
See

Section 4 Design Considerations

Table 3-4

DSP56002 Power Supply Pins in PQFP Package

Pin Number

Power Supply

Circuit Supplied

CCA

Address

Bus

Buffers

GND

CCC

Bus Control

Buffers

GND

124

CCCK

Clock

122

GND

CCD

Data

Bus

Buffers

102

113

GND

105

110

116

CCH

Host

Interface

Buffers

GND

Packaging

Pin-out and Package Information

MOTOROLA

DSP56002/D, Rev. 3

3-11

Figure 3-3 132-Pin Plastic Quad Flat Pack (PQFP) Mechanical Information

L-M

0.016

117

116

VIEW AB

PIN 1
IDENT

0.002 L-M

0.002 N

0.004 T

4X 33 TIPS

SEATING
PLANE

132X

GAGE
PLANE

AC AC

128X

X=L, M, OR N

VIEW AB

(D)

BASE

PLATING

SECTION AC-AC

132X

L-M

0.008

R R1

L-M

0.010

L-M

0.012

132X

L-M

0.008

SECTION AA-AA

DIM

MIN

MAX

INCHES

1.100 BSC

0.550 BSC

1.100 BSC

0.550 BSC

0.160

0.180

0.020

0.040

0.135

0.145

0.008

0.012

0.016

0.008

0.011

0.006

0.008

0.005

0.007

0.014

0.025 BSC

0.950 BSC

0.475 BSC

0.034

0.044

0.010 BSC

0.950 BSC

0.475 BSC

1.080 BSC

0.540 BSC

0.025 REF

1.080 BSC

0.540 BSC

0.006

0.008

0.013 REF

METAL

NOTES:

1. DIMENSIONING AND TOLERANCING

PER ASME Y14.5M, 1982.

2. DIMENSIONS IN INCHES.
3. DIMENSIONS A, B, J, AND P DO NOT

INCLUDE MOLD PROTRUSION.
ALLOWABLE MOLD PROTRUSION
FOR DIMENSIONS A AND B IS 0.007,
FOR DIMENSIONS J AND P IS 0.010.

4. DATUM PLANE H IS LOCATED AT THE

UNDERSIDE OF LEADS WHERE
LEADS EXIT PACKAGE BODY.

5. DATUMS L, M, AND N TO BE

DETERMINED WHERE CENTER
LEADS EXIT PACKAGE BODY AT
DATUM H.

6. DIMENSIONS S AND V TO BE

DETERMINED AT SEATING PLANE,
DATUM T.

7. DIMENSIONS A, B, J, AND P TO BE

DETERMINED AT DATUM PLANE H.

8. DIMENSION F DOES NOT INCLUDE

DAMBAR PROTRUSIONS. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
LEAD WIDTH TO EXCEED 0.019.

CASE 831A-02

ISSUE C

3-12

DSP56002/D, Rev. 3

MOTOROLA

Packaging

Pin-out and Package Information

TQFP Package Description

Top and bottom views of the TQFP package are shown in

Figure 3-4

and

Figure 3-5

with their pin-outs.

Figure 3-4 Top View of the 144-pin Thin Quad Flat Pack (TQFP) Package

Note:

"NC" are No Connection pins that are reserved for possible future enhancements. Do not
connect these pins to any power, ground, signal traces, or vias.

An OVERBAR indicates the signal is asserted when the voltage = ground (active low).

To simplify locating the pins, each fifth pin is shaded in the illustration.

Orientation Mark

109

D0
D1

GND

D2
D3

CCD

D4
D5

GND

D6
D7
D8
D9

CCQ

GND

D10

D11

CCD

D12
D13

GND

D14
D15
D16
D17

GND

D18
D19

CCD

D20
D21

GND

NC
DSCK/OS1
NC
GND

RD
WR
V

CCC

BR
BG
WT
BN
NC
TIO
SRD/PC7
V

CCQ

GND

SC1/PC4
NC
GND

STD/PC8
SC2/PC5
SCK/PC6
V

CCS

SC0/PC3
SCLK/PC2
GND

TXD/PC1
RXD/PC0
H0/PB0
H1/PB1
GND

H2/PB2
V

CCH

H3/PB3
H4/PB4
NC

D22

D23

MODC/NMI

MODB/IRQB

MOD

A/IRQA

GND

OUT

CCCK

RESET

CKP

CCP

PCAP

GND

PLOCK

PINIT

EXT

CCQ

GND

HA2/PB10

GND

HA1/PB9

HA0/PB8

/PB14

CCH

HEN

/PB12

GND

HR/W

/PB11

HREQ

/PB13

H7/PB7

H6/PB6

GND

H5/PB5

A15

A14

GND

A13

CCA

A12

A11

A10

GND

CCA

GND

CCQ

GND

CCA

GND

X/Y

DSI/OS0

DSO

AA0613

(Top View)

Packaging

Pin-out and Package Information

MOTOROLA

DSP56002/D, Rev. 3

3-13

Figure 3-5 Bottom View of the144-pin Thin Quad Flat Pack (TQFP) Package

Note:

"NC" are No Connection pins that are reserved for possible future enhancements. Do not
connect these pins to any power, ground, signal traces, or vias.

An OVERBAR indicates the signal is asserted when the voltage = ground (active low).

To simplify locating the pins, each fifth pin is shaded in the illustration.

Orientation Mark

109

NC
D0
D1
GND

D2
D3
V

CCD

D4
D5
GND

D6
D7
D8
D9
V

CCQ

GND

D10
NC
D11
V

CCD

D12
D13
GND

D14
D15
D16
D17
GND

D18
D19
V

CCD

D20
D21
GND

DSCK/OS1

GNDC

CCC

TIO

SRD/PC7

CCQ

GND

SC1/PC4

GNDS

STD/PC8

SC2/PC5

SCK/PC6

CCS

SC0/PC3

SCLK/PC2

GNDS

TXD/PC1

RXD/PC0

H0/PB0
H1/PB1

GND

H2/PB2

CCH

H3/PB3
H4/PB4

D22

D23

MODC/NMI

MODB/IRQB

MOD

A/IRQA

GND

OUT

CCCK

RESET

CKP

CCP

PCAP

GND

PLOCK

PINIT

EXT

CCQ

GND

HA2/PB10

GND

HA1/PB9

HA0/PB8

/PB14

CCH

HEN

/PB12

GND

HR/W

/PB11

HREQ

/PB13

H7/PB7

H6/PB6

GND

H5/PB5

A15

A14

GND

A13

CCA

A12

A11

A10

GND

CCA

GND

CCQ

GND

CCA

GND

X/Y

DSI/OS0

DSO

AA0614

(Bottom View)

(on Top Side)

3-14

DSP56002/D, Rev. 3

MOTOROLA

Packaging

Pin-out and Package Information

The DSP56002 signals that may be programmed as General Purpose I/O are listed
with their primary function in

Table 3-9

Table 3-5

DSP56002 General Purpose I/O Pin Identification in TQFP Package

Pin Number

Primary Function

Port

GPIO ID

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

HA0

PB8

HA1

PB9

HA2

PB10

HR/W

PB11

HEN

PB12

HREQ

PB13

HACK

PB14

RXD

PC0

TXD

PC1

SCLK

PC2

SC0

PC3

SC1

PC4

SC2

PC5

SCK

PC6

SRD

PC7

STD

PC8

TIO

No port assigned

Packaging

Pin-out and Package Information

MOTOROLA

DSP56002/D, Rev. 3

3-15

Table 3-6

DSP56002 Signal Identification by TQFP Pin Number

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

HACK/PB14

SCK/PC6

D22

CCH

SC2/PC5

D23

HEN/PB12

STD/PC8

MODC/NMI

GND

MODB/IRQB

HR/W/PB11

MODA/IRQA

HREQ/PB13

SC1/PC4

GND

H7/PB7

GND

CKOUT

H6/PB6

CCQ

CCCK

GND

SRD/PC7

RESET

H5/PB5

TIO

CKP

CCP

PCAP

H4/PB4

GND

H3/PB3

PLOCK

CCH

PINIT

H2/PB2

CCC

XTAL

GND

H1/PB1

EXTAL

H0/PB0

GND

CCQ

RXD/PC0

GND

TXD/PC1

DSCK/OS1

HA2/PB10

GND

SCLK/PC2

HA1/PB9

SC0/PC3

HA0/PB8

CCS

DSO

3-16

DSP56002/D, Rev. 3

MOTOROLA

Packaging

Pin-out and Package Information

DSI/OS0

GND

122

100

A10

123

CCQ

X/Y

101

A11

124

GND

102

A12

125

GND

103

CCA

126

D10

CCA

104

A13

127

105

GND

128

D11

106

A14

129

CCD

107

A15

130

D12

GND

108

131

D13

109

132

GND

110

133

D14

111

134

D15

CCQ

112

GND

135

D16

GND

113

136

D17

114

137

GND

115

CCD

138

D18

CCA

116

139

D19

GND

117

140

CCD

118

GND

141

D20

119

142

D21

120

143

GND

121

144

Note:

"NC" are No Connection pins that are reserved for possible future enhancements.
Do not connect these pins to any power, ground, signal traces, or vias.

An OVERBAR indicates the signal is asserted when the voltage = ground (active
low).

Table 3-6

DSP56002 Signal Identification by TQFP Pin Number (Continued)

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

Packaging

Pin-out and Package Information

MOTOROLA

DSP56002/D, Rev. 3

3-17

Table 3-7

DSP56002 TQFP Pin Identification by Signal Name

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

114

DSO

116

EXTAL

117

GND

119

GND

120

GND

121

GND

122

GND

105

D10

126

GND

D11

128

GND

D12

130

GND

112

A10

100

D13

131

GND

118

A11

101

D14

133

GND

125

A12

102

D15

134

GND

132

A13

104

D16

135

GND

137

A14

106

D17

136

GND

143

A15

107

D18

138

GND

D19

139

GND

D20

141

GND

D21

142

GND

D22

GND

CKOUT

D23

GND

CKP

GND

110

GND

111

DSCK

GND

124

113

DSI

GND

3-18

DSP56002/D, Rev. 3

MOTOROLA

Packaging

Pin-out and Package Information

GND

PB1

PLOCK

PB2

PB3

PB4

RESET

PB5

RXD

PB6

SC0

PB7

SC1

PB8

SC2

PB9

SCK

HA0

PB10

SCLK

HA1

PB11

SRD

HA2

PB12

STD

HACK

PB13

TIO

HEN

PB14

TXD

HR/W

PC0

CCA

HREQ

PC1

CCA

IRQA

PC2

CCA

103

IRQB

PC3

CCC

MODA

PC4

CCCK

MODB

PC5

CCD

115

MODC

PC6

CCD

129

NMI

PC7

CCD

140

OS0

PC8

CCH

OS1

PCAP

CCH

PB0

PINIT

CCP

Table 3-7

DSP56002 TQFP Pin Identification by Signal Name (Continued)

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

3-20

DSP56002/D, Rev. 3

MOTOROLA

Packaging

Pin-out and Package Information

Power and ground pins have special considerations for noise immunity. See the
section

Design Considerations

Table 3-8

DSP56002 Power Supply Pins in TQFP Package

Pin Number

Power Supply

Circuit Supplied

CCA

Address

Bus

Buffers

103

GND

105

CCC

Bus Control

Buffers

GND

CCCK

Clock

GND

115

CCD

Data

Bus

Buffers

129

140

112

GND

118

125

132

137

143

CCH

Host

Interface

Buffers

GND

3-22

DSP56002/D, Rev. 3

MOTOROLA

Packaging

Pin-out and Package Information

Figure 3-6 144-pin Thin Plastic Quad Flat Pack (TQFP) Mechanical Information

SEATING
PLANE

0.1 T

144X

VIEW AB

PLATING

BASE
METAL

SECTION J1-J1

(ROTATED 90)

144 PL

0.08

T L-M

0.20 T L-M

144

109

108

4X 36 TIPS

PIN 1
IDENT

VIEW Y

0.20 T L-M

140X

VIEW Y

X=L, M OR N

GAGE PLANE

0.05

(Z)

(Y)

(K)

0.25

VIEW AB

DIM

MIN

MAX

MILLIMETERS

20.00 BSC

10.00 BSC

20.00 BSC

10.00 BSC

1.40

1.60

0.05

0.15

1.35

1.45

0.17

0.27

0.45

0.75

0.17

0.23

0.50 BSC

0.09

0.20

0.50 REF

0.25 BSC

0.13

0.20

0.13

0.20

22.00 BSC

11.00 BSC

22.00 BSC

11.00 BSC

0.25 REF

1.00 REF

0.09

0.16

1
2

NOTES:

9. DIMENSIONS AND TOLERANCING PER ASME

Y14.5, 1994.

10.DIMENSIONS IN MILLIMETERS.
11.DATUMS L, M AND N TO BE DETERMINED AT

THE SEATING PLANE, DATUM T.

12.DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE, DATUM T.

13.DIMENSIONS A AND B DO NOT INCULDE

MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B DO INCLUDE MOLD MISMATCH AND
ARE DETERMINED AT DATUM PLANE H.

14.DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLED DAMBAR
PROTRUSION SHALL NOT CAUSE THE D
DIMENSION TO EXCEED 0.35.

CASE 918-03

ISSUE C

Packaging

Pin-out and Package Information

MOTOROLA

DSP56002/D, Rev. 3

3-23

PGA Package Description

Top and bottom views of the PGA package are shown in

Figure 3-7

and

Figure 3-8

with their pin-outs.

Figure 3-7 Top View of the 132-pin Ceramic (RC) 13

13 Pin Grid Array Package

Note:

"NC" are No Connection pins that are reserved for possible future enhancements. Do not
connect these pins to any power, ground, signal traces, or vias.

An OVERBAR indicates the signal is asserted when the voltage = ground (active low).

Orientation

Mark

GND

CCD

GND

D15

D14

D11

CCD

GND

CCD

GND

RESET

D21

D19

D17

D12

GND

CCQ

CKP

GND

D23

D22

A15

A14

A13

A12

CCA

GND

CCP

CKOUT

MODC/

NMI

A11

A10

GND

CCQ

PCAP

GND

PLOCK

PINIT

CCA

CCQ

XTAL

EXTAL

GND

HA2

HA1

HA0

HR/W

CCA

HACK

HEN

HREQ

X/Y

GND

SC0

STD

TIO

DSO

DSI/OS0

GND

RXD

TXD

SCLK

SCK

SC1

DSCK/

OS1

GND

CCH

GND

CCH

GND

SC2

SRD

GNDS

CCS

GNDS

CCC

GNDC

CCQ

CCCK

MODB/

IRQB

D20

D18

D16

D13

D10

MODA/

IRQA

AA0615

Top View

3-24

DSP56002/D, Rev. 3

MOTOROLA

Packaging

Pin-out and Package Information

Figure 3-8 Bottom View of the 132-pin Ceramic (RC) 13

13 Pin Grid Array Package

Note:

"NC" are No Connection pins that are reserved for possible future enhancements. Do not
connect these pins to any power, ground, signal traces, or vias.

An OVERBAR indicates the signal is asserted when the voltage = ground (active low).

Orientation Mark

(on Top Side)

GND

CCD

GND

D15

D14

D11

CCD

GND

CCD

GND

RESET

D21

D19

D17

D12

GND

CCQ

CKP

GND

D23

D22

A15

A14

A13

A12

CCA

GND

CCP

CKOUT

MODC/

NMI

A11

A10

GND

CCQ

PCAP

GND

PLOCK

PINIT

CCA

CCQ

XTAL

EXTAL

GND

HA2

HA1

HA0

HR/W

CCA

HACK

HEN

HREQ

X/Y

GND

SC0

STD

TIO

DSO

DSI/OS0

GND

RXD

TXD

SCLK

SCK

SC1

DSCK/

OS1

GND

CCH

GND

CCH

GND

SC2

SRD

GNDS

CCS

GNDS

CCC

GNDC

CCQ

CCCK

MODB/

IRQB

D20

D18

D16

D13

D10

MODA/

IRQA

AA0616

Bottom View

Packaging

Pin-out and Package Information

MOTOROLA

DSP56002/D, Rev. 3

3-25

The DSP56008 signals that may be programmed as General Purpose I/O are listed
with their primary function in

Table 3-9

DSP56002 General Purpose I/O Pin Identification in PGA Package

Pin Number

Primary Function

Port

GPIO ID

E11

PB0

D11

PB1

C11

PB2

E10

PB3

D10

PB4

B12

PB5

A11

PB6

B11

PB7

HA0

PB8

HA1

PB9

HA2

PB10

HR/W

PB11

B10

HEN

PB12

C10

HREQ

PB13

A10

HACK

PB14

C12

RXD

PC0

D12

TXD

PC1

E12

SCLK

PC2

F11

SC0

PC3

G12

SC1

PC4

F13

SC2

PC5

F12

SCK

PC6

G13

SRD

PC7

G11

STD

PC8

H11

TIO

No port assigned

3-26

DSP56002/D, Rev. 3

MOTOROLA

Packaging

Pin-out and Package Information

Table 3-10

DSP56002 Signal Identification by PGA Pin Number

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

GND

B13

CCH

D18

CCQ

CCD

D19

GND

MODB/IRQB

D22

CCQ

MODA/IRQA

E10

H3/PB3

GND

E11

H0/PB0

CCQ

CKOUT

E12

SCLK/PC2

GND

E13

GND

CCQ

PINIT

D15

HA2/PB10

EXTAL

D16

A10

HACK/PB14

HA0/PB8

D17

A11

H6/PB6

C10

HREQ/PB13

F11

SC0/PC3

A12

GND

C11

H2/PB2

F12

SCK/PC6

A13

GND

C12

RXD/PC0

F13

SC2/PC5

GND

C13

GND

D14

CCCK

GND

D13

RESET

D20

D12

CKP

D21

G11

STD/PC8

CCP

D23

G12

SC1/PC4

PCAP

MODC/NMI

G13

SRD/PC7

PLOCK

HR/W/PB11

D11

XTAL

D10

H4/PB4

D10

HA1/PB9

D11

H1/PB1

B10

HEN/PB12

D12

TXD/PC1

H11

TIO*

B11

H7/PB7

D13

CCH

H12

B12

H5/PB5

GND

H13

Packaging

Pin-out and Package Information

MOTOROLA

DSP56002/D, Rev. 3

3-27

CCD

A13

M10

A15

A10

M11

DSI/OS0

J10

M12

J11

M13

CCC

J12

GND

J13

GND

L10

GND

L11

DSO

CCA

L12

GND

A14

L13

GND

A11

CCD

CCA

GND

K10

X/Y

CCA

K11

A12

N10

GND

K12

N11

K13

CCS

N12

DSCK/OS1

GND

N13

GND

Note:

NC" are No Connection pins that are reserved for possible future enhancements.
Do not connect these pins to any power, ground, signal traces, or vias.

An OVERBAR indicates the signal is asserted when the voltage = ground (active
low).

Table 3-10

DSP56002 Signal Identification by PGA Pin Number (Continued)

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

3-28

DSP56002/D, Rev. 3

MOTOROLA

Packaging

Pin-out and Package Information

Table 3-11

DSP56002 PGA Pin Identification by Signal Name

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

DSO

L11

EXTAL

GND

N10

GND

D10

GND

N13

D11

GND

D12

GND

A10

D13

GND

A11

D14

GND

A12

D15

GND

A13

D16

GND

A14

D17

GND

A15

D18

GND

A12

K12

D19

GND

A13

H13

D20

GND

C13

L12

D21

GND

E13

N11

D22

GND

CKOUT

D23

GND

CKP

K11

GND

L10

GND

DSCK

N12

GND

DSI

M11

GND

J13

Packaging

Pin-out and Package Information

MOTOROLA

DSP56002/D, Rev. 3

3-29

GND

L13

PB5

B12

SCK

F12

E11

PB6

A11

SCLK

E12

D11

PB7

B11

SRD

G13

C11

PB8

STD

G11

E10

PB9

TIO

H11

D10

PB10

TXD

D12

B12

PB11

CCA

A11

PB12

B10

CCA

B11

PB13

C10

CCA

HA0

PB14

A10

CCC

M13

HA1

PC0

C12

CCCK

HA2

PC1

D12

CCD

HACK

A10

PC2

E12

CCD

HEN

B10

PC3

F11

CCD

HR/W

PC4

G12

CCH

B13

HREQ

C10

PC5

F13

CCH

D13

IRQA

PC6

F12

CCP

IRQB

PC7

G13

CCQ

MODA

PC8

G11

CCQ

MODB

PCAP

CCQ

MODC

PINIT

CCQ

NMI

PLOCK

CCS

K13

OS0

M11

M10

J11

OS1

N12

J10

J12

PB0

E11

RESET

X/Y

K10

PB1

D11

RXD

C12

XTAL

PB2

C11

SC0

F11

H12

PB3

E10

SC1

G12

M12

PB4

D10

SC2

F13

Table 3-11

DSP56002 PGA Pin Identification by Signal Name (Continued)

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

3-30

DSP56002/D, Rev. 3

MOTOROLA

Packaging

Pin-out and Package Information

Power and ground pins have special considerations for noise immunity. See the
section

Design Considerations

Table 3-12

DSP56002 Power Supply Pins in PGA Package

Pin Number

Power Supply

Circuit Supplied

CCA

Address

Bus

Buffers

N10

GND

M13

CCC

Bus Control

Buffers

N13

GND

CCCK

Clock

GND

CCD

Data

Bus

Buffers

GND

B13

CCH

Host

Interface

Buffers

D13

A12

GND

A13

C13

E13

Packaging

Pin-out and Package Information

MOTOROLA

DSP56002/D, Rev. 3

3-31

CCQ

Internal Logic

GND

CCP

PLL

GND

K13

CCS

Serial Port

J13

GND

L13

Figure 3-9 132-pin Ceramic Pin Grid Array (PGA) Package Mechanical Information

Table 3-12

DSP56002 Power Supply Pins in PGA Package (Continued)

Pin Number

Power Supply

Circuit Supplied

NOTES:
1.

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

DIM

MIN

MAX

INCHES

1.340

1.380

1.340

1.380

0.100

0.150

0.017

0.022

0.100 BSC

0.170

0.195

-A-

-B-

132 PL

-T-

0.005

1 2 3 4 5 6 7 8 9 10 11 12 13

CASE 789B-01

ISSUE O

3-32

DSP56002/D, Rev. 3

MOTOROLA

Packaging

Ordering Drawings

ORDERING DRAWINGS

Complete mechanical information regarding DSP56002 packaging is available by
facsimile through Motorola's MfaxTM system. Call the following number to obtain
information by facsimile:

The Mfax automated system requests the following information:

The receiving facsimile telephone number including area code or country
code

The caller's Personal Identification Number (PIN)

Note:

For first time callers, the system provides instructions for setting up a PIN,
which requires entry of a name and telephone number.

The type of information requested:

Instructions for using the system

A literature order form

Specific part technical information or data sheets

Other information described by the system messages

A total of three documents may be ordered per call.

The DSP56002 132-pin PQFP package mechanical drawing is referenced as 831A-02.
The reference number for the 144-pin TQFP package is 918-03. The reference number
for the 132-pin ceramic PGA package is 789B-01.

(602) 244-6591

MOTOROLA

DSP56002/D, Rev. 3

4-1

SECTION

DESIGN CONSIDERATIONS

HEAT DISSIPATION

An estimation of the chip junction temperature, T

, in

C can be obtained from the

equation:

Equation 1:

Where:

= ambient temperature °C

= package junction-to-ambient thermal resistance °C/W

= power dissipation in package

Historically, thermal resistance has been expressed as the sum of a junction-to-case
thermal resistance and a case-to-ambient thermal resistance:

Equation 2:

Where:

= package junction-to-ambient thermal resistance °C/W

= package junction-to-case thermal resistance °C/W

= package case-to-ambient thermal resistance °C/W

is device-related and cannot be influenced by the user. The user controls the

thermal environment to change the case-to-ambient thermal resistance, R

. For

example, the user can change the air flow around the device, add a heat sink, change
the mounting arrangement on the Printed Circuit Board, or otherwise change the
thermal dissipation capability of the area surrounding the device on a Printed Circuit
Board. This model is most useful for ceramic packages with heat sinks; some 90% of
the heat flow is dissipated through the case to the heat sink and out to the ambient
environment. For ceramic packages, in situations where the heat flow is split between
a path to the case and an alternate path through the Printed Circuit Board, analysis of
the device thermal performance may need the additional modeling capability of a
system level thermal simulation tool.

The thermal performance of plastic packages is more dependent on the temperature
of the Printed Circuit Board to which the package is mounted. Again, if the

(

)

4-2

DSP56002/D, Rev. 3

MOTOROLA

Design Considerations

Heat Dissipation

estimations obtained from R

do not satisfactorily answer whether the thermal

performance is adequate, a system level model may be appropriate.

A complicating factor is the existence of three common ways for determining the
junction-to-case thermal resistance in plastic packages:

To minimize temperature variation across the surface, the thermal resistance
is measured from the junction to the outside surface of the package (case)
closest to the chip mounting area when that surface has a proper heat sink.

To define a value approximately equal to a junction-to-board thermal
resistance, the thermal resistance is measured from the junction to where the
leads are attached to the case.

If the temperature of the package case (T

) as determined by a thermocouple,

the thermal resistance is computed using the value obtained by the equation
(T

)/P

As noted above, the junction-to-case thermal resistances quoted in this data sheet are
determined using the first definition. From a practical standpoint, that value is also
suitable for determining the junction temperature from a case thermocouple reading
in forced convection environments. In natural convection, using the junction-to-case
thermal resistance to estimate junction temperature from a thermocouple reading on
the case of the package will estimate a junction temperature slightly hotter than
actual temperature. Hence, the new thermal metric, Thermal Characterization
Parameter or

, has been defined to be (T

)/P

. This value gives a better

estimate of the junction temperature in natural convection when using the surface
temperature of the package. Remember that surface temperature readings of
packages are subject to significant errors caused by inadequate attachment of the
sensor to the surface and to errors caused by heat loss to the sensor. The
recommended technique is to attach a 40-gauge thermocouple wire and bead to the
top center of the package with thermally conductive epoxy.

Note:

Table 2-2 Thermal Characteristics

on page 2-2 contains the package thermal

values for this chip.

Design Considerations

Electrical Design Considerations

MOTOROLA

DSP56002/D, Rev. 3

4-3

ELECTRICAL DESIGN CONSIDERATIONS

Use the following list of recommendations to assure correct DSP operation:

Provide a low-impedance path from the board power supply to each V

on the DSP, and from the board ground to each GND pin.

Use at least four 0.1

F bypass capacitors positioned as close as possible to the

four sides of the package to connect the V

power source to GND.

Ensure that capacitor leads and associated printed circuit traces that connect
to the chip V

and GND pins are less than 0.5 inch per capacitor lead.

Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for
V

and GND.

Because the DSP output signals have fast rise and fall times, PCB trace lengths
should be minimal. This recommendation particularly applies to the address
and data buses as well as the RD, WR, IRQA, IRQB, NMI, HEN, and HACK
pins.

Consider all device loads as well as parasitic capacitance due to PCB traces
when calculating capacitance. This is especially critical in systems with higher
capacitive loads that could create higher transient currents in the V

and

GND circuits.

All inputs must be terminated (i.e., not allowed to float) using CMOS levels.

Take special care to minimize noise levels on the PLL supply pins (both V

and GND).

CAUTION

This device contains protective circuitry to
guard against damage due to high static
voltage or electrical fields. However, normal
precautions are advised to avoid application
of any voltages higher than maximum rated
voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage
level (e.g., either GND or V

4-4

DSP56002/D, Rev. 3

MOTOROLA

Design Considerations

Power Consumption

POWER CONSUMPTION

Power dissipation is a key issue in portable DSP applications. The following describes
some factors which affect current consumption. Current consumption is described by
the formula:

Equation 3:

where:

C = node/pin capacitance
V = voltage swing
f = frequency of node/pin toggle

For example, for an address pin loaded with a 50 pF capacitance and operating at 5.5
V with a 40 MHz clock, toggling at its maximum possible rate (which is 10 MHz), the
current consumption is:

Equation 4:

The maximum internal current value (I

CCI

-max), reflects the maximum I

expected

when running the code given below. This represents "typical" internal activity, and is
included as a point of reference. Some applications may consume more or less current
depending on the code used. The typical internal current value (I

CCI

-typ) reflects

what is typically seen when running the given code.

The following steps are recommended for applications requiring very low current
consumption:

1. Minimize external memory accesses; use internal memory accesses instead.

2. Minimize the number of pins that are switching.

3. Minimize the capacitive load on the pins.

4. Connect the unused inputs to pull-up or pull-down resistors.

5.5

2.75mA

4-6

DSP56002/D, Rev. 3

MOTOROLA

Design Considerations

Host Port Considerations

HOST PORT CONSIDERATIONS

Careful synchronization is required when reading multibit registers that are written
by another asynchronous system. This is a common problem when two
asynchronous systems are connected. The situation exists in the host interface. The
following paragraphs present considerations for proper operation.

Host Programming Considerations

UNSYNCHRONIZED READING OF RECEIVE BYTE REGISTERS

When reading receive byte registers (RXH, RXM, and RXL) the host programmer
should use interrupts or poll the RXDF flag that indicates that data is available. This
assures that the data in the receive byte registers will be stable.

OVERWRITING TRANSMIT BYTE REGISTERS

The host programmer should not write to the transmit byte registers (TXH, TXM, and
TXL) unless the TXDE bit is set indicating that the transmit byte registers are empty.
This guarantees that the transmit byte registers will transfer valid data to the HRX
register.

SYNCHRONIZATION OF STATUS BITS FROM DSP TO HOST

HC, HREQ, DMA, HF3, HF2, TRDY, TXDE, and RXDF status bits are set or cleared
from inside the DSP and read by the host processor. The host can read these status
bits very quickly without regard to the clock rate used by the DSP, but the possibility
exists that the state of the bit could be changing during the read operation. This is
generally not a system problem, since the bit will be read correctly in the next pass of
any host polling routine.

Note:

Refer to

DSP56002 User's Manual

sections describing the I/O Interface and

Host/DMA Interface Programming Model for descriptions of these status
bits.

OVERWRITING THE HOST VECTOR

The Host programmer should change the Host Vector register only when the Host
Command bit (HC) is clear. This change guarantees that the DSP interrupt control
logic will receive a stable vector.

Design Considerations

Host Port Considerations

MOTOROLA

DSP56002/D, Rev. 3

4-7

CANCELLING A PENDING HOST COMMAND EXCEPTION

The host processor may elect to clear the HC bit to cancel the Host Command
Exception request at any time before it is recognized by the DSP. Because the host
does not know exactly when the exception will be recognized (due to exception
processing synchronization and pipeline delays), the DSP may execute the Host
Command Exception after the HC bit is cleared. For these reasons, the HV bits must
not be changed at the same time the HC bit is cleared.

VARIANCE IN THE HI TIMING

HI timing may vary during initial startup during the time after reset before the PLL
locks. Therefore, before a host attempt to load (i.e., bootstrap) the DSP, the host
should first make sure that the HI port programming has been completed. The
following steps can be used to ensure that the programming is complete:

1. Set the INIT bit in the ICR

2. Poll the INIT bit until it is cleared.

3. Read the ISR.

An alternate method is:

1. Write the TREQ/RREQ together with INIT.

2. Poll INIT, ISR, and the HREQ pin.

DSP Programming Considerations

SYNCHRONIZATION OF STATUS BITS FROM HOST TO DSP

DMA, HF1, HF0, and HCP, HTDE, and HRDF status bits are set or cleared by the host
processor side of the interface. These bits are individually synchronized to the DSP
clock.

Note:

Refer to

DSP56002 User's Manual

sections describing the I/O Interface and

Host/DMA Interface Programming Model for descriptions of these status
bits.

READING HF0 AND HF1 AS AN ENCODED PAIR

A potential problem exists when reading status bits HF0 and HF1 as an encoded pair
(i.e., the four combinations 00, 01, 10, and 11 each have significance). A very small
probability exists that the DSP will read the status bits synchronized during
transition. The solution to this potential problem is to read the HF0 and HF1 bits
twice and check for consensus.

4-8

DSP56002/D, Rev. 3

MOTOROLA

Design Considerations

Package Compatibility

PACKAGE COMPATIBILITY

The PQFP and TQFP packages are designed so that a single Printed Circuit Board
(PCB) can accommodate either package. The two package pinouts are similarly
sequenced. Proper orientation of each package with the smaller TQFP footprint
inside the PQFP footprint allow connection of PCB traces to either package. For
example, the D0 pin is near the corner of both the PQFP package (pin 84) and the
TQFP package (pin 109), and is adjacent to D1 on both packages.

Note:

Some "no connect" pins in the TQFP pin sequence are excluded from the
PQFP pin sequence.

MOTOROLA

DSP56002/D, Rev. 3

5-1

SECTION

ORDERING INFORMATION

DSP56002 ordering information in the table below lists the pertinent information
needed to place an order. Consult a Motorola Semiconductor sales office or
authorized distributor to determine availability and to order parts.

Table 5-1

DSP56002 Ordering Information

Part

Supply

Voltage

Package Type

Pin Count

Frequency

(MHz)

Order Number

DSP56002

5 V

Plastic Quad Flat Pack

(PQFP)

132

DSP56002FC40

DSP56002FC66

DSP56002FC80

Plastic Thin Quad Flat

Pack (TQFP)

144

DSP56002PV40

DSP56002PV66

DSP56002PV80

Ceramic Pin Grid Array

132

DSP56002RC40

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does
Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may
be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer
application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights
of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support life, or for any other application in which the
failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer
purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs,
damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury
or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent
regarding the design or manufacture of the part. Motorola and

are registered trademarks of Motorola, Inc.

Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

How to reach us:

USA/Europe/Locations Not Listed

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P.O. Box 5405
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303-675-2140
1 (800) 441-2447

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Technical Resource Center:

1 (800) 521-6274

DSP Helpline

dsphelp@dsp.sps.mot.com

Japan

Nippon Motorola Ltd.
SPD, Strategic Planning Office
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81-3-5487-8488

Internet

http://www.motorola-dsp.com

OnCE and Mfax are trademarks of Motorola, Inc.

Document Outline

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Document Outline

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