Document Outline

DSP56156 16-Bit Digital Signal Processor
Features
Documentation
Pin Groupings
Pin Descriptions
- Address and Data Bus
- Bus Control
- Interrupt and Mode Control
- Host Interface
- 16-Bit Timer
- Synchronous Serial Interfaces (SSI)
- On-Chip Emulation (OnCE Port)
- On-Chip Codec
- Power, Ground, and Clock
Electrical Characteristics and Timing
- Analog I/O Characteristics
- A/D and D/A Performance
- Other On-Chip Codec Characteristics
- DC Electrical Characteristics
- AC Electrical Characteristics
  - Clock Operation Timing
  - Other Clock and PLL Operation Timing
  - Reset, Stop, Wait, Mode Select, and Interrupt Timing
  - Capacitance Derating
  - External Bus Synchronous Timing
  - External Bus Asynchronous Timing
  - Bus Arbitration Timing„Slave Mode
  - Bus Arbitration Timing„Master Mode
  - Host Port Timing
  - SSI Timing
  - Timer Timing
  - OnCE Port Timing
Pin-Out and Package Information
Design Considerations
- Heat Dissipation
- Power, Ground, and Noise
- Power Consumption
- Host Port Considerations
- Bus Operation
- Analog I/O Considerations
Ordering Information

MOTOROLA INC., 1994

MOTOROLA

TECHNICAL DATA

SEMICONDUCTOR

The DSP56156 is a general-purpose MPU-style Digital Signal Processor (DSP). On a single semi-
conductor chip, the DSP56156 comprises a very efficient 16-bit digital signal processing core, pro-
gram and data memories, a number of peripherals, and system support circuitry. Unique features
of the DSP56156 include a built-in sigma-delta (²ý) codec and phase-locked loop (PLL). This com-
bination of features makes the DSP56156 a cost-effective, high-performance solution for many DSP
applications, especially speech coding, digital communications, and cellular base stations.

The central processing unit of the DSP56156 is the DSP56100 core processor. Like all DSP56100-

based DSPs, the DSP56156 consists of three execution units operating in parallel, allowing up to
six operations to be performed during each instruction cycle. This parallelism greatly increases the
effective processing speed of the DSP56156. The MPU-style programming model and instruction
set allow straightforward generation of efficient, compact code. The basic architectures and devel-
opment tools of Motorola's 16-bit, 24-bit, and 32-bit DSPs are so similar that understanding how to
design and program one greatly reduces the time needed to learn the others.

On-Chip Emulation (OnCE

port) circuitry provides convenient and inexpensive debug facil-

ities normally available only through expensive external hardware. Development costs are re-
duced and in-field testing is greatly simplified using the OnCE

port. Figure 1 illustrates the

DSP56156 in detail.

Figure 1 DSP56156 Block Diagram

Specifications and information herein are subject to change without notice.

OnCE is a trademark of Motorola, Inc.

Data

Control

Address

Data ALU

16 x 16 + 40 --> 40-bit MAC

Two 40-bit Accumulators

PLL

Clock

Gen.

GDB

PDB

XDB

Internal

Data

Bus

Switch

External

Data

Bus

Switch

Bus

Control

PAB

XAB1

XAB2

Address

Generation

Unit

External

Address

Bus

Switch

IRQ 2

16-bit Bus

16-bit

56100 DSP

Core

Program

Address

Generator

Program

Decode

Controller

Interrupt

Control

Program Control Unit

Sigma-

Delta

Codec

OnCETM Port

16-bit

Timer/

Event

Counter

Sync.

Serial

(SSI)

I/O

Host

Interface

(HI)

I/O

(boot)

Sync.

Serial

(SSI)

I/O

Data

Memory

2048

16 RAM

Program

Memory *

2048

16 RAM

16 ROM

* 12 k x 16 ROM replaces the program RAM on the DSP56156ROM

Advance Information

16-bit Digital Signal Processor

DSP56156

Order this document

by DSP56156/D

REV 1

DSP56156ROM

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DSP56156 Data Sheet

MOTOROLA

Introduction

DSP56156 Features

Digital Signal Processing Core

· Efficient, object code compatible, 16-bit 56100-Family DSP engine

-- Up to 30 Million Instructions Per Second (MIPS) 33 ns instruction cycle at 60 MHz
-- Up to 180 Million Operations Per Second (MOPS) at 60 MHz
-- Highly parallel instruction set with unique DSP addressing modes
-- Two 40-bit accumulators including extension byte
-- Parallel 16

16-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)

-- Double precision 32

32-bit multiply with 72-bit result in 6 instruction cycles

-- Least Mean Square (LMS) adaptive loop filter in 2 instructions
-- 40-bit Addition/Subtraction in 1 instruction cycle
-- Fractional and integer arithmetic with support for multiprecision arithmetic
-- Hardware support for block-floating point FFT
-- Hardware-nested DO loops including infinite loops
-- Zero-overhead fast interrupts (2 instruction cycles)
-- Three 16-bit internal data buses and three 16-bit internal address buses for

maximum information transfer on-chip

Memory

· On-chip Harvard architecture permitting simultaneous accesses to program

and memories

· 2048

16-bit on-chip program RAM and 64

16-bit bootstrap ROM

(or 12 k

16-bit on-chip program ROM on the DSP56156ROM)

· 2048

16-bit on-chip data RAM

· External memory expansion with 16-bit address and data buses

· Bootstrap loading from external data bus, Host Interface, or

Synchronous Serial Interface

Peripheral and Support Circuits

· Byte-wide Host Interface (HI) with Direct Memory Access support

· Two Synchronous Serial Interfaces (SSI) to communicate with codecs and

synchronous serial devices

-- Built in µ-law and A-law compression/expansion
-- Up to 32 software-selectable time slots in network mode

· 16-bit Timer/Event Counter also generates and measures digital waveforms

· On-chip sigma-delta voice band Codec:

-- Sampling clock rates between 100 kHz and 3 MHz
-- Four software-programmable decimation/interpolation ratios
-- Internal voltage reference (

of positive power supply)

-- No external components required

DSP56156 Features

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MOTOROLA

DSP56156 Data Sheet

Introduction

· On-chip peripheral registers memory mapped in data memory space

· Double buffered peripherals

· Up to 27 general purpose I/O pins

· Two external interrupt request pins

· On-Chip Emulation (OnCETM) port for unobtrusive, processor speed-independent

debugging

· Software-programmable, Phase-Locked Loop-based (PLL) frequency synthesizer for the

core clock

Miscellaneous Features

· Power-saving Wait and Stop modes

· Fully static, HCMOS design for operating frequencies from 40 or 60 MHz down to DC

· 112-pin Ceramic Quad Flat Pack (CQFP) surface-mount package; 20

3 mm

· 112-pin Plastic Thin Quad Flat Pack (TQFP) surface-mount package; 20

1.5 mm

· 5 V power supply

Product Documentation

This data sheet plus the two manuals listed in Table 1 are required for a complete DSP56156
description and are necessary to properly design with the part. Documentation is available
from a local Motorola distributor, a semiconductor sales office, or through a Motorola Litera-
ture Distribution Center.

Table 1 DSP56156 Documentation

Topic

Description

Order Number

DSP56100 Family Manual

Detailed description of the 56000-
family architecture and the 16-bit core
processor and instruction set

DSP56100FAMUM/AD

DSP56156 User's Manual

Detailed description of memory,
peripherals, and interfaces

DSP56156UM/AD

DSP56156 Data Sheet

Pin and package descriptions, and
electrical and timing specifications

DSP56156/D

DSP56156 Features

Documentation

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DSP56156 Data Sheet

MOTOROLA

Introduction

Related Documentation

Table 2 lists additional documentation relevant to the DSP56156.

Data Sheet Contents

This data sheet contains:

· signal definitions and pin locations
· electrical specifications and timings
· package descriptions
· design considerations
· ordering information

Table 2 Related Motorola Documentation

Topic

Description

Order Number

DSP Family Brochure

Overview of all DSP product families

BR1105/D

Development Tools

Product Brief. Includes ordering
information

DSPTOOLSP/D

Fractional and Integer Arithmetic

Application Report. Includes code

APR3/D

Fast Fourier Transforms (FFTs)

Application Report. Comprehensive
FFT algorithms and code for
DSP56001, DSP56156, and
DSP96002

APR4/D

G.722 Audio Processing

Application Report. Theory and code
using SB-ADPCM

APR404/D

Dr. BuB Bulletin Board

Flyer. Motorola's electronic bulletin
board where free DSP software is
available

BR297/D

Third Party Compendium

Brochures from companies selling

hardware and software that supports
Motorola DSPs

DSP3RDPTYPAK/D

University Support Program

Flyer. Motorola's program that sup-
ports universities in DSP research
and education

BR382/D

Documentation

Data Sheet Contents

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MOTOROLA

DSP56156 Data Sheet

Introduction

Pin Groupings

The DSP56156 is available in a 112-pin Ceramic Quad Flat Pack (CQFP) and a 112-pin Plastic
Thin Quad Flat Pack (TQFP). The input and output signals are organized into the functional
groups indicated in Table 3. Figure 2 illustrates the chip's pin functions.

NOTE:

OVERBARS are used throughout this document to indicate a signal which is at Ground voltage (typi-
cally a TTL logic low -- V

or V

) when the function is logically true. These signals are, likewise, at

voltage (typically a TTL logic high -- V

or V

) when the function is logically false.

Table 3 Functional Pin Groupings

Functional Group

Number of Pins

Address 16

Data Bus

Bus Control

Host Interface (HI)

Synchronous Serial Interfaces (SSI)

Timer Interface

Interrupt and Mode Control

Phase-Locked Loop (PLL) and Clock

On-Chip Emulation (OnCE

Port)

On-Chip Codec

Power (V

)

Ground (GND)

Total 112

Pin Groupings

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DSP56156 Data Sheet

MOTOROLA

Introduction

Figure 2 DSP56156 Pin Functions

These pins have an alternate function of general purpose input/output.

H0-H7*

HA0-HA2*
HR/W*
HEN*
HREQ*
HACK*

Interrupt/
Mode
Control

DSP56156

Host

Interface (HI)

On-Chip
Emulator
(OnCE

)

Port

STD0*
SRD0*
SCK0*
SC00-SC10*

STD1*
SRD1*
SCK1*
SC01-SC11*

MIC

AUX

SPKM

BIAS

VREF

VDIV

GND

SPKP

MODA/IRQA
MODB/IRQB

MODC

RESET

EXTAL
CLKO
SXFC

A0-A15

D0-D15

PS/DS

R/W

DSI/OS0

DSCK/OS1

DSO

Clock

and

Phase-locked

Loop

(PLL)

External

Bus

On-Chip
Codec

Two

Synchronous

Serial

Interfaces

(SSI)

112 pins

Timer/Event

Counter

TIN*
TOUT*

Pin Functions

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Pin Descriptions

MOTOROLA

DSP56156 Data Sheet

Pin Descriptions

Address and Data Bus

A0-A15

(Address Bus) -- three-state, active

high outputs.

A0-A15 change in t0 and

specify the address for external pro-
gram and data memory accesses. If
there is no external bus activity, A0-A15
remain at their previous values. A0-A15
are three-stated during hardware reset.

D0-D15

(Data Bus) -- three-state, active

high, bidirectional input/outputs.

Read data is sampled on the trailing
edge of t2, while write data output is
enabled by the leading edge of t2 and
three-stated at the leading edge of t0. If
there is no external bus activity, D0-D15
are three-stated. D0-D15 are also three-
stated during hardware reset.

Bus Control

PS/DS (Program/Data Memory Select) --

three-state, active low output.

This out-

put is asserted only when external data
memory is referenced. PS/DS timing is
the same for the A0-A15 address lines.
PS/DS is high for program memory ac-
cess and is low for data memory access. If
the external bus is not used during an in-
struction cycle (t0, t1, t2, t3), PS/DS goes
high in t0. PS/DS is in the high imped-
ance state during hardware reset.

R/W (Read/Write) -- three-state, active

low output.

Timing is the same as the

address lines, providing an "early
write" signal. R/W (which changes in
t0) is high for a read access and is low
for a write access. If the external bus is
not used during an instruction cycle

(t0, t1, t2, t3), R/W goes high in t0. R/W
is three-stated during hardware reset.

WR (Write Enable) -- three-state, active

low output.

This output is asserted dur-

ing external memory write cycles. When
WR is asserted in t1, the data bus pins
D0-D15 become outputs and the DSP
puts data on the bus during the leading
edge of t2. When WR is deasserted in t3,
the external data has been latched inside
the external device. When WR is assert-
ed, it qualifies the A0-A15 and PS/DS
pins. WR can be connected directly to
the WE pin of a static RAM. WR is three-
stated during hardware reset or when
the DSP is not bus master.

RD (Read Enable) -- three-state, active

low output.

This output is asserted

during external memory read cycles.
When RD is asserted in late t0/early t1,
the data bus pins D0-D15 become in-
puts and an external device is enabled
onto the data bus. When RD is deas-
serted in t3, the external data is latched
inside the DSP. When RD is asserted, it
qualifies the A0-A15 and PS/DS pins.
RD can be connected directly to the
OE pin of a static RAM or ROM. RD is
three-stated during hardware reset or
when the DSP is not bus master.

BS (Bus Strobe) -- three-state, active

low output.

Asserted at the start of a

bus cycle (during t0) and deasserted at
the end of the bus cycle (during t2).
This pin provides an "early bus start"
signal which can be used as address
latch and as an "early bus end" signal
which can be used by an external bus
controller. BS is three-stated during
hardware reset.

Address and Data Bus

Bus Control

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DSP56156 Data Sheet

MOTOROLA

Pin Descriptions

TA (Transfer Acknowledge) -- active

low input.

If there is no external bus ac-

tivity, the TA input is ignored by the
DSP. When there is external bus cycle
activity, TA can be used to insert wait
states in the external bus cycle. TA is
sampled on the leading edge of the
clock. Any number of wait states from 1
to infinity may be inserted by using TA.
If TA is sampled high on the leading
edge of the clock beginning the bus cy-
cle, the bus cycle will end 2T after the
TA has been sampled low on a leading
edge of the clock; if the Bus Control Reg-
ister (BCR) value does not program
more wait states. The number of wait
states is determined by the TA input or
by the Bus Control Register (BCR),
whichever is longer. TA is still sampled
during the leading edge of the clock
when wait states are controlled by the
BCR value. In that case, TA will have to
be sampled low during the leading edge
of the last period of the bus cycle pro-
grammed by the BCR (2T before the end
of the bus cycle programmed by the
BCR) in order not to add any wait states.
TA should always be deasserted during

t3 to be sampled high by the leading
edge of T0. If TA is sampled low (assert-
ed) at the leading edge of the t0 begin-
ning the bus cycle, and if no wait states
are specified in the BCR register, zero
wait states will be inserted in the exter-
nal bus cycle, regardless the status of
TA during the leading edge of T2.

BR (Bus Request) -- active low output

when in master mode, active low in-

put when in slave mode.

After power-

on reset, this pin is an input (slave
mode). In this mode, the bus request
BR allows another device such as a pro-
cessor or DMA controller to become
the master of the DSP external data
bus D0-D15 and external address bus
A0-A15. The DSP asserts BG a few T
states after the BR input is asserted.
The DSP bus controller releases control
of the external data bus D0-D15, ad-
dress bus A0-A15 and bus control pins
PS/DS, RD, WR, and R/W at the earli-
est time possible consistent with prop-
er synchronization. These pins are then
placed in the high impedance state and

Bus Control

T0 T1 T2 T3 T0 T1 T2 Tw T2 T3 T0 T1 T2 T3 T0 T1 T2 Tw T2 Tw T2 T3

T0 T1 T2 Tw T2 Tw T2 Tw T2 T3 T0 T1 T2 Tw T2 Tw T2 T3 T0 T1 T2

CLKO

Figure 3 TA Controlled Accesses

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Pin Descriptions

MOTOROLA

DSP56156 Data Sheet

the BB pin is deasserted. The DSP con-
tinues executing instructions only if in-
ternal program and data memory
resources are accessed. If the DSP re-
quests the external bus while BR input
pin is asserted, the DSP bus controller
inserts wait states until the external bus
becomes available (BR and BB deas-
serted). Note that interrupts are not
serviced when a DSP instruction is
waiting for the bus controller. Note
also that BR is prevented from inter-
rupting the execution of a read/ modi-
fy/write instruction.

If the master bit in the OMR register is
set, this pin becomes an output (Master
Mode). In this mode, the DSP is not the
external bus master and has to assert
BR to request the bus mastership. The
DSP bus controller will insert wait
states until BG input is asserted and
will then begin normal bus accesses af-
ter the rising of the clock which sam-
pled BB high. The BR output signal will
remain asserted until the DSP no long-
er needs the bus. In this mode, the Re-
quest Hold bit (RH) of the Bus Control
Register (BCR) allows BR to be asserted
under software control.

During external accesses caused by an
instruction executed out of external pro-
gram memory, BR remains asserted low
for consecutive external X memory ac-
cesses and continues toggling for con-
secutive external P memory accesses
unless the Request Hold bit (RH) is set
inside the Bus Control Register (BCR).

In the master mode, BR can also be
used for non arbitration purpose: if BG
is always asserted, BR is asserted in t0
of every external bus access. It can then
be used as a chip select to turn a exter-

nal memory device off and on between
internal and external bus accesses. BR
timing is in that case similar to A0-A15,
R/W and PS/DS; it is asserted and
deasserted during t0.

BG (Bus Grant) -- active low input when

in master mode, active low output

when in slave mode.

Output after

power on reset if the slave is selected,
this pin is asserted to acknowledge an
external bus request. It indicates that
the DSP will release control of the ex-
ternal address bus A0-A15, data bus
D0-D15 and bus control pins when BB
is deasserted. The BG output is assert-
ed in response to a BR input. When the
BG output is asserted and BB is deas-
serted, the external address bus A0-A15,
data bus D0-D15 and bus control pins
are in the high impedance state. BG as-
sertion may occur in the middle of an
instruction which requires more than
one external bus cycle for execution.
Note that BG assertion will not occur
during indivisible read-modify-write
instructions (BFSET, BFCLR, BFCHG).
When BR is deasserted, the BG output
is deasserted and the DSP regains con-
trol of the external address bus, data
bus, and bus control pins when the BB
pin is sampled high.

This pin becomes an input if the master
bit in the OMR register is set (Master
Mode). It is asserted by an external pro-
cessor when the DSP may become the
bus master. The DSP can start normal
external memory access after the BB pin
has been deasserted by the previous
bus master. When BG is deasserted, the
DSP will release the bus as soon as the
current transfer is completed. The state
of BG may be tested by testing the BS bit
in the Bus Control Register. BG is ig-
nored during hardware reset.

Bus Control

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DSP56156 Data Sheet

MOTOROLA

Pin Descriptions

BB (Bus Busy) -- active low input when

not bus master, active low output

when bus master.

This pin is asserted

by the DSP when it becomes the bus
master and it performs an external ac-
cess. It is deasserted when the DSP re-
leases bus mastership. BB becomes an
input when the DSP is no longer the
bus master.

Interrupt and Mode Control

MODA/IRQA

(Mode Select A/External In-

terrupt Request A)

input.

This in-

put has two functions:

· to select the initial chip operating

mode and,

· to allow an external device to request

a DSP interrupt after internal syn-
chronization.

MODA is read and internally latched
in the DSP when the processor exits the
reset state. MODA and MODB select
the initial chip operating mode. Several
clock cycles after leaving the reset state,
the MODA pin changes to the external
interrupt request IRQA. The chip oper-
ating mode can be changed by soft-
ware after reset.

The IRQA input is a synchronized ex-
ternal interrupt request which indi-
cates that an external device is
requesting service. It may be pro-
grammed to be level sensitive or nega-
tive edge triggered. If level sensitive
triggering is selected, an external pull
up resistor is required for wired-OR
operation. If the processor is in the stop
standby state and IRQA is asserted, the
processor will exit the stop state.

MODB/IRQB

(Mode Select B/External In-

terrupt Request B)

input.

This in-

put has two functions:

· to select the initial chip operating

mode and,

· to allow an external device to request

a DSP interrupt after internal syn-
chronization.

MODB is read and internally latched in
the DSP when the processor exits the
reset state. MODA and MODB select
the initial chip operating mode. Several
clock cycles after leaving the reset state,
the MODB pin changes to the external
interrupt request IRQB. After reset, the
chip operating mode can be changed
by software.

The IRQB input is an external interrupt
request which indicates that an exter-
nal device is requesting service. It may
be programmed to be level sensitive or
negative edge triggered. If level sensi-
tive triggering is selected, an external
pull up resistor is required for wired-
OR operation.

MODC (Mode Select C)

input.

This input

selects the initial bus operating mode.
When tied high, the external bus is pro-
grammed in the master mode (BR out-
put and BG input) and when tied low
the bus is programmed in the slave
mode (BR input and BG output).
MODC is read and internally latched in
the DSP when the processor exits the
reset state. After RESET, the bus operat-
ing mode can be changed by software by
writing the MC bit of the OMR register.

RESET (Reset)

input.

This input is a direct

hardware reset of the processor. When
RESET is asserted, the DSP is initialized
and placed in the reset state. A Schmitt

Interrupt and Mode Control

Bus Control

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Pin Descriptions

MOTOROLA

DSP56156 Data Sheet

trigger input is used for noise immunity.
When the reset pin is deasserted, the ini-
tial chip operating mode is latched from
the MODA and MODB pins, and the ini-
tial bus operating mode is latched from
the MODC pin. The internal reset signal
should be deasserted synchronized with
the internal clocks.

Host Interface

H0-H7 (Host Data Bus)

bidirectional.

This

bidirectional data bus is used to transfer
data between the host processor and the
DSP. This bus is an input unless enabled
by a host processor read. H0-H7 may be
programmed as Port B general purpose
parallel I/O pins called PB0-PB7 when
the Host Interface (HI) is not being used.

HA0-HA2 (Host Address 0-2)

input*.

These

inputs provide the address selection
for each HI register and are stable
when HEN is asserted. HA0-HA2 may
be programmed as Port B general pur-
pose parallel I/O pins called PB8-PB10
when the HI is not being used.

HR/W (Host Read/Write)

input*.

This in-

put selects the direction of data transfer
for each host processor access. If HR/W
is high and HEN is asserted, H0-H7 are
outputs and DSP data is transferred to
the host processor. If HR/W is low and
HEN is asserted, H0-H7 are inputs and
host data is transferred to the DSP.
When HEN is asserted, HR/W is stable.
HR/W may be programmed as a gen-
eral purpose I/O pin called PB11
when the HI is not being used.

HEN

(Host Enable)

input*.

This input en-

ables a data transfer on the host data
bus. When HEN is asserted and HR/W
is high, H0-H7 becomes an output and
DSP data may be latched by the host
processor. When HEN is asserted and
HR/W is low, H0-H7 is an input and
host data is latched inside the DSP
when HEN is deasserted. Normally a
chip select signal derived from host ad-
dress decoding and an enable clock is
connected to the Host Enable. HEN
may be programmed as a general pur-
pose I/O pin called PB12 when the HI
is not being used.

HREQ (Host Request)

output*.

This open-

drain output signal is used by the HI to
request service from the host proces-
sor. HREQ may be connected to an in-
terrupt request pin of a host processor,
a transfer request of a DMA controller,
or a control input of external circuitry.
HREQ is asserted when an enabled re-
quest occurs in the HI. HREQ is deas-
serted when the enabled request is
cleared or masked, DMA HACK is as-
serted, or the DSP is reset. HREQ may
be programmed as a general purpose
I/O pin (not open-drain) called PB13
when the HI is not being used.

HACK (Host Acknowledge)

input*.

This

input has two functions:

· to provide a host acknowledge signal

for DMA transfers and,

· to control handshaking and to pro-

vide a host interrupt acknowledge
compatible with MC68000 family
processors.

If programmed as a host acknowledge
signal, HACK may be used as a data
strobe for HI DMA data transfers. If pro-
grammed as an MC68000 host interrupt

Host Interface

* These pins can be bidirectional when programmed as general purpose I/O.

Interrupt and Mode Control

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DSP56156 Data Sheet

MOTOROLA

Pin Descriptions

acknowledge, HACK enables the HI
Interrupt Vector Register (IVR) onto
the host data bus H0-H7 if the Host Re-
quest HREQ output is asserted. In this
case, all other HI control pins are ig-
nored and the HI state is not affected.
HACK may be programmed as a gen-
eral purpose I/O pin called PB14 when
the HI is not being used.

16-bit Timer

TIN (Timer Input)

input*.

This input re-

ceives external pulses to be counted by
the on-chip 16-bit timer when external
clocking is selected. The pulses are in-
ternally synchronized to the DSP core
internal clock. TIN may be pro-
grammed as a general purpose I/O pin
called PC10 when the external event
function is not being used.

TOUT (Timer Output)

output*.

This out-

put generates pulses or toggles on a
timer overflow event or a compare
event. TOUT may be programmed as a
general purpose I/O pin called PC11
when disabled by the timer out enable
bits (TO2-TO0).

Synchronous Serial
Interfaces (SSI)

STD0-1 (SSI0-1 Transmit Data)

output*.

These output pins transmit serial data
from the SSI0-1 Transmit Shift Register.
STD0 and STD1 may be programmed
as a general purpose I/O pin called

PC0 and PC5, respectively, when the
STD function is not being used.

SRD0-1 (SSI0-1 Receive Data)

input*.

These input pins receive serial data and
transfer the data to the SSI0-1 Receive
Shift Register. SRD0 and SRD1 may be
programmed as a general purpose I/O
pin called PC1 and PC6, respectively,
when the SRD function is not being
used.

SCK0-1 (SSI0-1 Serial Clock)

bidirection-

al.

These bidirectional pins provide the

serial bit rate clock for the SSI0-1 inter-
face. SCK0 and SCK1 may be pro-
grammed as a general purpose I/O pin
called PC2 and PC7, respectively,
when the SSI0-1 interfaces are not be-
ing used.

SC10-11 (SSI0-1 Serial Control 1)

bidirec-

tional.

These bidirectional pins are

used by the SSI0-1 serial interface as
frame sync I/O or flag I/O. SC10 and
SC11 may be programmed as a general
purpose I/O pin called PC3 and PC8,
respectively, when the SSI0-1 are not
using these pins.

SC00-01 (SSI0-1 Serial Control 0)

bidirec-

tional.

These bidirectional pins are

used by the SSI0-1 serial interface as
frame sync I/O or flag I/O. SC00 and
SC01 may be programmed as a general
purpose I/O pin called PC4 and PC9,
respectively, when the SSI0-1 are not
using these pins.

16-bit Timer

SSI

* These pins can be bidirectional when programmed as general purpose I/O.

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Pin Descriptions

MOTOROLA

DSP56156 Data Sheet

On-Chip Emulation
(OnCE

Port)

DSI/OS0 (Debug Serial Input/Chip Status 0)

bidirectional.

The DSI/OS0 pin, when

an input, is the pin through which seri-
al data or commands are provided to
the OnCE port controller. The data re-
ceived on the DSI pin will be recog-
nized only when the DSP has entered
the debug mode of operation. Data
must have valid TTL logic levels before
the serial clock falling edge. Data is al-
ways shifted into the OnCE serial port
most significant bit (MSB) first. When the
DSP is not in the debug mode, the DSI/
OS0 pin provides information about the
chip status if it is an output and used in
conjunction with the OS1 pin.

DSCK/OS1 (Debug Serial Clock/Chip Status 1)

bidirectional.

The DSCK/OS1 pin,

when an input, is the pin through
which the serial clock is supplied to the
OnCE port. The serial clock provides
pulses required to shift data into and
out of the OnCE serial port. Data is
clocked into the OnCE port on the fall-
ing edge and is clocked out of the
OnCE serial port on the rising edge. If
the DSCK/OS1 pin is an output and
used in conjunction with the OS0 pin, it
provides information about the chip
status when the DSP is not in the debug
mode.

DSO (Debug Serial)

output.

The debug

serial output provides the data con-
tained in one of the OnCE port control-
ler registers as specified by the last
command received from the command
controller. When idle, this pin is high.
When the requested data is available, the
DSO line will be asserted (negative true
logic) for four T cycles (one instruction

cycle) to indicate that the serial shift reg-
ister is ready to receive clocks in order to
deliver the data. When the chip enters
the debug mode due to an external de-
bug request (DR), an internal software
debug request (DEBUG), a hardware
breakpoint occurrence or a trace/step
occurrence, this line will be asserted for
three T cycles to indicate that the chip
has entered the debug mode and is wait-
ing for commands. Data is always shift-
ed out the OnCE serial port with the
most significant bit first.

DR (Debug Request)

input.

The debug

request input provides a means of en-
tering the debug mode of operation.
This pin, when asserted, will cause the
DSP to finish the current instruction be-
ing executed, enter the debug mode,
and wait for commands to be entered
from the debug serial input line.

On-Chip Codec

AUX (Auxiliary)

input

. This pin is select-

ed as the analog input to the A/D con-
verter when the INS bit is set in the
codec control register COCR. This pin
should be left floating when the codec
is not used.

BIAS (Bias current)

input

. This input is

used to determine the bias current for
the analog circuitry. Connecting a re-
sistor between BIAS and GNDA will
program the current bias generator.
This pin should be left floating when
the codec is not used.

MIC (Microphone)

input

. This pin is se-

lected as the analog input to the A/D
converter when the INS bit is cleared in

OnCE

On-Chip Codec

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DSP56156 Data Sheet

MOTOROLA

Pin Descriptions

the codec control register COCR. This
pin should be left floating when the co-
dec is not used.

SPKP (Speaker Plus)

output

. This pin is

the positive analog output from the on-
chip D/A converter. This pin should be
left floating when the codec is not used.

SPKM (Speaker Minus)

output

. This pin is

the negative analog output from the
on-chip D/A converter. This pin
should be left floating when the codec
is not used.

VREF (Voltage Reference)

output

. This

pin is the op-amp buffer output in the
reference voltage generator. It has a
value of (

CCA

. This pin should al-

ways be connected to the GNDA
through two capacitors, even when the
codec is not used.

VDIV (Voltage Division)

output

. This

output pin is also the output to the on-
chip op-amp buffer in the reference
voltage generator. It is connected to a
resistor divider network located within
the codec block which provides a volt-
age equal to (

CCA

. This pin should

be connected to the GND via a capacitor
when the codec is used and should be
left floating when the codec is not used.

Power, Ground, and Clock

(Power)

-- Power pins

GND (Ground)

-- Ground pins

CCS

(Synthesizer Power)

-- This pin sup-

plies a quiet power source to the Phase-
Locked Loop (PLL) to provide greater
frequency stability.

GNDS (Synthesizer Ground)

-- This pin sup-

plies a quiet ground source to the PLL
to provide greater frequency stability.

CCA

(Analog Power)

-- This pin is the posi-

tive analog supply input. It should be con-
nected to V

when the codec is not used.

GNDA (Analog Ground)

-- This pin is the an-

alog ground return. It should be con-
nected to digital GND when the codec
is not used.

EXTAL (External Clock)

input.

This input

should be driven by an external clock or
by an external oscillator. After being
squared, the input frequency can be
used as the DSP core internal clock. In
that case, it is divided by two to produce
a four phase instruction cycle clock, the
minimum instruction time being two in-
put clock periods. This input frequency
is also used, after division, as input
clock for the on-chip codec and the on-
chip PLL.

CLKO (Clock Output)

output.

This pin

outputs a buffered clock signal. By pro-
gramming two bits (CS1-CS0) inside
the PLL Control Register (PLCR), the
user can select between outputting a
squared version of the signal applied to
EXTAL, a squared version of the signal
applied to EXTAL divided by 2, and a
delayed version of the DSP core master
clock. The clock frequency on this pin
can be disabled by setting the Clockout
Disable bit (CD; bit 7) of the Operating
Mode Register (OMR). When disabled,
the pin can be left floating.

SXFC (External Filter Capacitor)

-- This pin

adds an external capacitor to the PLL
filter circuit. A low leakage capacitor
should be connected between and lo-
cated very close to SXFC and V

CCS

Power, Ground, and Clock

On-Chip Codec

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Electrical Characteristics and Timing

MOTOROLA

DSP56156 Data Sheet

Electrical Characteristics and Timing

CAUTION:

Exceeding maximum electrical ratings will permanently damage or
disable the chip, or impair the chip's long term reliability.

The DSP56156 is fabricated in high density HCMOS with TTL compatible inputs and CMOS
compatible outputs.

NOTE: This device contains protective circuitry to guard against damage due to high static voltage or electrical

fields. However, normal precautions are advised to avoid application of any voltages higher than maximum
rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied
to an appropriate logic voltage level (e.g., either GND or V

Table 4 Maximum Electrical Ratings (GND = 0 Vdc)

Rating

Symbol

Value

Unit

Supply Voltage

-0.3 to +7.0

All Input Voltages

GND - 0.5 to V

+ 0.5

Current Drain per Pin excluding V

and GND

Storage Temperature

stg

-55 to +150

Table 5 Operating Conditions

Supply Voltage

Junction Temperature

(

Min

Max

Min

Max

4.5

5.5

-40

115

Table 6 Thermal Characteristics of CQFP and TQFP Packages

Thermal Resistance

Characteristics

Symbol

Value

Rating

CQFP

TQFP

Junction to Ambient

C/W

Junction to Case (estimated)

C/W

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Electrical Characteristics and Timing

DSP56156 Data Sheet

MOTOROLA

Analog I/O Characteristics

= 5.0 V dc ± 10%, T

= -40

to +125

The analog I/O characteristics of this device are listed in Table 7.
For additional information regarding the use of analog signals, see "Design Considerations"
at the end of this document.

Table 7 Analog I/O Characteristics

Characteristic

Min

Typ

Max

Unit

Input Impedance on MIC and AUX (See Note 1)

1400

Input Capacitance on MIC and AUX

Peak Input Voltage on the MIC/AUX Input for Full Scale
Linearity (0.14 dBm0):

6 dB - MGS1 - 0 = 00

(See Note 2)

0 dB - MGS1 - 0 = 01
6 dB - MGS1 - 0 = 10
17 dB - MGS1 - 0 = 11

--
--
--
--

1.414
0.707

354
100

Vp
Vp

mVp
mVp

Internal Input Gain Variation;
G = -6 dB, 0 dB, 6 dB or 17 dB
(±0.83 dB variation due to 10% variation on V

G - 0.83

G + 0.83

VREF Output Voltage

1.8

2.2

VREF Output Current

±1

DC Offset Between SPKP and SPKM

100

Allowable Differential Load Capacitance on
SPKP and SPKM (with 1 k

in series)

0.05

µF

Allowable Single-ended Load Capacitance on
SPKP or SPKM (with 0.5 k

in series)

(See Note 3)

100

0.1

µF

Maximum Single-ended Signal Output Level

Maximum Differential Signal Output Level

Single-ended Load Resistance

500

Differential Load Resistance

Resistance BIAS

(See

Note 4)

Internal Output Volume Control Variation
VC = -20, -15, -10, -5, 0, 6, 12, 18, 24, 30, 35 dB
(± 0.83 dB variation due to 10% variation on V

)

VC - 0.83

VC + 0.83

NOTES:

1. Minimum value reached for a Codec clock of 3 MHz, typical for 2 MHz and maximum for 100 kHz
2. 0 dBm0 corresponds to 3.14 dB below the input saturation level
3. AC coupling is necessary in single-ended mode when the load resistor is not tied to VREF
4. ± 10%

Analog I/O Characteristics

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Electrical Characteristics and Timing

MOTOROLA

DSP56156 Data Sheet

A/D and D/A Performance

CCA

= 5.0 V dc ± 10%, T

= -40

to +125

The A/D and D/A performance of the codec section are given in Table 8 with an
example presented in Figure 4.

NOTES:

1. 0 dB gain on the A/D and D/A; Codec clock at 1.538 MHz with 128 decimation/interpolation ratio and

tested at 1502 Hz

2. 0 dBm0 corresponds to -3.14 dB below the input saturation level

Figure 4 Example: S/N and S/N+T Performance for the A/D Section

Table 8 A/D and D/A Performance of Codec

Characteristic

Level

Min

Typ

(See Note 1)

Max

Unit

Analog to Digital Section Signal to Noise
plus Distortion Ratio (S/N+T)

0 dBm0

(See Note 2)

-50 dBm0

Digital to Analog Section Signal to Noise
plus Distortion Ratio (S/N+T)

0 dB

-50 dB

S in dB

S/N

S/N+T

Signal in dB

÷13

CODEC

÷(12+1)*4

2 MHz

1 MHz

PLL

52 MHz

COCR=$E400

PLL

Codec

÷(12+1)x4

÷ 13

÷ 6.5

13 MHz

A/D and D/A Performance

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Electrical Characteristics and Timing

DSP56156 Data Sheet

MOTOROLA

Other On-Chip Codec Characteristics

CCA

= 5.0 V dc ± 10%, T

= -40

to +125

C, C

= 50 pF + 1 TTL Load)

The analog I/O characteristics of this device are shown in Table 9.

Table 9 Analog I/O Characteristics of On-Chip Codec

Characteristic

Min

Typ

Max

Unit

Codec Master Clock

0.1

2.048

MHz

Codec Sampling Rate

16000

37000

A/D Section Group Delay

0.2

msec

D/A Section Group Delay

0.2

msec

Other On-Chip Codec Characteristics

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DC Electrical Characteristics and Timing

MOTOROLA

DSP56156 Data Sheet

DC Electrical Characteristics

(GND = 0 V dc)

= 5.0 V dc ± 10%, T

= -40

to +125

C, C

= 50 pF + 1 TTL Load)

The DC electrical characteristics of this device are shown in Table 10.

NOTES:

1. When EXTAL is AC coupled, V

IHC

- V

ILC

S 1 V must be true.

2. Input capacitance is periodically sampled and not 100% tested in production.

Table 10 DC Electrical Characteristics

Characteristic

Symbol

Min

Typ

Max

Unit

Input High Voltage
except EXTAL, RESET, MODA, MODB, MODC

2.0

Input Low Voltage
except EXTAL, MODA, MODB, MODC

-0.5

0.8

Input High Voltage

EXTAL DC coupled
EXTAL AC coupled (See Note 1)

IHC

70% of V

--
--

Input Low Voltage

EXTAL DC coupled
EXTAL AC coupled (See Note 1)

ILC

-0.5
-0.5

--
--

20% of V

-1

Input High Voltage RESET

IHR

2.5

Input High Voltage MODA, MODB, MODC

IHM

3.5

Input Low Voltage MODA, MODB, MODC

ILM

-0.5

2.0

Input Leakage Current

EXTAL

RESET, MODA, MODB, MODC, TA, DR, BR

-100

-1

100

µA
µA

Three-State (Off-State) Input Current

(@2.4 V/0.5 V)

TSI

-10

µA

Output High Voltage (I

= -10 µA)

OHC

-0.1

Output High Voltage (I

= -0.4 mA)

2.4

Output Low Voltage (I

= 10 µA)

OLC

0.1

Output Low Voltage (I

= 3.2 mA

R/W I

= 1.6 mA; Open Drain

HREQ I

= 6.7 mA, TXD I

= 6.7 mA)

0.4

Input Capacitance

(See Note 2)

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AC Electrical Characteristics and Timing

DSP56156 Data Sheet

MOTOROLA

AC Electrical Characteristics

(GND = 0 V dc)

The timing waveforms in the AC Electrical Characteristics are tested with a V

maximum of

0.5 V and a V

minimum of 2.4 V for all pins, except EXTAL, RESET, MODA, MODB and

MODC. These five pins are tested using the input levels set forth in the DC Electrical Charac-
teristics

. AC timing specifications which are referenced to a device input signal are measured

in production with respect to the 50% point of the respective input signal's transition. The
DSP56156 output levels are measured with the production test machine V

and V

refer-

ence levels set at 0.8 V and 2.0 V respectively.

Clock Operation Timing

The system clock to the DSP56156 must be externally supplied to EXTAL as illustrated in
Figure 6.

NOTES: 1. Rise and fall time may be relaxed to 12 ns maximum if the EXTAL input frequency is less than or equal

to 20 MHz. If the EXTAL input frequency is between 20 MHz and 40 MHz, rise and fall time should
meet the specified values in the 40 MHz column (4 ns maximum).

2. The duty cycle may be relaxed to 43-57% if the EXTAL input frequency is less than or equal to 20 MHz.

If the EXTAL input frequency is between 20 MHz and 40 MHz, the duty cycle should be such that T

and T

meet the specified values in the 40 MHz column (12 ns minimum).

3. T = I

CYC

/ 4 is used in the electrical characteristics. The exact length of each T is affected by the duty

cycle of the external clock input.

4. Duty cycles and EXTAL widths are measured at the EXTAL input signal midpoint when AC coupled and

at V

/2 when not AC coupled.

Table 11 Clock Operation Timing

Num

Characteristics

Sym

40 MHz

50 MHz

60 MHz

Unit

Min

Max

Min

Max

Min

Max

Frequency of Operation (EXTAL)

MHz

Instruction Cycle Time = 2T

CYC

Wait State Time = T

= 2T

16.6

EXTAL Cycle Period

16.6

EXTAL Rise Time (See Note 1)

EXTAL Fall Time (See Note 1)

EXTAL Width High
48-52% duty cycle
(See Notes 2, 3, 4)

9.6

EXTAL Width Low
48%-52% duty cycle
(See Notes 2, 3, 4)

9.6

Clock Operation Timing

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AC Electrical Characteristics and Timing

MOTOROLA

DSP56156 Data Sheet

Figure 5 External Clock Timing

Other Clock and PLL Operation Timing

Clock and PLL timings are listed in Table 12 and the clocking configurations are illustrated in
Figure 6.

Figure 6 Clocking Configurations

EXTAL

IHC

Midpoint

90%

10%

ILC

Table 12 Clock and PLL Timing

Characteristics

Min

Max

Unit

PLL Output frequency

Max Fosc

(See Note 1)

MHz

EXTAL Input Clock Amplitude (See Note 2)

Vpp

NOTES:

1. Maximum DSP operating frequency. See Table 11.
2. An AC coupling capacitor is required on EXTAL if the levels are out of the normal CMOS level

range (V

ILC

>20% of V

or V

IHC

<70% of V

EXTAL

PLL

PLLE=1

PLLE=0

Fosc

ED3-ED0

CLKO

internal phase PH0 at Fosc

CS1-CS0

1000 pF

GSM

SXFC

CCS

XFC

0.01

GNDS

0.1

100 K

1 to

6.5

CODEC

VCO

PFD

YD3-YD0

1 to

10 nF

Clock Operation Timing

PLL

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AC Electrical Characteristics and Timing

DSP56156 Data Sheet

MOTOROLA

Reset, Stop, Wait, Mode Select, and Interrupt Timing

= 5.0 V dc ± 10%, T

= -40

to +125

C, C

= 50 pF + 1 TTL Load)

cyc = Clock cycle =

instruction cycle = 2 T cycles

ws = Number of wait states programmed into external bus access using BCR (WS = 0 - 31)

Table 13 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Num

Characteristics

40 MHz

50 MHz

60 MHz

Unit

Min

Max

Min

Max

Min

Max

RESET Assertion to Address, Data and
Control Signals High Impedance

Minimum Stabilization Duration
(See Note 1)

OMR bit 6=0

OMR bit 6=1

600KT

60T

--
--

600KT

60T

--
--

600KT

60T

--
--

ns
ns

Asynchronous RESET Deassertion to
First External Address Output
(See Note 7)

16T

18T+20

16T

18T+17

16T

18T+15

Synchronous Reset Setup Time from
RESET Deassertion to Rising Edge of
CLKO

cyc-4

cyc-3

cyc-2

Synchronous Reset Delay Time from
CLKO High to the First External Access
(See Note 7)

16T+3

16T+20

16T+ 3

16T+18

16T+3

16T+16

Mode Select Setup Time

Mode Select Hold Time

Edge-triggered Interrupt Request Width

Delay from IRQA, IRQB Assertion to
External Data Memory Access Out Valid
- Caused by First Interrupt

Instruction Fetch

- Caused by First Interrupt

Instruction Execution

11T+4

19T+4

11T+4

19T+4

11T+3

19T+3

Delay from IRQA, IRQB Assertion to
General Purpose Output Valid Caused
by the Execution of the First Interrupt
Instruction

22T+5

22T+4

22T+3

Delay from External Data Memory
Address Output Valid Caused by First
Interrupt Instruction Execution to Inter-
rupt Request Deassertion for Level Sen-
sitive Fast Interrupts (See Note 2)

5T-26

cyc

5T-24

cyc

5T-22

cyc

Reset, Stop, Wait, Mode Select, and Interrupt Timing

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AC Electrical Characteristics and Timing

MOTOROLA

DSP56156 Data Sheet

= 5.0 V dc ± 10%, T

= -40

to +125

C, C

= 50 pF + 1 TTL Load)

Table 13 Reset, Stop, Wait, Mode Select, and Interrupt Timing (continued)

Num

Characteristics

40 MHz

50 MHz

60 MHz

Unit

Min

Max

Min

Max

Min

Max

Delay from General-Purpose
Output Valid Caused by the
Execution of the First Inter-
rupt Instruction to IRQA,
IRQB Deassertion for Level
Sensitive Fast Interrupts -- If
2nd Interrupt Instruction is:

Single Cycle

(See Note 2)

Two Cycles

cyc - 29

3 cyc - 29

cyc - 27

3 cyc - 27

cyc - 26

3 cyc - 26

Synchronous setup time from
IRQA, IRQB assertion to
Synchronous falling edge of
CLKO (See Notes 5 and 6)

cyc-3

cyc-2

cyc-1

Falling Edge of CLKO to First
Interrupt Vector Address Out
Valid after Synchronous
recovery from Wait State
(See Notes 3 and 5)

27T+3

27T+20

27T+3

27T+18

27T+3

27T+16

IRQA Width Assertion to
Recover from Stop State
(See Note 4)

Delay from IRQA Assertion to
Fetch of first instruction (exit-
ing Stop)
(See Notes 1 and 3)

OMR bit 6=0
OMR bit 6=1

524303T+4

47T+4

--
--

524303T+3

47T+3

--
--

524303T+3

47T+3

--
--

ns
ns

Duration for Level Sensitive
IRQA Assertion to Cause the
Fetch of First IRQA Interrupt
Instruction (exiting Stop)
(See Notes 1 and 3)

OMR bit 6=0
OMR bit 6=1

524303T

47T

--
--

524303T

47T

--
--

524303T

47T

--
--

ns
ns

Delay from Level Sensitive
IRQA Assertion to First Inter-
rupt Vector Address Out
Valid (exiting Stop)
(See Notes 1 and 3)

OMR bit 6=0
OMR bit 6=1

524303T+4

47T+4

--
--

524303T+3

47T+3

--
--

524303T+3

47T+3

--
--

ns
ns

Reset, Stop, Wait, Mode Select, and Interrupt Timing

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AC Electrical Characteristics and Timing

DSP56156 Data Sheet

MOTOROLA

NOTES:

1. Circuit stabilization delay is required during reset when using an external clock in two cases:

· after power-on reset
· when recovering from Stop mode

2. When using fast interrupts, IRQA or IRQB is defined as level-sensitive, then timings 20 and 21

apply to prevent multiple interrupt service. To avoid these timing restrictions, the negative edge-trig-
gered mode is recommended when using fast interrupts.

3. The interrupt instruction fetch is visible on the pins only in Mode 3.
4. The minimum is specified for the duration of an edge triggered IRQA interrupt required to recover

from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted.

5. Timing #22 is for all IRQx interrupts while timing #23 is only when exiting the Wait state.
6. Timing #22 triggers off T1 in the normal state and off phi1 when exiting the Wait state.
7. The instruction fetch is visible on the pins only in Mode 2 and Mode 3.

Figure 7 Asynchronous Reset Timing

Figure 8 Synchronous Reset Timing

RESET

D0-D15

A0-A15

PS/DS

R/W

First Fetch

IHR

CLKO

RESET

A0-A15

PS/DS

R/W

Reset, Stop, Wait, Mode Select, and Interrupt Timing

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AC Electrical Characteristics and Timing

MOTOROLA

DSP56156 Data Sheet

Figure 9 Operating Mode Select Timing

Figure 10 External Interrupt Timing (Negative Edge-Triggered)

Figure 11 External Level-Sensitive Fast Interrupt Timing

RESET

MODA

MODB

MODC

IHR

IRQA

IRQB

IHM

ILM

IRQA

IRQB

First Interrupt Instruction Execution

A0-A15

PS/DS

R/W

IRQA
IRQB

a) First Interrupt Instruction Execution

General

Purpose

I/O Pin

IRQA
IRQB

b) General Purpose I/O

Reset, Stop, Wait, Mode Select, and Interrupt Timing

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AC Electrical Characteristics and Timing

DSP56156 Data Sheet

MOTOROLA

Figure 12 Synchronous Interrupt from Wait State Timing

Figure 13 Recovery from Stop State Using Asynchronous Interrupt Timing

Figure 14 Recovery from Stop State Using IRQA Interrupt Service

T0, T2

phi0

T1, T3

phi1

CLKO

IRQA

IRQB

A0-A15

PD/DS

R/W

Instruction Fetch

First Interrupt

IRQA

A0-A15

PD/DS

R/W

Not IRQA Interrupt Vector

First Instruction Fetch

IRQA

A0-A15

PD/DS

R/W

First IRQA Interrupt
Instruction Fetch

Reset, Stop, Wait, Mode Select, and Interrupt Timing

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AC Electrical Characteristics and Timing

MOTOROLA

DSP56156 Data Sheet

Table 14 Wait and Stop Timings

Num

Characteristics

40 MHz

50 MHz

60 MHz

Unit

Min

Max

Min

Max

Min

Max

DR Asserted to CLK high (Setup
Time for Synchronous Recovery
from Wait State)

cyc - 4

cyc - 3

cyc - 2

CLK high to DSO (ACK) Valid
(Enter Debug Mode) after Syn-
chronous Recovery from Wait
State

18 cyc

DR to DSO (ACK) Valid
(Enter Debug Mode)
- After Asynchronous Recovery

from Stop State

- After Asynchronous Recovery

from Wait State

29 cyc

18 cyc

29 cyc

18 cyc

29 cyc

18 cyc

DR Assertion Width
- to Recover from Wait/Stop

without entering debug mode

- to Recover from Wait/Stop

short wake-up and enter
debug mode

- to Recover from Stop

long wake-up and enter
debug mode

29 cyc

262157

cyc

10 cyc

29 cyc

262157

cyc

10 cyc

29 cyc

262157

cyc

10 cyc

Figure 15 Recovery from Wait State Using DR Pin -- Synchronous Timing

(input)

DSO

(output)

Reset, Stop, Wait, Mode Select, and Interrupt Timing

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AC Electrical Characteristics and Timing

DSP56156 Data Sheet

MOTOROLA

Figure 16 Recovery from Wait/Stop State Using DR Pin -- Asynchronous Timing

Capacitance Derating

The DSP56156 External Bus Timing Specifications are designed and tested at the maximum ca-
pacitive load of 50 pF, including stray capacitance. Typically, the drive capability of the Exter-
nal Bus pins (A0-A15, D0-D15, PS/DS, RD, BS, WR, R/W) derates linearly at 1 ns per 12 pF of
additional capacitance from 50 pF to 250 pF of loading. Port B and C pins derate linearly at 1 ns
per 5 pF of additional capacitance from 50 pF to 250 pF of loading.

When an internal memory access follows an external memory access, the PS/DS, R/W, RD
and WR strobes remain deasserted and A0-A15 do not change from their previous state.

CLKO

(output)

(input)

DSO

(output)

T1, T3

T0, T2

Reset, Stop, Wait, Mode Select, and Interrupt Timing

Capacitance Derating

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AC Electrical Characteristics and Timing

MOTOROLA

DSP56156 Data Sheet

External Bus Synchronous Timing

= 5.0 V dc ± 10%, T

= -40

to +125

C, C

= 50 pF + 1 TTL Load)

Table 15 lists external bus synchronous timing. Figure 17 and illustrate the bus timings
with no wait states and two wait states, respectively.

Table 15 External Bus Synchronous Timing

Num

Characteristic

40 MHz

50 MHz

60 MHz

Unit

Min

Max

Min

Max

Min

Max

EXTAL CLK In High to CLKO High

2.4

CLKO High to

a. A0-A15 Valid

b. PS/DS, R/W Valid, BS, RD Asserted

4.7

(See Note)

BS Width Deasserted

18.3

13.4

9.8

CLKO High to WR Asserted Low

T+3.1

T+12.4

T+3.1

T+12.4

T+3.1

T+12.4

WR and RD Deasserted High to BS
Asserted Low (2 Successive Bus Cycles)

14.3

15.8

11.8

13.3

10.2

11.8

CLKO High to BS Deasserted

2.6

10.3

2.6

10.3

2.6

10.3

TA Valid to CLKO High (Setup)

4.5

CLKO High to TA Invalid (Hold)

CLKO High to D0-D15 Out Valid

1.7

7.1

1.7

7.1

1.7

7.1

CLKO High to D0-D15 Out Invalid

2.0

D0-D15 In Valid to CLKO Low (Setup)

CLKO Low to D0-D15 In Invalid (Hold)

CLKO Low to WR, RD Deasserted

WR, RD Hold Time from CLKO Low

2.2

CLKO High to D0-D15 Three-state

CLKO High to D0-D15 Out Active

1.2

4.2

1.2

4.2

1.2

4.2

CLKO High to A0-A15, PS/DS, R/W Invalid

2.8

NOTE:

10 ns C

= 25 pF

External Bus Synchronous Timing

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AC Electrical Characteristics and Timing

DSP56156 Data Sheet

MOTOROLA

NOTE: During Read-Modify-Write instructions and internal instructions, the address lines do not change state.

Figure 17 External Bus Synchronous Timing -- No Wait States

EXTAL

(Input)

Data In

Data Out

CLKO

(Output)

A0-A15

PS/DS

R/W

(See Note)

(Output)

(Input)

D0-D15

(Output)

D0-D15

(Input)

External Bus Synchronous Timing

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AC Electrical Characteristics and Timing

DSP56156 Data Sheet

MOTOROLA

Bus Arbitration Timing -- Slave Mode

= 5.0 V dc ± 10%, T

= -40

to +125

C, C

= 50 pF + 1 TTL Load)

cyc = Clock cycle =

instruction cycle = 2 T cycles

WS = Number of Wait States for external X or P memory, Determined by BCR

WT =

cyc=2T

WX = Number of Wait States for external X memory, Determined by BCR

WP = Number of Wait States for external P memory, Determined by BCR

NOTES:

1. With no external access from the DSP56156
2. During external read or write access
3. During external read-modify-write access
4. During Stop mode -- external bus is released and BG is always low
5. During Wait mode
6. With external accesses pending by the DSP56156
7. Slave mode, when bus is still busy after bus request has been deasserted

Table 17 Slave Mode

Num

Characteristics

40/50/60 MHz

Unit

Min

Max

BR Input to CLKO low setup time

Delay from BR Input Assertion to

(See Note 1)

BG Output Assertion

(See Note 2)
(See Note 3)

(See Note 4)
(See Note 5)

5T+1.9
3T+1.9
5T+1.9

T+1.9

9T+4.2

6T+WT+4.2

26T+4T x WX

+2T x WP+4.2

3T+4.2

CLKO high to BG Output Assertion

1.9

5.2

BG Output Deassertion Duration

(See Note 1)
(See Note 5)
(See Note 6)

5T-0.5
2T-0.5
3T-0.5

--
--
--

CLKO High to Control Bus High Impedance

2.7

6.5

CLKO High to BB Output Deassertion

3.2

7.8

CLKO High to BB Input

3.3

8.1

BR Input Deassertion to

(See Note 1)

BG Output Deassertion

(See Note 5)
(See Note 7)

4T+2.5
3T+3.2
3T+3.2

9T+6.4
8T+7.8
8T+8.0

CLKO Low to BG Deassertion

(See Note 1)

CLKO High to BG Deassertion

(See Note 5)

CLKO High to BG Deassertion

(See Note 7)

2.5
3.2
3.2

6.4
7.8
8.0

CLKO High to BB Output Active

1.3

3.6

CLKO High to BB Output Assertion

2.3

CLKO High to Address and Control Bus Active

CLKO High to Address and Control Bus Valid

4.4

Bus Arbitration Timing -- Slave Mode

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AC Electrical Characteristics and Timing

MOTOROLA

DSP56156 Data Sheet

Bus Arbitration Timing -- Master Mode

= 5.0 V dc ± 10%, T

= -40

to +125

C, C

= 50 pF + 1 TTL Load)

Figure 22 Bus Arbitration Timing -- Master Mode -- Bus Acquisition

Table 18 Master Mode

Num

Characteristic

40 MHz

50 MHz

60 MHz

Unit

Min

Max

Min

Max

Min

Max

CLKO High to BR Output Assertion
CLKO High to BR Output Deassertion

4.7

BG Input Asserted/ Deasserted to CLKO
Low (Setup)

9.2

6.5

4.5

CLKO Low to BG Input Invalid (Hold)

BB Input Deasserted to CLKO Low (Setup)

9.2

6.5

4.5

CLKO Low to BB Input Deasserted (Hold)

CLKO High to BB Output Asserted

4.7

Three-state

CLKO

(Output)

(Input)

(I/O)

A0-A15

PS/DS

R/W

Bus Arbitration Timing -- Master Mode

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AC Electrical Characteristics and Timing

MOTOROLA

DSP56156 Data Sheet

Host Port Timing

= 5.0 V dc ± 10%, T

= -40

to +125

C, C

= 50 pF + 1 TTL Load)

T =

CYC

/ 4

cyc = Clock cycle =

instruction cycle= 2 T cycle

HSDL

= Host Synchronization Delay Time (See Note 1)

suh

= Host Processor Data Setup Time

Active low lines should be "pulled up" in a manner consistent with the AC and DC specifica-
tions.

Table 19 Host Port Timing

Num

Characteristic

40 MHz

50 MHz

60 MHz

Unit

Min

Max

Min

Max

Min

Max

100

tHSDL Host Synchronous Delay
(See Note 1)

101

HEN/HACK Assertion Width

· CVR, ICR, ISR Read

· Read
· Write

(See Notes 2, 4)

2T+36

32+t

suh

--
--

2T+33

29+t

suh

--
--

2T+30

26+t

suh

--
--

102

HEN/HACK Deassertion Width
(See Note 2)

103

Minimum Cycle Time Between Two
HEN Assertion for Consecutive
CVR, ICR, ISR Reads

4T+36

4T+33

4T+30

104

Host Data Input Setup Time before
HEN/HACK Deassertion

105

Host Data Input Hold Time after
HEN/HACK Deassertion

106

HEN/HACK Assertion to Output
Data Active from High Impedance

107

HEN/HACK Assertion to Output
Data Valid

108

HEN/HACK Deassertion to Output
Data High Impedance

18.5

109

Output Data Hold Time after
HEN/HACK Deassertion

Host Port Timing

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AC Electrical Characteristics and Timing

DSP56156 Data Sheet

MOTOROLA

NOTES:

1. "Host Synchronization Delay (tHSDL)" is the time period required for the DSP56156 to sample any

external asynchronous input signal, determine whether it is high or low, and synchronize it to the
internal clock.

2. See Host Port Considerations.
3. HREQ is pulled up by 1 k

4. Only if two consecutive reads from one of these registers are executed.

Table 19 Host Port Timing (continued)

Num

Characteristic

40 MHz

50 MHz

60 MHz

Unit

Min

Max

Min

Max

Min

Max

110

HR/W Low Setup Time before HEN Assertion

111

HR/W Low Hold Time after HEN Deassertion

112

HR/W High Setup Time to HEN Assertion

113

HR/W High Hold Time after HEN/HACK
Deassertion

114

HA0-HA2 Setup Time before HEN Assertion

7.5

115

HA0-HA2 Hold Time after HEN Deassertion

116

DMA HACK Assertion to HREQ Deassertion
(See Note 3)

+37

+36

+35

117

DMA HACK Deassertion to HREQ
Assertion (See Note 3)

for DMA RXL Read

for DMA TXL Write

for All Other Cases

HSDL

+3T+5

HSDL

+2T+5

--
--

HSDL

3T+5

HSDL

+2T+5

--
--

HSDL

+3T+4

HSDL

+2T+4

--
--

118

Delay from HEN Deassertion to HREQ
Assertion for RXL Read (See Note 3)

HSDL

+3T+5

HSDL

+3T+5

HSDL

+3T+4

119

Delay from HEN Deassertion to HREQ
Assertion for TXL Write (See Note 3)

HSDL

+2T+5

HSDL

+2T+5

HSDL

+2T+4

120

Delay from HEN Assertion to HREQ
Deassertion for RXL Read, TXL Write
(See Note 3)

+37

+36

+35

Host Port Timing

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AC Electrical Characteristics and Timing

DSP56156 Data Sheet

MOTOROLA

Figure 26 Host Read Cycle (Non-DMA Mode)

Figure 27 Host Write Cycle (Non-DMA Mode)

HREQ

(Output)

HEN

(Input)

HA0-HA2

(Input)

HR/W

(Input)

H0-H7

(Output)

118

120

103

101

102

114

115

112

113

107

108

109

RXL
Read

RXH
Read

Address

Valid

Address

Valid

Data
Valid

106

119

120

101

102

114

115

TXL

Write

TXH

Write

Address

Valid

Address

Valid

Data
Valid

HREQ

(Output)

HEN

(Input)

HA0-HA2

(Input)

HR/W

(Input)

H0-H7

(Input)

110

111

104

105

103

Host Port Timing

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AC Electrical Characteristics and Timing

DSP56156 Data Sheet

MOTOROLA

Synchronous Serial Interfaces (SSI) Timing

= 5.0 V dc ± 10%, T

= -40

to + 125

C, C

= 50 pF + 1 TTL Load)

T = I

CYC

/ 4

SCK = Serial Clock Pin

FST (Transmit Frame Sync) = SCx0 Pin

FSR (Receive Frame Sync) = SCx1 Pin

i ck = Internal Clock

x ck = External Clock

i ck a = Internal Clock, Asynchronous Mode (Asynchronous

implies that FSR and FST are two different frame syncs)

i ck s = Internal Clock, Synchronous Mode (Synchronous implies

that only one frame sync FS is used)

bl = bit

length

wl = word length

NOTE: All the timings for the SSI are given for a non-inverted serial clock polarity (SCKP=0 in CRB) and a non-

inverted frame sync (FSI=0 in CRB). If the polarity of the clock and/or the frame sync have been inverted,
all the timings remain valid by inverting the clock signal SCK and/or the frame sync FSR/FST in the tables
and in the figures.

Table 20 Synchronous Serial Interfaces Timing

Num

Characteristic

40/50/60 MHz

Case

Unit

Min

Max

130

Clock Cycle (See Note)

100

131

Clock High Period

132

Clock Low Period

133

Output Clock Rise/Fall Time

134

SCK Rising Edge to FSR Out
(bl) High

--
--

32
18

x ck

i ck a

135

SCK Rising Edge to FSR Out
(bl) Low

--
--

32
15

x ck

i ck a

136

SCK Rising Edge to FSR Out
(wl) High

--
--

32
15

x ck

i ck a

137

SCK Rising Edge to FSR Out
(wl) Low

--
--

32
15

x ck

i ck a

138

Data In Setup Time before SCK
Falling Edge

30
40

--
--

x ck

i ck

139

Data In Hold Time after SCK
Falling Edge

25
12

--
--

x ck

i ck

SSI Timing

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AC Electrical Characteristics and Timing

DSP56156 Data Sheet

MOTOROLA

Table 20 Synchronous Serial Interfaces Timing (continued)

Num

Characteristic

40/50/60MHz

Case

Unit

Min

Max

140

FSR Input (bl) High before SCK
Falling Edge

--
--

x ck

i ck a

141

FSR Input (wl) High before SCK
Falling Edge

--
--

x ck

i ck a

142

FSR Input Hold Time after SCK
Falling Edge

--
--

x ck

i ck a

143

Flags Input Setup before SCK
Falling Edge

--
--

x ck

i ck

144

Flags Input Hold Time after SCK
Falling Edge

--
--

x ck

i ck

145

SCK Rising Edge to FST Out
(bl) High

--
--

33
15

x ck

i ck

146

SCK Rising Edge to FST Out
(bl) Low

--
--

30
15

x ck

i ck

147

SCK Rising Edge to FST Out
(wl) High

--
--

30
15

x ck

i ck

148

SCK Rising Edge to FST Out
(wl) Low

--
--

33
15

x ck

i ck

149

SCK Rising Edge to Data Out
Enable from High Impedance

--
--

30
12

x ck

i ck

150

SCK Rising Edge to Data Out Valid

--
--

30
12

x ck

i ck

151

SCK Rising Edge to Data Out High
Impedance

--
--

30
20

x ck

i ck

152

FST Input (bl) Setup Time before SCK
Falling Edge

--
--

x ck

i ck

153

FST Input (wl) to Data Out Enable from
High Impedance

154

FST Input (wl) Setup Time before SCK
Falling Edge

--
--

x ck

i ck

155

FST Input Hold Time after SCK
Falling Edge

--
--

x ck

i ck

156

Flag Output Valid after SCK
Rising Edge

--
--

32
15

x ck

i ck

SSI Timing

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AC Electrical Characteristics and Timing

DSP56156 Data Sheet

MOTOROLA

Figure 31 SSI Transmitter Timing

NOTE:

In the Network mode, output flag transitions can occur at the start of each time slot within the frame.
In the Normal mode, the output flag state is asserted for the entire frame period.

150

151

155

152

153

155

156

First Bit

Last Bit

(See Note)

132

130

133

131

145

146

147

148

149

150

SCK

(Input/Output)

FST (Bit)

Out

FST (Word)

Out

Data Out

FST (Bit)

FST (Word)

Flags Out

154

Timer Timing

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AC Electrical Characteristics and Timing

MOTOROLA

DSP56156 Data Sheet

Timer Timing

= 5.0 V dc ± 10%, T

= -40

to +125

C, C

= 50 pF + 1 TTL Load)

Figure 32 Timer Timing

Table 21 Timer Timing

Num

Characteristic

40/50/60 MHz

Unit

Min

Max

170

TIN Valid to CLKO Low (Setup time)

171

CLKO Low to TIN Invalid (Hold time)

172

CLKO High to TOUT Asserted

3.5

173

CLKO High to TOUT Deasserted

5.1

20.7

174

TIN Period

175

TIN High/Low Period

170

172

171

173

CLKO

(Output)

TIN

(Input)

TOUT

(Output)

OnCE Port Timing

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AC Electrical Characteristics and Timing

DSP56156 Data Sheet

MOTOROLA

OnCE

Port Timing

= 5.0 V dc ± 10%, T

= -40

to +125

C, C

= 50 pF + 1 TTL Load)

NOTES:

1. 45%-55% duty cycle
2. Td = DSCK High (Timing #183)

Table 22 OnCE Port Timing

Num

Characteristic

40/50/60 MHz

Unit

Min

Max

180

DSCK High to DSO Valid

181

DSI Valid to DSCK Low (Setup)

5.2

182

DSCK Low to DSI Invalid (Hold)

183

DSCK High

(See Note 1)

2Tc

184

DSCK Low

(See Note 1)

2Tc

185

DSCK Cycle Time

(See Note 1)

4Tc

186

CLKO High to OS0-OS1 Valid

14.5

187

CLKO High to OS0-OS1 Invalid

188

Last DSCK High to OS0-OS1

(See Note 2)

Last DSCK High to ACK Active (data)

(See Note 2)

Last DSCK High to ACK Active (command)

(See Note 2)

10T+Td+14.5
10T+Td+13.5
21T+Td+13.5

--
--

189

DSO (ACK) Asserted to OS0-OS1 Three-state

190

DSO (ACK) Asserted to First DSCK High

3Tc

191

DSO (ACK) Width Asserted:

· when entering debug mode

· when acknowledging command/data transfer

3T-2

2Tc+0.5

3T-5

2Tc+3

ns
ns

192

Last DSCK High of Read Register to First
DSCK High of Next Command

6Tc

193

DSCK High to DSO Invalid

(See Note 2)

Td+11.2

194

DR asserted to DSO (ACK) Asserted

11T+19.5

OnCE Port Timing

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Pin-out and Package

DSP56156 Data Sheet

MOTOROLA

Pin-out and Package Information

Figure 39 Top View of the DSP56156 112-pin Plastic (FC) and Ceramic (FE) Quad Flat Packages

GND4

D2
D3

CC3

D4
D5

GND5

D6
D7
D8
D9

GND6

D10

D11

CC4

D12
D13

GND7

D14
D15

CCA

SPKP

SPKM

GNDA

VDIV

VREF

Orientation Mark

GND3

GNDQ1

CC2

GND2

CCQ

GND1

CC1

GND0

/IRQ

NOTE: An OVERBAR indicates the signal is asserted when the voltage = ground (active low).

CCQ

CC5

GND8

/
D

DSO

CK/OS

I/O

GNDQ0

CCS

EXT

SC0

GND9

/
PC

/PB

(Top View)

MODA/IRQA
RESET
STD0/PC0
SRD0/PC1
SCK0/PC2
SC10/PC3
SC00/PC4
TIN/PC10
V

CC7

TOUT/PC11
HA0/PB8
GND10
HA1/PB9
HA2/PB10
HR/W/PB11
HEN/PB12
HACK/PB14
HREQ/PB13
H0/PB0
H1/PB1
STD1/PC5
SRD1/PC6
H4/PB4
H3/PB3
H2/PB2
V

CC6

H5/PB5
H6/PB6

Top View

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Pin-out and Package

MOTOROLA

DSP56156 Data Sheet

Figure 40 Bottom View of the DSP56156 112-pin Plastic (FC) and Ceramic (FE) Quad Flat Packages

NOTE: An OVERBAR indicates the signal is asserted when the voltage = ground (active low).

MODA/IRQA

RESET

STD0/PC0

SRD0/PC1

SCK0/PC2

SC10/PC3
SC00/PC4

TIN/PC10

CC7

TOUT/PC11

HA0/PB8

GND10

HA1/PB9

HA2/PB10

HR/W/PB11

HEN/PB12

HACK/PB14

HREQ/PB13

H0/PB0
H1/PB1

STD1/PC5

SRD1/PC6

H4/PB4
H3/PB3
H2/PB2

CC6

H5/PB5
H6/PB6

GND4
D2
D3
V

CC3

D4
D5
GND5
D6
D7
D8
D9
GND6
D10
D11
V

CC4

D12
D13
GND7
D14
D15
TA
DR
V

CCA

SPKP
SPKM
GNDA
VDIV
VREF

Orientation Mark

/
P

SCK

/
P

GND9

01/

PC9

CCS

GNDS

GNDQ0

CLK

I/O

/OS1

R/W

/DS

GND8

CC5

CCQ0

BIA

MIC

MODB/

I
RQB

CC1

CCQ

A10

CC2

A12

A13

A14

A15

(on Top side)

(Bottom View)

Bottom View

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Pin-out and Package

DSP56156 Data Sheet

MOTOROLA

Table 23

DSP56156 General Purpose I/O Pin Identification

112-pin

Package

Pin #

DSP56156

Primary Pin

Function

DSP56156

General

Purpose I/O

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

HA0

PB8

HA1

PB9

HA2

PB10

HR/W

PB11

HEN

PB12

HREQ

PB13

HACK

PB14

STD0

PC0

SRD0

PC1

SCK0

PC2

SC10

PC3

SC00

PC4

STD1

PC5

SRD1

PC6

SCK1

PC7

SC11

PC8

SC01

PC9

TIN

PC10

TOUT

PC11

General Purpose I/O

NOTES:

1. In Tables 23, 24, and 25, OVERBAR indicates the signal is asserted when the voltage = ground (active low).

2. For more information on power and ground, see Table 26 under Design Considerations.

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Pin-out and Package

DSP56156 Data Sheet

MOTOROLA

Table 24

DSP56156 Pin Identification by Pin Number

112-pin

Package

Pin #

Signal Name

112-pin

Package

Pin #

Signal Name

112-pin

Package

Pin #

Signal Name

GND4

CC7

PS/DS

TIN/PC10

SC00/PC4

CC3

R/W

SC10/PC3

DSO

SCK0/PC2

DSCK/OS1

SRD0/PC1

GND5

DSI/OS0

STD0/PC0

CLKO

RESET

GNDQ0

MODA/IRQA

GNDS

MODB/IRQB

SXFC

MODC

GND6

CCS

D10

EXTAL

D11

SC01/PC9

GND0

CC4

GND9

D12

SC11/PC8

D13

SCK1/PC7

CC1

GND7

H7/PB7

D14

H6/PB6

D15

H5/PB5

GND1

CC6

CCQ1

H2/PB2

CCA

H3/PB3

SPKP

H4/PB4

SPKM

SRD1/PC6

100

GNDA

STD1/PC5

101

GND2

VDIV

H1/PB1

102

A10

VREF

H0/PB0

103

CC2

MIC

HREQ/PB13

104

GNDQ1

AUX

HACK/PB14

105

A11

BIAS

HEN/PB12

106

A12

HR/W/PB11

107

A13

CCQ0

HA2/PB10

108

GND3

HA1/PB9

109

A14

GND10

110

A15

CC5

HA0/PB8

111

TOUT/PC11

112

GND8

Signal Name

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Pin-out and Package

DSP56156 Data Sheet

MOTOROLA

Table 25

DSP56156 Pin Identification by Signal Name

112-pin

Package

Pin #

Signal Name

112-pin

Package

Pin #

Signal Name

112-pin

Package

Pin #

Signal Name

GNDQ0

104

GNDQ1

GNDS

D10

D11

D12

D13

100

D14

102

A10

D15

105

A11

HA0

106

A12

DSCK

HA1

107

A13

DSI

HA2

109

A14

DSO

HACK

110

A15

EXTAL

HEN

AUX

GND0

HR/W

GND1

HREQ

101

GND2

IRQA

BIAS

108

GND3

IRQB

GND4

MIC

GND5

MODA

CLKO

GND6

MODB

111

GND7

MODC

112

GND8

OS0

GND9

OS1

GND10

PB0

GNDA

PB1

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Pin-out and Package

DSP56156 Data Sheet

MOTOROLA

Table 25

DSP56156 Pin Identification by Signal Name (continued)

112-pin

Package

Pin #

Signal Name

112-pin

Package

Pin #

Signal Name

112-pin

Package

Pin #

Signal Name

PB2

PC7

STD1

PB3

PC8

SXFC

PB4

PC9

PB5

PC10

TIN

PB6

PC11

TOUT

PB7

PS/DS

CC1

PB8

R/W

103

CC2

PB9

CC3

PB10

RESET

CC4

PB11

SC00

CC5

PB12

SC01

CC6

PB13

SC10

CC7

PB14

SC11

CCA

PC0

SCK0

CCQ0

PC1

SCK1

CCQ1

PC2

SPKM

CCS

PC3

SPKP

VDIV

PC4

SRD0

VREF

PC5

SRD1

PC6

STD0

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Pin-out and Package

DSP56156 Data Sheet

MOTOROLA

-L-

VIEW Y

PIN 1
Identifier

112

108 Place

VIEW P

0.15 (0.006)

0.20 (0.008)

T L-M S N S

0.20 (0.008)

T L-M S

N S

0.20 (

.
008)

-
M

0.20 (

.
008)

-
M

-M-

-N-

-H-

DATUM

PLANE

-T-

SEATING

PLANE

VIEW Y

3 Place

-L-, -M-, -N-

R R1

R R2

-H-

DATUM

PLANE

VIEW P

MIN

MAX

MILLIMETERS

INCHES

DIM

18.880

2.740

0.220

2.340

0.220

0.130

0.650

22.950

0.300

0.200

0.120

20.400

3.450

0.380

3.060

0.330

0.230

0.950

23.450

0.600

0.132

0.743

0.108

0.009

0.092

0.009

0.005

0.026

0.904

0.012

0.008

0.0047

0.803

0.135

0.015

0.120

0.013

0.009

0.037

0.923

0.024

0.0052

0.650 BSC

0.0256 BSC

0.325 BSC

0.0128 BSC

1.800 REF

0.070 REF

0.200 REF

0.008 REF

0.200 REF

0.008 REF

NOTES:

1. Dimensioning and tolerancing per ANSI Y14.5M, 1982.

2. Controlling dimension: millimeter.

3. Datum plane -H- is coincident with the bottom of the lead

where the lead exits the ceramic body.

4. Datums -L-, -M- and -N- to be determined at datum plane -H-.

5. Dimensions S and V to be determined at seating plane -T-.

6. Dimensions A and B define maximum ceramic body dimensions

including glass protrusion and mismatch.

0.127 (0.005)

T L-M

BASE
METAL

PLATING

SECTION J1-J1

112 Place

VIEW ROTATED 90

Figure 41 DSP56156 112-pin Ceramic Quad Flat Pack (CQFP) Mechanical Information

NOTE: BSC = Between Statistical Center

(i.e., typical)

TOP
VIEW

Case 915-01

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Pin-out and Package

DSP56156 Data Sheet

MOTOROLA

0.100 (0.004)

VIEW AB

SEATING

PLANE

-T-

-L-, -M-, -N-

VIEW Y

BASE
METAL

SECTION J1-J1

(VIEW ROTATED 90

COUNTER CLOCKWISE)

VIEW AB

0.13 (0.005)

T L -M

VIEW Y

DIM

MIN

MAX

MIN

MAX

INCHES

MILLIMETERS

20.000 BSC

0.790 BSC

10.000 BSC

0.395 BSC

20.000 BSC

0.790 BSC

10.000 BSC

0.395 BSC

1.400

1.600

0.055

0.063

0.050

0.150

0.002

0.006

1.350

1.450

0.053

0.057

0.270

0.370

0.011

0.014

0.450

0.750

0.018

0.030

0.270

0.330

0.011

0.013

0.650 BSC

0.0256 BSC

0.115

0.175

0.006

0.007

0.500 BSC

0.020 BSC

0.325 BSC

0.013 BSC

0.100

0.200

0.004

0.008

0.100

0.200

0.004

0.008

22.000 BSC

0.866 BSC

11.000 BSC

0.433 BSC

22.000 BSC

0.866 BSC

11.000 BSC

0.433 BSC

0.250 REF

0.010 REF

1.000 REF

0.039 REF

0.115

0.135

0.004

0.005

PIN 1
Identifier

112

-L-

-M-

-N-

0.200 (0.008) T L-M N

0.200 (0.008) H L-M N

4x 28 TIPS

0.25 (0.010)

108x

GAGE PLANE

0.050 (0.002)

-H-

NOTES:

1. Dimensioning and tolerancing per ANSI Y14.5M, 1982.
2. Controlling dimension: Millimeter.
3. Datum plane -H- is located at bottom of lead and is coincident with the lead

where the lead exits the plastic body at the bottom of the parting line.

4. Datums -L-, -M- and -N- to be determined at datum plane -H-.
5. Dimensions S and V to be determined at seating plane -T-.
6. Dimensions A and B do not include mold protrusion. Allowable protrusion is

0.25 (0.010) per side. Dimensions A and B do include mold mismatch and are
determined at datum plane -H-.

7. Dimension D does not include dambar protrusion. Allowable dambar

protrusion shall not cause the D dimension to exceed 0.43 (0.017).

Figure 42

DSP56156 112-pin Plastic Thin Quad Flat Pack (TQFP) Mechanical Information

NOTE: BSC = Between Statistical Center

(i.e., typical)

TOP
VIEW

Case 987-01

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Design Considerations

DSP56156 Data Sheet

MOTOROLA

Design Considerations

is device-related and cannot be influ-

enced by the user. However,

is user-de-

pendent and can be minimized by such
thermal management techniques as heat
sinks, ambient air cooling, and thermal con-
vection. Thus, good thermal management on
the part of the user can significantly reduce

so that

approximately equals

Substitution of

for

in equation (1) will

result in a lower semiconductor junction
temperature. Values for thermal resistance
presented in this document, unless estimat-
ed, were derived using the procedure de-
scribed in Motorola Reliability Report 7843,
"Thermal Resistance Measurement Method
for MC68XX Microcomponent Devices", and
are provided for design purposes only. Ther-
mal measurements are complex and depen-
dent on procedure and setup. User-derived
values for thermal resistance may differ.

Power, Ground, and
Noise

Each DSP56156 V

pin should be provided

with a low-impedance path to +5 volts. Each
DSP56156 GND pin should likewise be pro-
vided with a low-impedance path to ground.
The power supply pins drive distinct groups
of logic on chip as shown in Table 26.

The V

power supply should be by-

passed to GND ground using at least six
0.01 0.1 µF bypass capacitors located ei-
ther underneath the chip's socket or as close
as possible to the four sides of the package.
The capacitor leads and the associated
printed circuit traces connecting to chip V

and GND should be kept to less than 0.5" per

Heat Dissipation

The average chip junction temperature, T

, in

C, can be obtained from:

= T

+ (P

)

(1)

Where:

= ambient temperature,

= package thermal resistance,

junction-to-ambient,

C/W

= P

INT

+ P

I/O

INT

= I

watts -- chip internal

power

I/O

= power dissipation on input and

output pins -- user determined

For most applications P

I/O

< P

INT

and P

I/O

can

be neglected. An appropriate relationship be-
tween P

and T

(if P

I/O

is neglected) is:

= K/(T

+ 273)

(2)

Solving equations (1) and (2) for K gives:

K = P

+ 273) + P

(3)

Where K is a constant pertaining to the partic-
ular package. K can be determined from
equation (2) by measuring P

(at equilibri-

um) for a known T

. Using this value of K, the

values of P

and T

can be obtained by solv-

ing equations (1) and (2) iteratively for any
value of T

. The total thermal resistance of a

package (

) can be separated into two com-

ponents,

and

, representing the barrier

to heat flow from the semiconductor junction
to the package (case) surface (

) and from

the case to the outside ambient (

). These

terms are related by the equation:

(4)

Heat Dissipation

Power, Ground, and Noise

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Design Considerations

MOTOROLA

DSP56156 Data Sheet

capacitor lead. The use of at least a four lay-
er board is recommended, employing two
inner layers as V

and GND planes. All

output pins on this DSP have fast rise and
fall times. Printed Circuit Board (PCB)
trace length should be minimized in order
to minimize undershoot and reflections
caused by these fast output switching
times. This recommendation particularly
applies to the address and data buses as
well as the PS/DS, BS, RD, WR, R/W, inter-
rupt, and HEN pins. Maximum PCB trace
lengths on the order of 6" are recommended.
Capacitance calculations should consider all

device loads as well as parasitic capacitanc-
es due to PCB traces. Attention to proper
PCB layout and bypassing becomes espe-
cially critical in systems with higher capac-
itive loads because these loads create
higher transient currents in the V

and

GND circuits.

Clock signals should not be run across

many signals and should be kept away
from analog power and ground traces as
well as any analog signals. See Figure 44 for
more details.

Power, Ground, and Noise

Table 26 Power and Ground Connections

Circuitry

Power

Ground

Signal

Name

Pin #

Signal

Name

Pin #

Address Bus Buffers

CC1

CC2

103

GND0
GND1
GND2
GND3

89
95

101
108

Data Bus Buffers

CC3

CC4

GND4
GND5
GND6
GND7

1
7

12
18

Bus Control Buffers

CC5

GND8

Codec

CCA

GNDA

Digital Peripherals

CC6

CC7

59
76

GND9
GND10

53
73

Internal logic

CCQ0

CCQ1

33
96

GNDQ0
GNDQ1

104

Phase-Locked Loop (PLL)

CCS

GNDS

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Design Considerations

DSP56156 Data Sheet

MOTOROLA

Power Consumption

= 5.0 V dc ± 10%, T

= -40

to +125

C, C

= 50 pF + 1 TTL Load)

The DC electrical characteristics of this device are shown in Table 27. Power consumption is
application dependant. The data in Table 27 is collected by running the following code using
internal memory after having programmed all pins of port B and C as input and after having
three-stated the data bus (MC = 0 in OMR) and pulled high:

move

#0,r0

move

#0,r3

move

#$100,r2

move

#$00ff,m0

loop

clr

move

x:(r0)+,a

;initial value to accumulator

move

a1,a0

rep

#30

mac

x0,y0,a

x:(r3)+,x0

;mac on typical data

move

a,p:(r2)

;store the mac result

move #0,r3
jmp loop

To minimize the power dissipation, all unused digital input pins should be tied inactive to
ground or power; and all unused I/O pins should be tied inactive through a 10K¾ resistor to
ground or power. When the codec is not used, GNDA should be connected to GND; and V

CCA

should be connected to V

. Also, all codec pins should be left floating, except VREF which

should still be decoupled.

Table 27 DC Electrical Characteristics

Conditions

Symbol

Typical

Unit

MHz

Digital current with Codec and PLL disabled

112

133

Digital current Wait Mode with Codec
and PLL disabled

Digital current Wait Mode with Codec Enabled
and PLL disabled

113

134

Stop mode with PLL and CLKO disabled

250

µA

Digital current drawn by the PLL when active

Digital current drawn by CLKO when active

3.6

Analog current with Codec enabled

CCA

Analog current with Codec disabled

CCA

µA

Power Consumption

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Design Considerations

MOTOROLA

DSP56156 Data Sheet

Host Port
Considerations

Careful synchronization is required when
reading multi-bit registers that are written by
another asynchronous system. This is a com-
mon problem when two asynchronous sys-
tems are connected. The situation exists in
the host interface. The considerations for
proper operation are discussed below.

Host Programming
Considerations

1. Unsynchronized Reading of

Receive Byte Registers

When reading receive byte registers,
RXH or RXL, the host program should
use interrupts or poll the RXDF flag
which indicates that data is available.
This assures that the data in the receive
byte registers will be stable.

2. Overwriting Transmit Byte Registers

The host program should not write to the
transmit byte registers, TXH or TXL, un-
less the TXDE bit is set indicating that the
transmit byte registers are empty. This
guarantees that the transmit byte regis-
ters will transfer valid data to the HRX
register.

3. Synchronization of Status Bits from

DSP to Host

HC, HREQ, DMA, HF3, HF2, TRDY,
TXDE, and RXDF status bits are set or
cleared from inside the DSP and read by
the host processor (refer to DSP56156 Us-
er's Manual, I/O Interface section, Host/
DMA Interface Programming Model for
descriptions of these status bits). The
host can read these status bits very quick-
ly without regard to the clock rate used

by the DSP, but the possibility exists that
the state of the bit could be changing dur-
ing the read operation. This is generally
not a system problem, since the bit will
be read correctly in the next pass of any
host polling routine.

However, if the host asserts HEN for

more than timing number 101 (T101),
with a minimum cycle time of timing
number 103 (T103), then these status bits
are guaranteed to be stable. Care must
be exercised when reading status bits
HF3 and HF2 as an encoded pair. If the
DSP changes HF3 and HF2 from 00 to 11,
there is a small probability that the host
could read the bits during the transition
and receive 01 or 10 instead of 11. If the
combination of HF3 and HF2 has signif-
icance, the host could read the wrong
combination. Therefore, read the bits
twice and check for consensus.

4. Overwriting the Host Vector

The host program should change the
Host Vector register only when the Host
Command bit (HC) is clear. This change
will guarantee that the DSP interrupt
control logic will receive a stable vector.

5. Cancelling a Pending Host Command

Exception

The host processor may elect to clear the
HC bit to cancel the host command ex-
ception request at any time before it is
recognized by the DSP. Because the host
does not know exactly when the excep-
tion will be recognized (due to exception
processing synchronization and pipeline
delays), the DSP may execute the host
command exception after the HC bit is
cleared. For these reasons, the HV bits
must not be changed at the same time
that the HC bit is cleared.

Host Port Considerations

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Design Considerations

DSP56156 Data Sheet

MOTOROLA

DSP Programming
Considerations

1. Synchronization of Status Bits

from Host to DSP

DMA, HF1, HF0, and HCP, HTDE,
and HRDF status bits are set or
cleared by the host processor side of
the interface. These bits are individ-
ually synchronized to the DSP clock.
(Refer to the DSP56156 User's Manual,
I/O Interface section, Host/DMA In-
terface Programming Model for de-
scriptions of these status bits.)

2. Reading HF0 and HF1 as an

Encoded Pair

Care must be exercised when reading
status bits HF0 and HF1 as an encod-
ed pair, i.e., the four combinations 00,
01, 10, and 11 each have significance.
A very small probability exists that
the DSP will read the status bits syn-
chronized during transition. There-
fore, HF0 and HF1 should be read
twice and checked for consensus.

Bus Operation

Figure 43 depicts the operation of the external memory interface with multiple wait states.

Figure 43 Read and Write Bus Operation (3 Wait States)

T2 Tw T2

T2 Tw

Data out

CLKO

A0-A15

PS/DS

R/W

D0-D15

Data in

DSP Programming Considerations

Bus Operation

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Design Considerations

MOTOROLA

DSP56156 Data Sheet

Analog I/O Considerations

Figure 44 describes the recommended analog I/O and power supply configurations. The two
analog inputs are electrically identical. When one is not used, it can be left floating. When
used, an AC coupling capacitor is required. The value of the capacitor along with the input
impedance of the pin determine the cut off frequency of a high pass filter. The input imped-
ance of the MIC and AUX varies as a function of the sigma-delta (²ý) modulator master clock.
78 k

is a typical value at 2 MHz. An AC capacitor of 1µF defines a high pass filter pole of 2

Hz. A smaller capacitor value will move this pole higher in frequency.

Figure 44 Recommended Analog I/O Configuration

modulator

2.0 V

10%

(

±1mA)

MIC

VREF

AUX

Bias

S10

-6 dB

6 dB

MGS1-0 bits

3 POLE
2 ZERO
Low Pass

Filter (LPF)

VC3-VC0

(to microphone)

SPKP

(2/5 V

)

digital V

INS bit

17 dB

VDIV

ð50 nF

600

0.001

600

Bias

0.1

+5 dB

54 K

36 K

S1 K

10 K

6 K

VREF

0.001

CCA

GNDA

0.1

MUX

GNDA

+5 V

220

Analog Decoupling

near DSP

Single trace

External

External Supply

GND

digital GND

Single trace

GNDA

CCA

0.01

SPKM

5.6 K

VREF

GND

Analog I/O Considerations

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Design Considerations

DSP56156 Data Sheet

MOTOROLA

Figure 45 shows three possible single-ended output configurations. Configuration (a) is highly
recommended. For configurations (b) and (c), an AC coupling capacitor is required since the
load resistor is tied to GNDA.

Figure 46 shows a recommended layout for power and ground planes.

Figure 46 Ground and Power planes

S 500

SPKP

SPKM

S 500

47 K¾

VREF

47 K

SPKP

SPKM

SPKP

SPKM

S 500

0 < C ð 100 nF

(a)

(b)

(c)

CCA

GNDA

0 < C ð 100 nF

Figure 45 Single-ended Output Configurations

57 56

112

Analog Ground and
Power planes

Digital Ground and
Power planes

Analog I/O Considerations

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Design Considerations

MOTOROLA

DSP56156 Data Sheet

A four level board is recommended. The top layer (directly under the parts) and the bottom
layer should be interconnect layers. The two center layers should be power and ground.
Ground and power planes should be completely separated. The digital and analog power/
ground planes should not overlap. All codec pins should be over the analog planes. The ana-
log planes should not encompass any digital pins. All codec signal traces should be over the
analog planes.

Figure 47 shows that 0.1

F bypass caps should be located as close to the pins being bypassed

as possible. The ground side of these caps should be connected as close as possible to the V

CCA

pin. The ground side of the bypass cap should be connected to the V

CCA

pin by short traces.

Figure 47 Suggested Top Layer Bypassing

The pins with 0.1

F bypass caps are VREF and GNDA. The largest size practical bypass

caps should also be added for each of these pins as well as for the VDIV pin; 10

F bypass

caps should be considered a minimum value for the larger caps (65

F on VDIV may be

used). These caps should be near the package but do not have to be right next to the pins.

The DAC outputs (SPKP and SPKM) should be run right next to each other as shown on Figure 48.

GNDA

SPKP

PKM

BIAS

AUX

MIC

0.1

S10 µF

VDI

VREF

10 k

Analog I/O Considerations

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Design Considerations

DSP56156 Data Sheet

MOTOROLA

Figure 48 Suggested Bottom Layer Routing

The output should be used differentially if at all possible. Analog signal traces should be
shielded by running traces connected to analog ground next to them. Unused board area on
both interconnect levels should be copper filled and connected to analog ground. The copper
fill is only shown on this page for clarity and simplicity. The ADC input anti-aliasing should
be done with respect to VREF.

Figure 49 presents four options for good power supply connections.

GNDA

CCA

0.25

47 k

Copper Fill of unused board space
should be connected to the analog ground plane.

BIAS

AUX

MIC

VDI

VREF

47 k

1nF

47 k

5.6 k

MIC IN

SPK OUT

Analog I/O Considerations

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Design Considerations

MOTOROLA

DSP56156 Data Sheet

Figure 49 Four Possible Power Supply Connections

GNDA

SPKP

SPKM

CCA

AUX

MIC

VREF

VDIV

Ideal Choice

Two separate power supplies.

Ground planes connected with a single trace as

close as possible to the V

CCA

pin on the codec.

NDA

SPKP

CCA

Second Choice

One power supply.

Two regulators, one for the digital supply, one for

the analog supply. Ground planes connected with

a 10 ¾ resistor as close as possible to the V

CCA

pin on the codec.

Voltage
Regulator

BIAS

AUX

MIC

VREF

VDIV

BIAS

Voltage
Regulator

Third Choice

One power supply.

One regulator for the analog supply. Digital sup-

plies driven directly by voltage source. Ground

planes connected with a 10 ¾ resistor as close as

possible to the V

CCA

the codec.

Fourth Choice

One power supply. Ground

planes connected at source. Ground planes

connected with a 10 ¾ resistor as close as pos-

sible to the V

CCA

pin on the codec.

NDA

SPKP

CCA

AUX

MIC

VREF

VDIV

BIAS

NDA

SPKP

PKM

CCA

AUX

MIC

VREF

VDIV

BIAS

Voltage
Regulator

Analog I/O Considerations

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MOTOROLA

Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume
any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights
of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal
injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and
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attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
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is an Equal Opportunity/Affirmative Action Employer.

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Hong Kong.

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