This document contains information on a new product. Specifications and information herein are subject to change without notice.

IMOTOROLA

DSP56362 Advance Information

Motorola designed the DSP56362 to support digital audio applications requiring digital audio compression

and decompression, sound field processing, acoustic equalization, and other digital audio algorithms. The

DSP56362 uses the high performance, single-clock-per-cycle DSP56300 core family of programmable

CMOS digital signal processors (DSPs) combined with the audio signal processing capability of the

Motorola SymphonyTM DSP family, as shown in

Figure 1

. This design provides a two-fold performance

increase over Motorola's popular Symphony family of DSPs while retaining code compatibility. Significant

architectural enhancements include a barrel shifter, 24-bit addressing, instruction cache, and direct

memory access (DMA). The DSP56362 offers 100 million instructions per second (MIPS) using an internal

100 MHz clock at 3.3 V.

Figure 1 DSP56362 Block Diagram

PLL

OnCE

Clock

Generator

Internal

Data

Bus

Switch

YAB

XAB

PAB

YDB
XDB

PDB

GDB

MODB/IRQB
MODC/IRQC

External

Data Bus

Switch

MODD/IRQD

DSP56300

24-Bit

DDB

DAB

Peripheral

Core

_EB

Expansion Area

SHI

JTAG

RESET

MODA/IRQA

PINIT/NMI

EXTAL

Address

Control

Data

Triple
Timer

Host

Interface

ESAI

Address

Generation

Unit

Six Channel

DMA Unit

Program

Interrupt

Controller

Program

Decode

Controller

Program

Address

Generator

Data ALU

× 24 + 56 56-bit MAC

Two 56-bit Accumulators

56-bit Barrel Shifter

Power

Mngmnt.

DRAM/SRAM

Bus

Interface

I - Cache

Control

External
Address

Bus

Switch

AA0456G

Memory

Expansion

Area

Program RAM/

Instruction

Cache

3072

× 24

Program ROM

30K

× 24

Bootstrap ROM

192

× 24

X Data

RAM

5632

× 24

ROM

6144

× 24

Y Data

RAM

5632

× 24

ROM

6144

× 24

CLKOUT

DAX

(SPDIF)

Technical Data

DSP56362/D
Rev. 3, 02/2004

24-Bit Audio Digital
Signal Processor

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DSP56362 Advance Information

MOTOROLA

FOR TECHNICAL ASSISTANCE:

Telephone:

1-800-521-6274

Email:

dsphelp@dsp.sps.mot.com

Internet:

http://www.motorola-dsp.com

Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR

Used to indicate a signal that is active when pulled low (For example, the RESET
pin is active when low.)

"asserted"

Means that a high true (active high) signal is high or that a low true (active low)
signal is low

"deasserted"

Means that a high true (active high) signal is low or that a low true (active low)
signal is high

Examples:

Signal/Symbol

Logic State

Signal State

Voltage*

True

Asserted

False

Deasserted

True

Asserted

False

Deasserted

Note:

*Values for V

, V

, and V

are defined by individual product specifications.

SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
POWER CONSUMPTION BENCHMARK . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
IBIS MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INDEX-I

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MOTOROLA

DSP56362 Advance Information

OVERVIEW

FEATURES

Multimode, multichannel decoder software functionality

Dolby Digital and Pro Logic

MPEG2 5.1

DTS

Bass management

Digital audio post-processing capabilities

3D Virtual surround sound

Lucasfilm THX5.1

Soundfield processing

Equalization

Digital Signal Processing Core

100 MIPS with a 100 MHz clock at 3.3 V +/- 5%

Object code compatible with the DSP56000 core

Highly parallel instruction set

Data arithmetic logic unit (ALU)

Fully pipelined 24 x 24-bit parallel multiplier-accumulator (MAC)

56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and
parsing)

Conditional ALU instructions

24-bit or 16-bit arithmetic support under software control

Program control unit (PCU)

Position independent code (PIC) support

Addressing modes optimized for DSP applications (including immediate offsets)

On-chip instruction cache controller

On-chip memory-expandable hardware stack

Nested hardware DO loops

Fast auto-return interrupts

Direct memory access (DMA)

Six DMA channels supporting internal and external accesses

One-, two-, and three- dimensional transfers (including circular buffering)

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DSP56362 Advance Information

MOTOROLA

Overview

Features

End-of-block-transfer interrupts

Triggering from interrupt lines and all peripherals

Phase-locked loop (PLL)

Software programmable PLL-based frequency synthesizer for the core clock

Allows change of low-power divide factor (DF) without loss of lock

Output clock with skew elimination

Hardware debugging support

On-Chip Emulation (OnCE`) module

Joint Action Test Group (JTAG) test access port (TAP)

Address trace mode reflects internal program RAM accesses at the external port

On-Chip Memories

Modified Harvard architecture allows simultaneous access to program and data memories

30720 x 24-bit on-chip program ROM

(disabled in 16-bit compatibility mode)

6144 x 24-bit on-chip X-data ROM

6144 x 24-bit on-chip Y-data ROM

Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable

192 x 24-bit bootstrap ROM (disabled in sixteen-bit compatibility mode)

Off-Chip Memory Expansion

Data memory expansion to 256K x 24-bit word memory for P, X, and Y memory using SRAM.

Data memory expansion to 16M x 24-bit word memory for P, X, and Y memory using DRAM.

External memory expansion port( twenty-four data pins for high speed external memory
access allowing for a large number of external accesses per sample)

Chip select logic for glueless interface to SRAMs

On-chip DRAM controller for glueless interface to DRAMs

Peripheral and Support Circuits

Enhanced serial audio interface (ESAI) includes:

Six serial data lines, 4 selectable as receive or transmit and 2 transmit only.

Master or slave capability

S, Sony, AC97, and other audio protocol implementations

1.These ROMs may be factory programmed with data or programs provided by the application developer.

Instruction

Cache

Switch

Mode

Program RAM

Size

Instruction

Cache Size

X Data RAM

Size

Y Data RAM

Size

Disabled

3072

× 24-bit

5632

× 24-bit

5632

× 24-bit

Enabled

Disabled

2048

× 24-bit

1024

× 24-bit

5632

× 24-bit

5632

× 24-bit

Disabled

Enabled

5120

× 24-bit

5632

× 24-bit

3584

× 24-bit

Enabled

4096

× 24-bit

1024

× 24-bit

5632

× 24-bit

3584

× 24-bit

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Overview

Documentation

MOTOROLA

DSP56362 Advance Information

Serial host interface (SHI) features:

SPI protocol with multi-master capability

C protocol with single-master capability

Ten-word receive FIFO

Support for 8-, 16-, and 24-bit words.

Byte-wide parallel host interface (HDI08) with DMA support

DAX features one serial transmitter capable of supporting S/PDIF, IEC958, IEC1937, CP-340,
and AES/EBU digital audio formats; alternate configuration supports up to two GPIO lines

Triple timer module with single external interface or GPIO line

On-chip peripheral registers are memory mapped in data memory space

Reduced Power Dissipation

Very low-power (3.3 V) CMOS design

Wait and stop low-power standby modes

Fully-static logic, operation frequency down to 0 Hz (dc)

Optimized power management circuitry (instruction-dependent, peripheral-dependent, and
mode-dependent)

Package

144-pin plastic thin quad flat pack (LQFP) surface-mount package

DOCUMENTATION

Table 1 lists the documents that provide a complete description of the DSP56362 and are required to
design properly with the part. Documentation is available from a local Motorola distributor, a Motorola
semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home
page on the Internet (the source for the latest information).

Table 1 DSP56362 Documentation

Document Name

Description

Order Number

DSP56300 Family Manual

Detailed description of the 56000-family
architecture and the 24-bit core processor and
instruction set

DSP56300FM/AD

DSP56362 User's Manual

Detailed description of memory, peripherals,
and interfaces

DSP56362UM/AD

DSP56362 Advance Information Electrical and timing specifications; pin and

package descriptions

DSP56362/D

There is also a product brief for this chip.
DSP56362 Product Brief

Brief description of the chip

DSP56362P/D

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MOTOROLA

DSP56362 Advance Information

1-1

SECTION 1

SIGNAL/CONNECTION DESCRIPTIONS

SIGNAL GROUPINGS

The input and output signals of the DSP56362 are organized into functional groups, which are listed in

Table 1-1

and illustrated in

Figure 1-1

The DSP56362 is operated from a 3.3 V supply; however, some of the inputs can tolerate 5 V. A special
notice for this feature is added to the signal descriptions of those inputs.

Table 1-1 DSP56362 Functional Signal Groupings

Functional Group

Number of

Signals

Detailed

Description

Power (V

)

Table 1-2

Ground (GND)

Table 1-3

Clock and PLL

Table 1-4

Address bus

Port A

Table 1-5

Data bus

Table 1-6

Bus control

Table 1-7

Interrupt and mode control

Table 1-8

HDI08

Port B

Table 1-9

SHI

Table 1-10

ESAI

Port C

Table 1-11

Digital audio transmitter (DAX)

Port D

Table 1-12

Timer

Table 1-13

JTAG/OnCE Port

Table 1-14

Port A is the external memory interface port, including the external address bus, data bus, and
control signals.
Port B signals are the GPIO port signals which are multiplexed with the HDI08 signals.
Port C signals are the GPIO port signals which are multiplexed with the ESAI signals.
Port D signals are the GPIO port signals which are multiplexed with the DAX signals.

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1-2

DSP56362 Advance Information

MOTOROLA

Signal/Connection Descriptions

Signal Groupings

Figure 1-1 Signals Identified by Functional Group

DSP56362

External
Address Bus

External
Data Bus

External
Bus
Control

Serial

Host

Interface

(SHI)

Timer 0

PLL

JTAG/

OnCE Port

Power Inputs:
PLL
External I/O
Internal Logic
Address Bus
Data Bus
Bus Control
HDI08
SHI/ESAI/DAX/Timer

A0A17

D0D23

AA0AA3/

RAS0RAS3

CAS

TCK
TDI
TDO
TMS
TRST
DE

CLKOUT

PCAP

PINIT/NMI

CCP

CCQH

CCQL

CCA

CCD

CCC

CCH

CCS

Digital Audio

Transmitter (DAX)

Grounds:
PLL
PLL
Internal Logic
Address Bus
Data Bus
Bus Control
HDI08
SHI/ESAI/DAX/Timer

GNDP

GNDP1

GND

4
4
4

Interrupt/
Mode
Control

MODA/IRQA
MODB/IRQB

MODC/IRQC
MODD/IRQD

RESET

Host

Interface

(HDI08)

Port

Non-
Multiplexed Bus
H0H7
HA0
HA1
HA2
HCS/HCS
Single DS
HRW
HDS/HDS
Single HR
HOREQ/HOREQ
HACK/HACK

ACI
ADO

TIO0

EXTAL

Clock and

Multiplexed
Bus
HAD0HAD7
HAS/HAS
HA8
HA9
HA10
Double DS
HRD/HRD
HWR/HWR
Double HR
HTRQ/HTRQ
HRRQ/HRRQ

Port B
GPIO
PB0PB7
PB8
PB9
PB10
PB13

PB11
PB12

PB14
PB15

Port D GPIO
PD0
PD1

Port C GPIO
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11

Timer GPIO
TIO0

Port A

Notes:

The HDI08 port supports a nonmultiplexed or a multiplexed bus, single or double data strobe (DS), and single or
double host request (HR) configurations. Since each of these modes is configured independently, any
combination of these modes is possible. These HDI08 signals can also be configured alternately as GPIO
signals (PB0PB15). Signals with dual designations (e.g., HAS/HAS) have configurable polarity.

The ESAI signals are multiplexed with the port C GPIO signals (PC0PC11). The DAX signals are multiplexed
with the Port D GPIO signals (PD0PD1). The timer 0 signal can be configured alternately as the timer GPIO
signal (TIO0).

SPI Mode
MOSI
SS
MISO
SCK
HREQ

C Mode

HA0
HA2
SDA
SCL
HREQ

Enhanced

Serial
Audio

Interface

(ESAI)

SCKR
FSR
HCKR
SCKT
FST
HCKT
SDO5/SDI0
SDO4/SDI1
SDO3/SDI2
SDO2/SDI3
SDO1
SDO0

AA0601

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Signal/Connection Descriptions

Power

MOTOROLA

DSP56362 Advance Information

1-3

POWER

Table 1-2 Power Inputs

Power

Name

Description

CCP

PLL Power--V

CCP

is V

dedicated for PLL use. The voltage should be well-

regulated and the input should be provided with an extremely low impedance path
to the V

power rail. There is one V

CCP

input.

CCQL

(4)

Quiet Core (Low) Power--V

CCQL

is an isolated power for the core processing

logic. This input must be tied externally to all other chip power inputs. The user
must provide adequate external decoupling capacitors. There are four V

CCQ

inputs.

CCQH

(3)

Quiet External (High) Power--V

CCQH

is a quiet power source for I/O lines. This

input must be tied externally to all other chip power inputs. The user must provide
adequate decoupling capacitors. There are three V

CCQH

inputs.

CCA

(3)

Address Bus Power--V

CCA

is an isolated power for sections of the address bus I/

O drivers. This input must be tied externally to all other chip power inputs. The user
must provide adequate external decoupling capacitors. There are three V

CCA

inputs.

CCD

(4)

Data Bus Power--V

CCD

is an isolated power for sections of the data bus I/O

drivers. This input must be tied externally to all other chip power inputs. The user
must provide adequate external decoupling capacitors. There are four V

CCD

inputs.

CCC

(2)

Bus Control Power--V

CCC

is an isolated power for the bus control I/O drivers.

This input must be tied externally to all other chip power inputs. The user must
provide adequate external decoupling capacitors. There are two V

CCC

inputs.

CCH

Host Power--V

CCH

is an isolated power for the HDI08 I/O drivers. This input must

be tied externally to all other chip power inputs. The user must provide adequate
external decoupling capacitors. There is one V

CCH

input.

CCS

(2)

SHI, ESAI, DAX, and Timer Power--V

CCS

is an isolated power for the SHI, ESAI,

DAX, and Timer I/O drivers. This input must be tied externally to all other chip
power inputs. The user must provide adequate external decoupling capacitors.
There are two V

CCS

inputs.

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1-4

DSP56362 Advance Information

MOTOROLA

Signal/Connection Descriptions

Ground

GROUND

Table 1-3 Grounds

Ground

Name

Description

GND

PLL Ground--GND

is a ground dedicated for PLL use. The connection should be

provided with an extremely low-impedance path to ground. V

CCP

should be

bypassed to GND

by a 0.47

µF capacitor located as close as possible to the chip

package. There is one GND

connection.

GND

PLL Ground 1--GND

is a ground dedicated for PLL use. The connection should

be provided with an extremely low-impedance path to ground. There is one GND

connection.

GND

(4)

Quiet Ground--GND

is an isolated ground for the internal processing logic. This

connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors. There are four GND

connections.

GND

A (4)

Address Bus Ground--GND

is an isolated ground for sections of the address

bus I/O drivers. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
There are four GND

connections.

GND

(4)

Data Bus Ground--GND

is an isolated ground for sections of the data bus I/O

drivers. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
There are four GND

connections.

GND

(2)

Bus Control Ground--GND

is an isolated ground for the bus control I/O drivers.

This connection must be tied externally to all other chip ground connections. The
user must provide adequate external decoupling capacitors. There are two GND

connections.

GND

Host Ground--GND

is an isolated ground for the HDI08 I/O drivers. This

connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors. There is one GND

connection.

GND

(2)

SHI, ESAI, DAX, and Timer Ground--GND

is an isolated ground for the SHI,

ESAI, DAX, and Timer I/O drivers. This connection must be tied externally to all
other chip ground connections. The user must provide adequate external
decoupling capacitors. There are two GND

connections.

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Signal/Connection Descriptions

Clock and PLL

MOTOROLA

DSP56362 Advance Information

1-5

CLOCK AND PLL

EXTERNAL MEMORY EXPANSION PORT (PORT A)

When the DSP56362 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-
states the relevant port A signals: A0A17, D0D23, AA0/RAS0AA3/RAS3, RD, WR, BB, CAS.

Table 1-4 Clock and PLL Signals

Signal

Name

Type

State during

Reset

Signal Description

EXTAL

Input

External Clock Input--An external clock source must be
connected to EXTAL in order to supply the clock to the
internal clock generator and PLL.
This input cannot tolerate 5V.

CLKOUT

Output

Chip-driven

Clock Output--CLKOUT provides an output clock
synchronized to the internal core clock phase.

If the PLL is enabled and both the multiplication and division
factors equal one, then CLKOUT is also synchronized to
EXTAL.

If the PLL is disabled, the CLKOUT frequency is half the
frequency of EXTAL. CLKOUT is not functional at
frequencies of 100 MHz and above.

PCAP

Input

PLL Capacitor--PCAP is an input connecting an off-chip
capacitor to the PLL filter. Connect one capacitor terminal to
PCAP and the other terminal to V

CCP

If the PLL is not used, PCAP may be tied to V

, GND, or left

floating.

PINIT/
NMI

Input

PLL Initial/Non maskable Interrupt--During assertion of
RESET, the value of PINIT/NMI is written into the PLL Enable
(PEN) bit of the PLL control register, determining whether the
PLL is enabled or disabled. After RESET deassertion and
during normal instruction processing, the PINIT/NMI Schmitt-
trigger input is a negative-edge-triggered non maskable
interrupt (NMI) request internally synchronized to CLKOUT.

PINIT/NMI cannot tolerate 5 V.

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1-6

DSP56362 Advance Information

MOTOROLA

Signal/Connection Descriptions

External Memory Expansion Port (Port A)

External Address Bus

External Data Bus

External Bus Control

Table 1-5 External Address Bus Signals

Signal

Name

Type

State during

Reset

Signal Description

A0A17

Output

Tri-stated

Address Bus--When the DSP is the bus master,
A0A17 are active-high outputs that specify the
address for external program and data memory
accesses. Otherwise, the signals are tri-stated. To
minimize power dissipation, A0A17 do not change
state when external memory spaces are not being
accessed.

Table 1-6 External Data Bus Signals

Signal

Name

Type

State during

Reset

Signal Description

D0D23

Input/Output

Tri-stated

Data Bus--When the DSP is the bus master,
D0D23 are active-high, bidirectional input/
outputs that provide the bidirectional data bus for
external program and data memory accesses.
Otherwise, D0D23 are tri-stated.

Table 1-7 External Bus Control Signals

Signal

Name

Type

State during

Reset

Signal Description

AA0AA3/
RAS0
RAS3

Output

Tri-stated

Address Attribute or Row Address Strobe--When
defined as AA, these signals can be used as chip selects
or additional address lines. When defined as RAS, these
signals can be used as RAS for DRAM interface. These
signals are can be tri-stated outputs with programmable
polarity.

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Signal/Connection Descriptions

External Memory Expansion Port (Port A)

MOTOROLA

DSP56362 Advance Information

1-7

CAS

Output

Tri-stated

Column Address Strobe--When the DSP is the bus
master, CAS is an active-low output used by DRAM to
strobe the column address. Otherwise, if the bus
mastership enable (BME) bit in the DRAM control
register is cleared, the signal is tri-stated.

Output

Tri-stated

Read Enable--When the DSP is the bus master, RD is
an active-low output that is asserted to read external
memory on the data bus (D0D23). Otherwise, RD is tri-
stated.

Output

Tri-stated

Write Enable--When the DSP is the bus master, WR is
an active-low output that is asserted to write external
memory on the data bus (D0D23). Otherwise, the
signals are tri-stated.

Input

Ignored Input

Transfer Acknowledge--If the DSP56362 is the bus
master and there is no external bus activity, or the
DSP56362 is not the bus master, the TA input is ignored.
The TA input is a data transfer acknowledge (DTACK)
function that can extend an external bus cycle
indefinitely. Any number of wait states (1, 2. . .infinity)
may be added to the wait states inserted by the BCR by
keeping TA deasserted. In typical operation, TA is
deasserted at the start of a bus cycle, is asserted to
enable completion of the bus cycle, and is deasserted
before the next bus cycle. The current bus cycle
completes one clock period after TA is asserted
synchronous to CLKOUT. The number of wait states is
determined by the TA input or by the bus control register
(BCR), whichever is longer. The BCR can be used to set
the minimum number of wait states in external bus
cycles.

In order to use the TA functionality, the BCR must be
programmed to at least one wait state. A zero wait state
access cannot be extended by TA deassertion,
otherwise improper operation may result. TA can operate
synchronously or asynchronously, depending on the
setting of the TAS bit in the operating mode register
(OMR).

TA functionality may not be used while performing DRAM
type accesses, otherwise improper operation may result.

Table 1-7 External Bus Control Signals (Continued)

Signal

Name

Type

State during

Reset

Signal Description

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1-8

DSP56362 Advance Information

MOTOROLA

Signal/Connection Descriptions

External Memory Expansion Port (Port A)

Output

Output
(deasserted)

Bus Request--BR is an active-low output, never tri-
stated. BR is asserted when the DSP requests bus
mastership. BR is deasserted when the DSP no longer
needs the bus. BR may be asserted or deasserted
independent of whether the DSP56362 is a bus master
or a bus slave. Bus "parking" allows BR to be deasserted
even though the DSP56362 is the bus master. (See the
description of bus "parking" in the BB signal description.)
The bus request hold (BRH) bit in the BCR allows BR to
be asserted under software control even though the DSP
does not need the bus. BR is typically sent to an external
bus arbitrator that controls the priority, parking, and
tenure of each master on the same external bus. BR is
only affected by DSP requests for the external bus, never
for the internal bus. During hardware reset, BR is
deasserted and the arbitration is reset to the bus slave
state.

Input

Ignored Input

Bus Grant--BG is an active-low input. BG is asserted by
an external bus arbitration circuit when the DSP56362
becomes the next bus master. When BG is asserted, the
DSP56362 must wait until BB is deasserted before taking
bus mastership. When BG is deasserted, bus mastership
is typically given up at the end of the current bus cycle.
This may occur in the middle of an instruction that
requires more than one external bus cycle for execution.

The default mode of operation of this signal requires a
setup and hold time referred to CLKOUT. But CLKOUT
operation is not guaranteed from 100MHz and up, so the
asynchronous bus arbitration must be used for clock
frequencies 100MHz and above. The asynchronous bus
arbitration is enabled by setting the ABE bit in the OMR
register.

Table 1-7 External Bus Control Signals (Continued)

Signal

Name

Type

State during

Reset

Signal Description

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Signal/Connection Descriptions

External Memory Expansion Port (Port A)

MOTOROLA

DSP56362 Advance Information

1-9

Input/
Output

Input

Bus Busy--BB is a bidirectional active-low input/output.
BB indicates that the bus is active. Only after BB is
deasserted can the pending bus master become the bus
master (and then assert the signal again). The bus
master may keep BB asserted after ceasing bus activity
regardless of whether BR is asserted or deasserted. This
is called "bus parking" and allows the current bus master
to reuse the bus without rearbitration until another device
requires the bus. The deassertion of BB is done by an
"active pull-up" method (i.e., BB is driven high and then
released and held high by an external pull-up resistor).

BB requires an external pull-up resistor.

Table 1-7 External Bus Control Signals (Continued)

Signal

Name

Type

State during

Reset

Signal Description

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1-10

DSP56362 Advance Information

MOTOROLA

Signal/Connection Descriptions

Interrupt and Mode Control

INTERRUPT AND MODE CONTROL

The interrupt and mode control signals select the chip's operating mode as it comes out of hardware reset.
After RESET is deasserted, these inputs are hardware interrupt request lines.

Table 1-8 Interrupt and Mode Control

Signal Name

Type

State during

Reset

Signal Description

MODA/IRQA

Input

Mode Select A/External Interrupt Request A--
MODA/IRQA is an active-low Schmitt-trigger input,
internally synchronized to the DSP clock. MODA/IRQA
selects the initial chip operating mode during hardware
reset and becomes a level-sensitive or negative-edge-
triggered, maskable interrupt request input during
normal instruction processing. MODA, MODB, MODC,
and MODD select one of 16 initial chip operating
modes, latched into the OMR when the RESET signal
is deasserted. If IRQA is asserted synchronous to
CLKOUT, multiple processors can be resynchronized
using the WAIT instruction and asserting IRQA to exit
the wait state. If the processor is in the stop standby
state and the MODA/IRQA pin is pulled to GND, the
processor will exit the stop state.

This input is 5 V tolerant.

MODB/IRQB

Input

Mode Select B/External Interrupt Request B--
MODB/IRQB is an active-low Schmitt-trigger input,
internally synchronized to the DSP clock. MODB/IRQB
selects the initial chip operating mode during hardware
reset and becomes a level-sensitive or negative-edge-
triggered, maskable interrupt request input during
normal instruction processing. MODA, MODB, MODC,
and MODD select one of 16 initial chip operating
modes, latched into OMR when the RESET signal is
deasserted. If IRQB is asserted synchronous to
CLKOUT, multiple processors can be re-synchronized
using the WAIT instruction and asserting IRQB to exit
the wait state.

This input is 5 V tolerant.

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Signal/Connection Descriptions

Interrupt and Mode Control

MOTOROLA

DSP56362 Advance Information

1-11

MODC/IRQC

Input

Mode Select C/External Interrupt Request C--
MODC/IRQC is an active-low Schmitt-trigger input,
internally synchronized to the DSP clock. MODC/IRQC
selects the initial chip operating mode during hardware
reset and becomes a level-sensitive or negative-edge-
triggered, maskable interrupt request input during
normal instruction processing. MODA, MODB, MODC,
and MODD select one of 16 initial chip operating
modes, latched into OMR when the RESET signal is
deasserted. If IRQC is asserted synchronous to
CLKOUT, multiple processors can be resynchronized
using the WAIT instruction and asserting IRQC to exit
the wait state.

This input is 5 V tolerant.

MODD/IRQD

Input

Mode Select D/External Interrupt Request D--
MODD/IRQD is an active-low Schmitt-trigger input,
internally synchronized to the DSP clock. MODD/IRQD
selects the initial chip operating mode during hardware
reset and becomes a level-sensitive or negative-edge-
triggered, maskable interrupt request input during
normal instruction processing. MODA, MODB, MODC,
and MODD select one of 16 initial chip operating
modes, latched into OMR when the RESET signal is
deasserted. If IRQD is asserted synchronous to
CLKOUT, multiple processors can be resynchronized
using the WAIT instruction and asserting IRQD to exit
the wait state.

This input is 5 V tolerant.

Table 1-8 Interrupt and Mode Control (Continued)

Signal Name

Type

State during

Reset

Signal Description

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1-12

DSP56362 Advance Information

MOTOROLA

Signal/Connection Descriptions

Host Interface (HDI08)

HOST INTERFACE (HDI08)

The HDI08 provides a fast, 8-bit, parallel data port that may be connected directly to the host bus. The
HDI08 supports a variety of standard buses and can be directly connected to a number of industry
standard microcomputers, microprocessors, DSPs, and DMA hardware.

Host Port Configuration

Signal functions associated with the HDI08 vary according to the interface operating mode as determined
by the HDI08 port control register (HPCR). See 6.5.6 Host Port Control Register (HPCR) on
page Section 6-13 for detailed descriptions of this register and (See Host Interface (HDI08) on
page Section 6-1.) for descriptions of the other HDI08 configuration registers.

RESET

Input

Reset--RESET is an active-low, Schmitt-trigger input.
When asserted, the chip is placed in the reset state
and the internal phase generator is reset. The Schmitt-
trigger input allows a slowly rising input (such as a
capacitor charging) to reset the chip reliably. If RESET
is deasserted synchronous to CLKOUT, exact start-up
timing is guaranteed, allowing multiple processors to
start synchronously and operate together in "lock-
step." When the RESET signal is deasserted, the initial
chip operating mode is latched from the MODA,
MODB, MODC, and MODD inputs. The RESET signal
must be asserted during power up. A stable EXTAL
signal must be supplied while RESET is being
asserted.

This input is 5 V tolerant.

Table 1-8 Interrupt and Mode Control (Continued)

Signal Name

Type

State during

Reset

Signal Description

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Signal/Connection Descriptions

Host Interface (HDI08)

MOTOROLA

DSP56362 Advance Information

1-13

Table 1-9 Host Interface

Signal

Name

Type

State during

Reset

Signal Description

H0H7

HAD0
HAD7

PB0PB7

Input/
output

Input, output,
or
disconnected

GPIO
disconnected

Host Data--When the HDI08 is programmed to
interface a nonmultiplexed host bus and the HI
function is selected, these signals are lines 07
of the bidirectional, tri-state data bus.

Host Address--When HDI08 is programmed to
interface a multiplexed host bus and the HI
function is selected, these signals are lines 07
of the address/data bidirectional, multiplexed, tri-
state bus.

Port B 07--When the HDI08 is configured as
GPIO, these signals are individually
programmable as input, output, or internally
disconnected.

The default state after reset for these signals is
GPIO disconnected.

This input is 5 V tolerant.

HA0

HAS/
HAS

PB8

Input

Input, output,
or
disconnected

GPIO
disconnected

Host Address Input 0--When the HDI08 is
programmed to interface a nonmultiplexed host
bus and the HI function is selected, this signal is
line 0 of the host address input bus.

Host Address Strobe--When HDI08 is
programmed to interface a multiplexed host bus
and the HI function is selected, this signal is the
host address strobe (HAS) Schmitt-trigger input.
The polarity of the address strobe is
programmable, but is configured active-low
(HAS) following reset.

Port B 8--When the HDI08 is configured as
GPIO, this signal is individually programmed as
input, output, or internally disconnected.

The default state after reset for this signal is
GPIO disconnected.

This input is 5 V tolerant.

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1-14

DSP56362 Advance Information

MOTOROLA

Signal/Connection Descriptions

Host Interface (HDI08)

HA1

HA8

PB9

Input

Input, output,
or
disconnected

GPIO
disconnected

Host Address Input 1--When the HDI08 is
programmed to interface a nonmultiplexed host
bus and the HI function is selected, this signal is
line 1 of the host address (HA1) input bus.

Host Address 8--When HDI08 is programmed
to interface a multiplexed host bus and the HI
function is selected, this signal is line 8 of the
host address (HA8) input bus.

Port B 9--When the HDI08 is configured as
GPIO, this signal is individually programmed as
input, output, or internally disconnected.

The default state after reset for this signal is
GPIO disconnected.

This input is 5 V tolerant.

HA2

HA9

PB10

Input

Input, Output,
or
Disconnected

GPIO
disconnected

Host Address Input 2--When the HDI08 is
programmed to interface a non-multiplexed host
bus and the HI function is selected, this signal is
line 2 of the host address (HA2) input bus.

Host Address 9--When HDI08 is programmed
to interface a multiplexed host bus and the HI
function is selected, this signal is line 9 of the
host address (HA9) input bus.

Port B 10--When the HDI08 is configured as
GPIO, this signal is individually programmed as
input, output, or internally disconnected.

The default state after reset for this signal is
GPIO disconnected.

This input is 5 V tolerant.

Table 1-9 Host Interface (Continued)

Signal

Name

Type

State during

Reset

Signal Description

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Signal/Connection Descriptions

Host Interface (HDI08)

MOTOROLA

DSP56362 Advance Information

1-15

HRW

HRD/
HRD

PB11

Input

Input, Output,
or
Disconnected

GPIO
disconnected

Host Read/Write--When HDI08 is programmed
to interface a single-data-strobe host bus and the
HI function is selected, this signal is the Host
Read/Write (HRW) input.

Host Read Data--When HDI08 is programmed
to interface a double-data-strobe host bus and
the HI function is selected, this signal is the host
read data strobe (HRD) Schmitt-trigger input. The
polarity of the data strobe is programmable, but is
configured as active-low (HRD) after reset.

Port B 11--When the HDI08 is configured as
GPIO, this signal is individually programmed as
input, output, or internally disconnected.

The default state after reset for this signal is
GPIO disconnected.

This input is 5 V tolerant.

HDS/
HDS

HWR/
HWR

PB12

Input

Input, output,
or
disconnected

GPIO
disconnected

Host Data Strobe--When HDI08 is programmed
to interface a single-data-strobe host bus and the
HI function is selected, this signal is the host data
strobe (HDS) Schmitt-trigger input. The polarity
of the data strobe is programmable, but is
configured as active-low (HDS) following reset.

Host Write Data--When HDI08 is programmed
to interface a double-data-strobe host bus and
the HI function is selected, this signal is the host
write data strobe (HWR) Schmitt-trigger input.
The polarity of the data strobe is programmable,
but is configured as active-low (HWR) following
reset.

Port B 12--When the HDI08 is configured as
GPIO, this signal is individually programmed as
input, output, or internally disconnected.

The default state after reset for this signal is
GPIO disconnected.

This input is 5 V tolerant.

Table 1-9 Host Interface (Continued)

Signal

Name

Type

State during

Reset

Signal Description

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1-16

DSP56362 Advance Information

MOTOROLA

Signal/Connection Descriptions

Host Interface (HDI08)

HCS

HA10

PB13

Input

Input, output,
or
disconnected

GPIO
disconnected

Host Chip Select--When HDI08 is programmed
to interface a nonmultiplexed host bus and the HI
function is selected, this signal is the host chip
select (HCS) input. The polarity of the chip select
is programmable, but is configured active-low
(HCS) after reset.

Host Address 10--When HDI08 is programmed
to interface a multiplexed host bus and the HI
function is selected, this signal is line 10 of the
host address (HA10) input bus.

Port B 13--When the HDI08 is configured as
GPIO, this signal is individually programmed as
input, output, or internally disconnected.

The default state after reset for this signal is
GPIO disconnected.

This input is 5 V tolerant.

HOREQ/
HOREQ

HTRQ/
HTRQ

PB14

Output

Input, output,
or
disconnected

GPIO
disconnected

Host Request--When HDI08 is programmed to
interface a single host request host bus and the
HI function is selected, this signal is the host
request (HOREQ) output. The polarity of the host
request is programmable, but is configured as
active-low (HOREQ) following reset. The host
request may be programmed as a driven or
open-drain output.

Transmit Host Request--When HDI08 is
programmed to interface a double host request
host bus and the HI function is selected, this
signal is the transmit host request (HTRQ)
output. The polarity of the host request is
programmable, but is configured as active-low
(HTRQ) following reset. The host request may be
programmed as a driven or open-drain output.

Port B 14--When the HDI08 is configured as
GPIO, this signal is individually programmed as
input, output, or internally disconnected.

The default state after reset for this signal is
GPIO disconnected.

This input is 5 V tolerant.

Table 1-9 Host Interface (Continued)

Signal

Name

Type

State during

Reset

Signal Description

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Signal/Connection Descriptions

Host Interface (HDI08)

MOTOROLA

DSP56362 Advance Information

1-17

HACK/
HACK

HRRQ/
HRRQ

PB15

Input

Output

Input, output,
or
disconnected

GPIO
disconnected

Host Acknowledge--When HDI08 is
programmed to interface a single host request
host bus and the HI function is selected, this
signal is the host acknowledge (HACK) Schmitt-
trigger input. The polarity of the host
acknowledge is programmable, but is configured
as active-low (HACK) after reset.

Receive Host Request--When HDI08 is
programmed to interface a double host request
host bus and the HI function is selected, this
signal is the receive host request (HRRQ) output.
The polarity of the host request is programmable,
but is configured as active-low (HRRQ) after
reset. The host request may be programmed as a
driven or open-drain output.

Port B 15--When the HDI08 is configured as
GPIO, this signal is individually programmed as
input, output, or internally disconnected.

The default state after reset for this signal is
GPIO disconnected.

This input is 5 V tolerant.

Table 1-9 Host Interface (Continued)

Signal

Name

Type

State during

Reset

Signal Description

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1-18

DSP56362 Advance Information

MOTOROLA

Signal/Connection Descriptions

Serial Host Interface

SERIAL HOST INTERFACE

The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I

C mode.

Table 1-10 Serial Host Interface Signals

Signal Name

Signal Type

State

during

Reset

Signal Description

SCK

SCL

Input or
output

Tri-stated

SPI Serial Clock--The SCK signal is an output
when the SPI is configured as a master and a
Schmitt-trigger input when the SPI is configured as
a slave. When the SPI is configured as a master,
the SCK signal is derived from the internal SHI
clock generator. When the SPI is configured as a
slave, the SCK signal is an input, and the clock
signal from the external master synchronizes the
data transfer. The SCK signal is ignored by the SPI
if it is defined as a slave and the slave select (SS)
signal is not asserted. In both the master and slave
SPI devices, data is shifted on one edge of the SCK
signal and is sampled on the opposite edge where
data is stable. Edge polarity is determined by the
SPI transfer protocol.

C Serial Clock--SCL carries the clock for I

C bus

transactions in the I

C mode. SCL is a Schmitt-

trigger input when configured as a slave and an
open-drain output when configured as a master.
SCL should be connected to V

through a pull-up

resistor.

This signal is tri-stated during hardware, software,
and individual reset. Thus, there is no need for an
external pull-up in this state.

This input is 5 V tolerant.

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Signal/Connection Descriptions

Serial Host Interface

MOTOROLA

DSP56362 Advance Information

1-19

MISO

SDA

Input or
output

Input or
open-drain
output

Tri-stated

SPI Master-In-Slave-Out--When the SPI is
configured as a master, MISO is the master data
input line. The MISO signal is used in conjunction
with the MOSI signal for transmitting and receiving
serial data. This signal is a Schmitt-trigger input
when configured for the SPI Master mode, an
output when configured for the SPI Slave mode,
and tri-stated if configured for the SPI Slave mode
when SS is deasserted. An external pull-up resistor
is not required for SPI operation.

C Data and Acknowledge--In I

C mode, SDA is

a Schmitt-trigger input when receiving and an open-
drain output when transmitting. SDA should be
connected to V

through a pull-up resistor. SDA

carries the data for I

C transactions. The data in

SDA must be stable during the high period of SCL.
The data in SDA is only allowed to change when
SCL is low. When the bus is free, SDA is high. The
SDA line is only allowed to change during the time
SCL is high in the case of start and stop events. A
high-to-low transition of the SDA line while SCL is
high is a unique situation, and is defined as the start
event. A low-to-high transition of SDA while SCL is
high is a unique situation defined as the stop event.

This signal is tri-stated during hardware, software,
and individual reset. Thus, there is no need for an
external pull-up in this state.

This input is 5 V tolerant.

Table 1-10 Serial Host Interface Signals (Continued)

Signal Name

Signal Type

State

during

Reset

Signal Description

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1-20

DSP56362 Advance Information

MOTOROLA

Signal/Connection Descriptions

Serial Host Interface

MOSI

HA0

Input or
output

Input

Tri-stated

SPI Master-Out-Slave-In--When the SPI is
configured as a master, MOSI is the master data
output line. The MOSI signal is used in conjunction
with the MISO signal for transmitting and receiving
serial data. MOSI is the slave data input line when
the SPI is configured as a slave. This signal is a
Schmitt-trigger input when configured for the SPI
Slave mode.

C Slave Address 0--This signal uses a Schmitt-

trigger input when configured for the I

C mode.

When configured for I

C slave mode, the HA0

signal is used to form the slave device address.
HA0 is ignored when configured for the I

C master

mode.

This signal is tri-stated during hardware, software,
and individual reset. Thus, there is no need for an
external pull-up in this state.

This input is 5 V tolerant.

HA2

Input

Tri-stated

SPI Slave Select--This signal is an active low
Schmitt-trigger input when configured for the SPI
mode. When configured for the SPI Slave mode,
this signal is used to enable the SPI slave for
transfer. When configured for the SPI master mode,
this signal should be kept deasserted (pulled high).
If it is asserted while configured as SPI master, a
bus error condition is flagged. If SS is deasserted,
the SHI ignores SCK clocks and keeps the MISO
output signal in the high-impedance state.

C Slave Address 2--This signal uses a Schmitt-

trigger input when configured for the I

C mode.

When configured for the I

C Slave mode, the HA2

signal is used to form the slave device address.
HA2 is ignored in the I

C master mode.

This signal is tri-stated during hardware, software,
and individual reset. Thus, there is no need for an
external pull-up in this state.

This input is 5 V tolerant.

Table 1-10 Serial Host Interface Signals (Continued)

Signal Name

Signal Type

State

during

Reset

Signal Description

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Signal/Connection Descriptions

Serial Host Interface

MOTOROLA

DSP56362 Advance Information

1-21

HREQ

Input or
Output

Tri-stated

Host Request--This signal is an active low
Schmitt-trigger input when configured for the
master mode but an active low output when
configured for the slave mode.

When configured for the slave mode, HREQ is
asserted to indicate that the SHI is ready for the
next data word transfer and deasserted at the first
clock pulse of the new data word transfer. When
configured for the master mode, HREQ is an input.
When asserted by the external slave device, it will
trigger the start of the data word transfer by the
master. After finishing the data word transfer, the
master will await the next assertion of HREQ to
proceed to the next transfer.

This signal is tri-stated during hardware, software,
personal reset, or when the HREQ1HREQ0 bits in
the HCSR are cleared. There is no need for
external pull-up in this state.

This input is 5 V tolerant.

Table 1-10 Serial Host Interface Signals (Continued)

Signal Name

Signal Type

State

during

Reset

Signal Description

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1-22

DSP56362 Advance Information

MOTOROLA

Signal/Connection Descriptions

Enhanced Serial Audio Interface

ENHANCED SERIAL AUDIO INTERFACE

Table 1-11 Enhanced Serial Audio Interface Signals

Signal

Name

Signal Type

State during

Reset

Signal Description

HCKR

PC2

Input or output

Input, output,
or
disconnected

GPIO
disconnected

High Frequency Clock for Receiver--When
programmed as an input, this signal provides a high
frequency clock source for the ESAI receiver as an
alternate to the DSP core clock. When programmed
as an output, this signal can serve as a high-
frequency sample clock (e.g., for external digital to
analog converters [DACs]) or as an additional
system clock.

Port C 2--When the ESAI is configured as GPIO,
this signal is individually programmable as input,
output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

HCKT

PC5

Input or output

Input, output,
or
disconnected

GPIO
disconnected

High Frequency Clock for Transmitter--When
programmed as an input, this signal provides a high
frequency clock source for the ESAI transmitter as
an alternate to the DSP core clock. When
programmed as an output, this signal can serve as a
high frequency sample clock (e.g., for external
DACs) or as an additional system clock.

Port C 5--When the ESAI is configured as GPIO,
this signal is individually programmable as input,
output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

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Signal/Connection Descriptions

Enhanced Serial Audio Interface

MOTOROLA

DSP56362 Advance Information

1-23

FSR

PC1

Input or output

Input, output,
or
disconnected

GPIO
disconnected

Frame Sync for Receiver--This is the receiver
frame sync input/output signal. In the asynchronous
mode (SYN=0), the FSR pin operates as the frame
sync input or output used by all the enabled
receivers. In the synchronous mode (SYN=1), it
operates as either the serial flag 1 pin (TEBE=0), or
as the transmitter external buffer enable control
(TEBE=1, RFSD=1).

When this pin is configured as serial flag pin, its
direction is determined by the RFSD bit in the RCCR
register. When configured as the output flag OF1,
this pin will reflect the value of the OF1 bit in the
SAICR register, and the data in the OF1 bit will show
up at the pin synchronized to the frame sync in
normal mode or the slot in network mode. When
configured as the input flag IF1, the data value at the
pin will be stored in the IF1 bit in the SAISR register,
synchronized by the frame sync in normal mode or
the slot in network mode.

Port C 1--When the ESAI is configured as GPIO,
this signal is individually programmable as input,
output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

FST

PC4

Input or output

Input, output,
or
disconnected

GPIO
disconnected

Frame Sync for Transmitter--This is the
transmitter frame sync input/output signal. For
synchronous mode, this signal is the frame sync for
both transmitters and receivers. For asynchronous
mode, FST is the frame sync for the transmitters
only. The direction is determined by the transmitter
frame sync direction (TFSD) bit in the ESAI transmit
clock control register (TCCR).

Port C 4--When the ESAI is configured as GPIO,
this signal is individually programmable as input,
output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

Table 1-11 Enhanced Serial Audio Interface Signals (Continued)

Signal

Name

Signal Type

State during

Reset

Signal Description

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1-24

DSP56362 Advance Information

MOTOROLA

Signal/Connection Descriptions

Enhanced Serial Audio Interface

SCKR

PC0

Input or output

Input, output,
or
disconnected

GPIO
disconnected

Receiver Serial Clock--SCKR provides the
receiver serial bit clock for the ESAI. The SCKR
operates as a clock input or output used by all the
enabled receivers in the asynchronous mode
(SYN=0), or as serial flag 0 pin in the synchronous
mode (SYN=1).

When this pin is configured as serial flag pin, its
direction is determined by the RCKD bit in the
RCCR register. When configured as the output flag
OF0, this pin will reflect the value of the OF0 bit in
the SAICR register, and the data in the OF0 bit will
show up at the pin synchronized to the frame sync in
normal mode or the slot in network mode. When
configured as the input flag IF0, the data value at the
pin will be stored in the IF0 bit in the SAISR register,
synchronized by the frame sync in normal mode or
the slot in network mode.

Port C 0--When the ESAI is configured as GPIO,
this signal is individually programmable as input,
output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

SCKT

PC3

Input or output

Input, output,
or
disconnected

GPIO
disconnected

Transmitter Serial Clock--This signal provides the
serial bit rate clock for the ESAI. SCKT is a clock
input or output used by all enabled transmitters and
receivers in synchronous mode, or by all enabled
transmitters in asynchronous mode.

Port C 3--When the ESAI is configured as GPIO,
this signal is individually programmable as input,
output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

Table 1-11 Enhanced Serial Audio Interface Signals (Continued)

Signal

Name

Signal Type

State during

Reset

Signal Description

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Signal/Connection Descriptions

Enhanced Serial Audio Interface

MOTOROLA

DSP56362 Advance Information

1-25

SDO5

SDI0

PC6

Output

Input

Input, output,
or
disconnected

GPIO
disconnected

Serial Data Output 5--When programmed as a
transmitter, SDO5 is used to transmit data from the
TX5 serial transmit shift register.

Serial Data Input 0--When programmed as a
receiver, SDI0 is used to receive serial data into the
RX0 serial receive shift register.

Port C 6--When the ESAI is configured as GPIO,
this signal is individually programmable as input,
output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

SDO4

SDI1

PC7

Output

Input

Input, output,
or
disconnected

GPIO
disconnected

Serial Data Output 4--When programmed as a
transmitter, SDO4 is used to transmit data from the
TX4 serial transmit shift register.

Serial Data Input 1--When programmed as a
receiver, SDI1 is used to receive serial data into the
RX1 serial receive shift register.

Port C 7--When the ESAI is configured as GPIO,
this signal is individually programmable as input,
output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

Table 1-11 Enhanced Serial Audio Interface Signals (Continued)

Signal

Name

Signal Type

State during

Reset

Signal Description

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1-26

DSP56362 Advance Information

MOTOROLA

Signal/Connection Descriptions

Enhanced Serial Audio Interface

SDO3

SDI2

PC8

Output

Input

Input, output,
or
disconnected

GPIO
disconnected

Serial Data Output 3--When programmed as a
transmitter, SDO3 is used to transmit data from the
TX3 serial transmit shift register.

Serial Data Input 2--When programmed as a
receiver, SDI2 is used to receive serial data into the
RX2 serial receive shift register.

Port C 8--When the ESAI is configured as GPIO,
this signal is individually programmable as input,
output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

SDO2

SDI3

PC9

Output

Input

Input, output,
or
disconnected

GPIO
disconnected

Serial Data Output 2--When programmed as a
transmitter, SDO2 is used to transmit data from the
TX2 serial transmit shift register.

Serial Data Input 3--When programmed as a
receiver, SDI3 is used to receive serial data into the
RX3 serial receive shift register.

Port C 9--When the ESAI is configured as GPIO,
this signal is individually programmable as input,
output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

SDO1

PC10

Output

Input, output,
or
disconnected

GPIO
disconnected

Serial Data Output 1--SDO1 is used to transmit
data from the TX1 serial transmit shift register.

Port C 10--When the ESAI is configured as GPIO,
this signal is individually programmable as input,
output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

Table 1-11 Enhanced Serial Audio Interface Signals (Continued)

Signal

Name

Signal Type

State during

Reset

Signal Description

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Signal/Connection Descriptions

Enhanced Serial Audio Interface

MOTOROLA

DSP56362 Advance Information

1-27

SDO0

PC11

Output

Input, output,
or
disconnected

GPIO
disconnected

Serial Data Output 0--SDO0 is used to transmit
data from the TX0 serial transmit shift register.

Port C 11--When the ESAI is configured as GPIO,
this signal is individually programmable as input,
output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

Table 1-11 Enhanced Serial Audio Interface Signals (Continued)

Signal

Name

Signal Type

State during

Reset

Signal Description

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1-28

DSP56362 Advance Information

MOTOROLA

Signal/Connection Descriptions

Digital Audio Interface (DAX)

DIGITAL AUDIO INTERFACE (DAX)

Table 1-12 Digital Audio Interface (DAX) Signals

Signal

Name

Type

State During

Reset

Signal Description

ACI

PD0

Input

Input,
output, or
disconnected

Disconnecte
d

Audio Clock Input--This is the DAX clock input. When
programmed to use an external clock, this input supplies
the DAX clock. The external clock frequency must be
256, 384, or 512 times the audio sampling frequency
(256

× Fs, 384 × Fs or 512 × Fs, respectively).

Port D 0--When the DAX is configured as GPIO, this
signal is individually programmable as input, output, or
internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

ADO

PD1

Output

Input,
output, or
disconnected

Disconnecte
d

Digital Audio Data Output--This signal is an audio and
non-audio output in the form of AES/EBU, CP340 and
IEC958 data in a biphase mark format.

Port D 1--When the DAX is configured as GPIO, this
signal is individually programmable as input, output, or
internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

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Signal/Connection Descriptions

Timer

MOTOROLA

DSP56362 Advance Information

1-29

TIMER

JTAG/OnCE INTERFACE

Table 1-13 Timer Signal

Signal Name

Type

State during

Reset

Signal Description

TIO0

Input or
Output

Input

Timer 0 Schmitt-Trigger Input/Output--When
timer 0 functions as an external event counter or
in measurement mode, TIO0 is used as input.
When timer 0 functions in watchdog, timer, or
pulse modulation mode, TIO0 is used as output.

The default mode after reset is GPIO input. This
can be changed to output or configured as a
timer input/output through the timer 0 control/
status register (TCSR0). If TIO0 is not being
used, it is recommended to either define it as
GPIO output immediately at the beginning of
operation or leave it defined as GPIO input but
connected it to Vcc through a pull-up resistor in
order to ensure a stable logic level at the input.

This input is 5 V tolerant.

Table 1-14 JTAG/OnCETM Interface

Signal

Name

Type

State

during

Reset

Signal Description

TCK

Input

Test Clock--TCK is a test clock input signal used to synchronize
the JTAG test logic. It has an internal pull-up resistor.

This input is 5 V tolerant.

TDI

Input

Test Data Input--TDI is a test data serial input signal used for test
instructions and data. TDI is sampled on the rising edge of TCK
and has an internal pull-up resistor.

This input is 5 V tolerant.

TDO

Output

Tri-
stated

Test Data Output--TDO is a test data serial output signal used for
test instructions and data. TDO can be tri-stated and is actively
driven in the shift-IR and shift-DR controller states. TDO changes
on the falling edge of TCK.

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1-30

DSP56362 Advance Information

MOTOROLA

Signal/Connection Descriptions

JTAG/OnCE Interface

TMS

Input

Test Mode Select--TMS is an input signal used to sequence the
test controller's state machine. TMS is sampled on the rising edge
of TCK and has an internal pull-up resistor.

This input is 5 V tolerant.

TRST

Input

Test Reset--TRST is an active-low Schmitt-trigger input signal
used to asynchronously initialize the test controller. TRST has an
internal pull-up resistor.

The use of TRST is not recommended for new designs. It is
recommended to leave TRST disconnected.

This input is 5 V tolerant.

Input/
Output

Input

Debug Event--DE is an open-drain, bidirectional, active-low signal
providing, as an input, a means of entering the debug mode of
operation from an external command controller, and, as an output,
a means of acknowledging that the chip has entered the debug
mode. This signal, when asserted as an input, causes the
DSP56300 core to finish the current instruction being executed,
save the instruction pipeline information, enter the debug mode,
and wait for commands to be entered from the debug serial input
line. This signal is asserted as an output for three clock cycles
when the chip enters the debug mode as a result of a debug
request or as a result of meeting a breakpoint condition. The DE
has an internal pull-up resistor.

This is not a standard part of the JTAG TAP controller. The signal
connects directly to the OnCE module to initiate debug mode
directly or to provide a direct external indication that the chip has
entered the debug mode. All other interface with the OnCE module
must occur through the JTAG port.

The use of DE is not recommended for new designs. It is
recommended to leave DE disconnected.

This input is not 5 V tolerant.

Table 1-14 JTAG/OnCETM Interface (Continued)

Signal

Name

Type

State

during

Reset

Signal Description

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MOTOROLA

DSP56362 Advance Information

2-1

SECTION 2

SPECIFICATIONS

INTRODUCTION

The DSP56362 is fabricated in high density CMOS with Transistor-Transistor Logic (TTL) compatible
inputs and outputs. The DSP56362 specifications are preliminary and are from design simulations, and
may not be fully tested or guaranteed. Finalized specifications will be published after full characterization
and device qualifications are complete.

MAXIMUM RATINGS

Note: In the calculation of timing requirements, adding a maximum value of one

specification to a minimum value of another specification does not yield a reasonable
sum. A maximum specification is calculated using a worst case variation of process
parameter values in one direction. The minimum specification is calculated using the
worst case for the same parameters in the opposite direction. Therefore, a "maximum"
value for a specification will never occur in the same device that has a "minimum"
value for another specification; adding a maximum to a minimum represents a
condition that can never exist.

CAUTION

This device contains circuitry protecting
against damage due to high static voltage or
electrical fields. However, normal precautions
should be taken to avoid exceeding maximum
voltage ratings. Reliability of operation is
enhanced if unused inputs are pulled to an
appropriate logic voltage level (e.g., either
GND or V

). The suggested value for a

pullup or pulldown resistor is 10 k

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2-2

DSP56362 Advance Information

MOTOROLA

Specifications

Thermal Characteristics

THERMAL CHARACTERISTICS

Table 2-1 Maximum Ratings

Rating

Symbol

Value

1, 2

Unit

Supply Voltage

0.3 to +4.0

All input voltages excluding "5 V tolerant" inputs

GND

0.3 to V

+ 0.3

All "5 V tolerant" input voltages

IN5

GND

0.3 to V

+ 3.95

Current drain per pin excluding V

and GND

Operating temperature range

40 to +105

°C

Storage temperature

STG

55 to +125

°C

Notes:

GND = 0 V, V

= 3.3 V

± .16V, T

= 0°C to +100°C, CL = 50 pF

Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not
guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent
damage to the device.

CAUTION: All "5 V Tolerant" input voltages must not be more than 3.95 V greater than the supply
voltage; this restriction applies to "power on", as well as during normal operation. In any case, the input
voltages cannot be more than 5.75 V. "5 V Tolerant" inputs are inputs that tolerate 5 V.

Table 2-2 Thermal Characteristics

Characteristic

Symbol

LQFP Value

Unit

Junction-to-ambient thermal resistance

45.3

°C/W

Junction-to-case thermal resistance

10.1

°C/W

Thermal characterization parameter

5.5

°C/W

Notes: 1.

Junction-to-ambient thermal resistance is based on measurements on a horizontal single-
sided printed circuit board per SEMI G38-87 in natural convection.(SEMI is Semiconductor
Equipment and Materials International, 805 East Middlefield Rd., Mountain View, CA 94043,
(415) 964-5111.)
Measurements were done with parts mounted on thermal test boards conforming to
specification EIA/JESD51-3.

Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI
G30-88, with the exception that the cold plate temperature is used for the case temperature.

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Specifications

DC Electrical Characteristics

MOTOROLA

DSP56362 Advance Information

2-3

DC ELECTRICAL CHARACTERISTICS

Table 2-3 DC Electrical Characteristics

Characteristics

Symbol

Min

Typ

Max

Unit

Supply voltage

3.14

3.3

3.46

Input high voltage

· D(0:23), BG, BB, TA, DE, and PINIT/

NMI

2.0

· MOD

/IRQ

, RESET, and TCK/TDI/

TMS/TRST/ESAI/Timer/HDI08/
SHI

(SPI mode)

pins

IHP

2.0

+ 3.95

· SHI

(I2C mode)

pins

1.5

CC + 3.95

· EXTAL

IHX

0.8

Input low voltage

· D(0:23), BG, BB, TA, MOD

/IRQ

RESET, PINIT/NMI

0.3

0.8

· All JTAG/ESAI/Timer/HDI08/ SHI

(SPI

mode)

pins

ILP

0.3

0.8

· SHI

(I2C mode)

pins

0.3

× V

· EXTAL

ILX

0.3

0.2

Input leakage current

µA

High impedance (off-state) input current
(@ 2.4 V / 0.4 V)

TSI

µA

Output high voltage
· TTL (I

= 0.4 mA)

5,7

2.4

· CMOS (I

= 10

µA)

0.01

Output low voltage
· TTL (I

= 3.0 mA, open-drain pins

= 6.7 mA)

5,7

0.4

· CMOS (I

= 10

µA)

0.01

Internal supply current

(Operating frequency 100MHz for
current measurements)

· In Normal mode

CCI

127

181

· In Wait mode

CCW

7. 5

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2-4

DSP56362 Advance Information

MOTOROLA

Specifications

AC Electrical Characteristics

AC ELECTRICAL CHARACTERISTICS

The timing waveforms shown in the AC electrical characteristics section are tested with a V

maximum of

0.3 V and a V

minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown

in Note 6 of the previous table. AC timing specifications, which are referenced to a device input signal, are
measured in production with respect to the 50% point of the respective input signal's transition. DSP56362
output levels are measured with the production test machine V

and V

reference levels set at 0.4 V

and 2.4 V, respectively.

Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test

conditions are 15 MHz and rated speed.

· In Stop mode

CCS

100

150

µA

PLL supply current

2.5

Input capacitance

Notes: 1.

Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC, and MODD/IRQD pins

Power Consumption Considerations on page 4-3

provides a formula to compute the

estimated current requirements in Normal mode. In order to obtain these results, all inputs must be
terminated (i.e., not allowed to float). Measurements are based on synthetic intensive DSP
benchmarks. The power consumption numbers in this specification are 90% of the measured
results of this benchmark. This reflects typical DSP applications. Typical internal supply current is
measured with V

= 3.3V at T

= 100°C. Maximum internal supply current is measured with V

3.46 V at T

= 100°C.

Deleted.

In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be
terminated (i.e., not allowed to float).

Periodically sampled and not 100% tested

= 3.3 V

± 5% V; T

= 0°C to +100°C, C

= 50 pF

This characteristic does not apply to PCAP.

Driving EXTAL to the low V

IHX

or the high V

ILX

value may cause additional power consumption (DC

current). To minimize power consumption, the minimum V

IHX

should be no lower than

0.9

and the maximum V

ILX

should be no higher than 0.1

Table 2-3 DC Electrical Characteristics

(Continued)

Characteristics

Symbol

Min

Typ

Max

Unit

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Specifications

Internal Clocks

MOTOROLA

DSP56362 Advance Information

2-5

INTERNAL CLOCKS

Table 2-4 Internal Clocks, CLKOUT

Characteristics

Symbol

Expression

1, 2

Min

Typ

Max

Internal operation frequency and
CLKOUT with PLL enabled

(Ef

× MF)/

(PDF

× DF)

Internal operation frequency and
CLKOUT with PLL disabled

Ef/2

Internal clock and CLKOUT high
period

· With PLL disabled

· With PLL enabled and

0.49

× ET

PDF

× DF/MF

0.51

× ET

PDF

× DF/MF

· With PLL enabled and

MF > 4

0.47

× ET

PDF

× DF/MF

0.53

× ET

PDF

× DF/MF

Internal clock and CLKOUT low
period

· With PLL disabled

· With PLL enabled and

0.49

× ET

PDF

× DF/MF

0.51

× ET

PDF

× DF/MF

· With PLL enabled and

MF > 4

0.47

× ET

PDF

× DF/MF

0.53

× ET

PDF

× DF/MF

Internal clock and CLKOUT cycle
time with PLL enabled

× PDF ×

DF/MF

Internal clock and CLKOUT cycle
time with PLL disabled

× ET

Instruction cycle time

CYC

Notes: 1.

DF = Division Factor
Ef = External frequency
ET

= External clock cycle

MF = Multiplication Factor
PDF = Predivision Factor
T

= internal clock cycle

See the PLL and Clock Generation section in the DSP56300 Family Manual for a detailed discussion
of the PLL.

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2-6

DSP56362 Advance Information

MOTOROLA

Specifications

EXTERNAL CLOCK OPERATION

The DSP56362 system clock is an externally supplied square wave voltage source connected to
EXTAL(

Figure 2-1

)

Figure 2-1 E

xternal Clock Timing

Table 2-5 Clock Operation 100 and 120 MHz Values

No.

Characteristics

Symbol

100 MHz

120 MHz

Min

Max

Min

Max

Frequency of EXTAL (EXTAL Pin
Frequency)
The rise and fall time of this external clock
should be 3 ns maximum.

100.0

120.0

EXTAL input high

1, 2

· With PLL disabled (46.7%53.3% duty

cycle

)

4.67 ns

0.00 ns

· With PLL enabled (42.5%57.5% duty

cycle

)

4.25 ns 157.0

µs 0.00 ns 157.0 µs

EXTAL input low

1, 2

· With PLL disabled (46.7%53.3% duty

cycle

)

4.67 ns

EXTAL

ILC

IHC

Midpoint

Note:

The midpoint is 0.5 (V

IHC

+ V

ILC

ETH

ETL

ETC

CLKOUT With

PLL Disabled

CLKOUT With

PLL Enabled

AA0459

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Specifications

EXTERNAL CLOCK OPERATION

MOTOROLA

DSP56362 Advance Information

2-7

· With PLL enabled (42.5%57.5% duty

cycle

)

4.25 ns 157.0

µs 4.25 ns 1570.00

EXTAL cycle time

· With PLL disabled

10.00 ns

8.33 ns

· With PLL enabled

10.00 ns 273.1

µs 8.33 ns 273.1 µs

CLKOUT change from EXTAL fall with PLL
disabled

4.3 ns

11.0 ns

CLKOUT rising edge from EXTAL rising
edge with PLL enabled (MF = 1,
PDF = 1, Ef > 15 MHz)

3,5

0.0 ns

1.8 ns

CLKOUT falling edge from EXTAL rising
edge with PLL enabled (MF = 2 or 4, PDF =
1, Ef > 15 MHz)

3,5

0.0 ns

1.8 ns

CLKOUT falling edge from EXTAL falling
edge with PLL enabled (MF

4, PDF 1,

Ef / PDF > 15 MHz)

3,5

0.0 ns

1.8 ns

Instruction cycle time = I

CYC

= T

See

Table 2-5

(46.7%53.3% duty cycle)

CYC

· With PLL disabled

0.00 ns

· With PLL enabled

0.00 ns 8.53

µs

8.53

µs

Notes:

Measured at 50% of the input transition

The maximum value for PLL enabled is given for minimum V

and

maximum MF.

Periodically sampled and not 100% tested

The maximum value for PLL enabled is given for minimum V

and

maximum DF.

The skew is not guaranteed for any other MF value.

The indicated duty cycle is for the specified maximum frequency for which
a part is rated. The minimum clock high or low time required for correction
operation, however, remains the same at lower operating frequencies;
therefore, when a lower clock frequency is used, the signal symmetry may
vary from the specified duty cycle as long as the minimum high time and
low time requirements are met.

Table 2-5 Clock Operation (Continued) 100 and 120 MHz Values

No.

Characteristics

Symbol

100 MHz

120 MHz

Min

Max

Min

Max

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2-8

DSP56362 Advance Information

MOTOROLA

Specifications

Phase Lock Loop (PLL) Characteristics

PHASE LOCK LOOP (PLL) CHARACTERISTICS

RESET, STOP, MODE SELECT, AND INTERRUPT TIMING

Table 2-6 PLL Characteristics

Characteristics

100 MHz

Unit

Min

Max

frequency when PLL enabled

(MF

× E

× 2/PDF)

200

MHz

PLL external capacitor (PCAP pin
to V

CCP

) (C

PCAP

· @ MF

(MF

× 580) - 100

(MF

× 780) - 140

· @ MF > 4

× 830

× 1470

Note:

PCAP

is the value of the PLL capacitor (connected between the PCAP pin and

CCP

). The recommended value in pF for C

PCAP

can be computed from one of the

following equations:

(680

× MF) 120, for MF 4, or

1100

× MF, for MF > 4.

Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values

No.

Characteristics

Expression

100 MHz

120 MHz

Unit

Min

Max

Min

Max

8 Delay from RESET assertion to

all pins at reset value

26.0

Required RESET duration

· Power on, external clock

generator, PLL disabled

× ET

500.0

416.7

· Power on, external clock

generator, PLL enabled

1000

× ET

10.0

8.3

µs

· Power on, internal oscillator

75000

× ET

750

625

µs

· During STOP, XTAL

disabled (PCTL Bit 16 = 0)

75000

× ET

750

625

µs

· During STOP, XTAL enabled

(PCTL Bit 16 = 1)

2.5

× T

25.0

20.8

· During normal operation

2.5

× T

25.0

20.8

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Specifications

Reset, Stop, Mode Select, and Interrupt Timing

MOTOROLA

DSP56362 Advance Information

2-9

Delay from asynchronous
RESET deassertion to first
external address output
(internal reset deassertion)

· Minimum

3.25

× T

+ 2.0

34.5

29.1

· Maximum

20.25 T

+ 7.50

211.5

176.2

Synchronous reset setup time
from RESET deassertion to
CLKOUT Transition 1
· Minimum

5.9

· Maximum

10.0

Synchronous reset deasserted,
delay time from the CLKOUT
Transition 1 to the first external
address output
· Minimum

3.25

× T

+ 2.0

33.5

· Maximum

20.25 T

+ 7.5

207.5

13 Mode select setup time

30.0

14 Mode select hold time

0.0

Minimum edge-triggered
interrupt request assertion
width

6.6

5.5

Minimum edge-triggered
interrupt request deassertion
width

6.6

5.5

Delay from IRQA, IRQB, IRQC,
IRQD, NMI assertion to
external memory access
address out valid
· Caused by first interrupt

instruction fetch

4.25

× T

+ 2.0

44.5

37.4

· Caused by first interrupt

instruction execution

7.25

× T

+ 2.0

74.5

62.4

Delay from IRQA, IRQB, IRQC,
IRQD, NMI assertion to
general-purpose transfer output
valid caused by first interrupt
instruction execution

× T

+ 5.0

105.0

88.3

Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values

No.

Characteristics

Expression

100 MHz

120 MHz

Unit

Min

Max

Min

Max

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2-10

DSP56362 Advance Information

MOTOROLA

Specifications

Reset, Stop, Mode Select, and Interrupt Timing

Delay from address output valid
caused by first interrupt
instruction execute to interrupt
request deassertion for level
sensitive fast interrupts

(3.75 + WS)

× T

10.94

(Note 9)

Delay from RD assertion to
interrupt request deassertion
for level sensitive fast
interrupts

(3.25 + WS)

× T

10.94

(Note 9)

Delay from WR assertion to
interrupt request deassertion
for level sensitive fast
interrupts

· DRAM for all WS

(WS + 3.5)

× T

10.94

(Note 9)

· SRAM WS =1

(WS + 3.5)

× T

10.94

(Note 9)

· SRAM WS=2,3

1.75

× T

4.0

(Note 9)

· SRAM WS

2.75

× T

4.0

(Note 9)

Synchronous interrupt setup
time from IRQA, IRQB, IRQC,
IRQD, NMI assertion to the
CLKOUT Transition 2

0.6

× T

0.1

5.9

4.9

Synchronous interrupt delay
time from the CLKOUT
Transition 2 to the first external
address output valid caused by
the first instruction fetch after
coming out of Wait Processing
state
· Minimum

9.25

× T

+ 1.0

93.5

78.1

· Maximum

24.75

× T

+ 5.0

252.5

211.2

24 Duration for IRQA assertion to

recover from Stop state

0.6

× T

- 0.1

5.9

4.9

Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values

No.

Characteristics

Expression

100 MHz

120 MHz

Unit

Min

Max

Min

Max

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Specifications

Reset, Stop, Mode Select, and Interrupt Timing

MOTOROLA

DSP56362 Advance Information

2-11

Delay from IRQA assertion to
fetch of first instruction (when
exiting Stop)

2, 3

· PLL is not active during Stop

(PCTL Bit 17 = 0) and Stop
delay is enabled
(OMR Bit 6 = 0)

PLC

× ET

× PDF +

(128 K

- PLC/2) × T

1.3

13.6

· PLL is not active during Stop

(PCTL Bit 17 = 0) and Stop
delay is not enabled (OMR
Bit 6 = 1)

PLC

× ET

× PDF +

(23.75

± 0.5) × T

232.5

12.3 ms

· PLL is active during Stop

(PCTL Bit 17 = 1) (Implies
No Stop Delay)

(8.25

± 0.5) × T

77.5

87.5

64.6

72.9

Duration of level sensitive IRQA
assertion to ensure interrupt
service (when exiting Stop)

2, 3

· PLL is not active during Stop

(PCTL Bit 17 = 0) and Stop
delay is enabled
(OMR Bit 6 = 0)

PLC

× ET

× PDF +

(128K

- PLC/2) × T

13.6

· PLL is not active during Stop

(PCTL Bit 17 = 0) and Stop
delay is not enabled
(OMR Bit 6 = 1)

PLC

× ET

× PDF +

(20.5

± 0.5) × T

12.3

· PLL is active during Stop

(PCTL Bit 17 = 1) (implies no
Stop delay)

5.5

× T

55.0

45.8

Interrupt Requests Rate

· HI08, ESAI, SHI, Timer

12T

120.0

100.0

· DMA

80.0

66.7

· IRQ, NMI (edge trigger)

80.0

66.7

· IRQ, NMI (level trigger)

12T

120.0

100.0

Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values

No.

Characteristics

Expression

100 MHz

120 MHz

Unit

Min

Max

Min

Max

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2-12

DSP56362 Advance Information

MOTOROLA

Specifications

Reset, Stop, Mode Select, and Interrupt Timing

DMA Requests Rate

· Data read from HI08, ESAI,

SHI

60.0

50.0

· Data write to HI08, ESAI,

SHI

70.0

58.0

· Timer

20.0

16.7

· IRQ, NMI (edge trigger)

30.0

25.0

Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values

No.

Characteristics

Expression

100 MHz

120 MHz

Unit

Min

Max

Min

Max

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Specifications

Reset, Stop, Mode Select, and Interrupt Timing

MOTOROLA

DSP56362 Advance Information

2-13

Delay from IRQA, IRQB, IRQC,
IRQD, NMI assertion to
external memory (DMA source)
access address out valid

4.25

× T

+ 2.0

44.0

37.4

Notes:

When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings
19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the
deasserted Edge-triggered mode is recommended when using fast interrupts. Long interrupts are
recommended when using Level-sensitive mode.

This timing depends on several settings:
For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator
disabled during Stop (PCTL Bit 17 = 0), a stabilization delay is required to assure the oscillator is
stable before executing programs. In that case, resetting the Stop delay (OMR Bit 6 = 0) will provide
the proper delay. While it is possible to set OMR Bit 6 = 1, it is not recommended and these
specifications do not guarantee timings for that case.
For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL
Bit 17=1), no stabilization delay is required and recovery time will be minimal (OMR Bit 6 setting is
ignored).
For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery
time will be defined by the PCTL Bit 17 and OMR Bit 6 settings.
For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires
the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range
of 0 to 1000 cycles. This procedure occurs in parallel with the stop delay counter, and stop recovery
will end when the last of these two events occurs. The stop delay counter completes count or PLL lock
procedure completion.
PLC value for PLL disable is 0.
The maximum value for ET

is 4096 (maximum MF) divided by the desired internal frequency (i.e., for

100 MHz it is 4096/100 MHz = 40.96

µs). During the stabilization period, T

, T

and T

will not be

constant, and their width may vary, so timing may vary as well.

Periodically sampled and not 100% tested

For an external clock generator, RESET duration is measured during the time in which RESET is
asserted, V

is valid, and the EXTAL input is active and valid.

For internal oscillator, RESET duration is measured during the time in which RESET is asserted and
V

is valid. The specified timing reflects the crystal oscillator stabilization time after power-up. This

number is affected both by the specifications of the crystal and other components connected to the
oscillator and reflects worst case conditions.
When the V

is valid, but the other "required RESET duration" conditions (as specified above) have

not been yet met, the device circuitry will be in an uninitialized state that can result in significant power
consumption and heat-up. Designs should minimize this state to the shortest possible duration.

If PLL does not lose lock

= 3.3 V

± 0.16 V; T

= 0°C to +100°C, C

= 50 pF

WS = number of wait states (measured in clock cycles, number of T

)

Use expression to compute maximum value.

These values depend on the number of wait states (WS) selected

Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values

No.

Characteristics

Expression

100 MHz

120 MHz

Unit

Min

Max

Min

Max

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2-18

DSP56362 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

EXTERNAL MEMORY EXPANSION PORT (PORT A)

SRAM Timing

Table 2-8 SRAM Read and Write Accesses 100 and 120 MHz

No.

Characteristics

Symbol

Expression

100 MHz

120 MHz

Unit

Min

Max

Min

Max

100

Address valid and
AA assertion pulse
width

, t

(WS + 1)

× T

- 4.0

WS 3]

16.0

12.0

(WS + 2)

× T

- 4.0

WS 7]

56.0

46.0

(WS + 3)

× T

- 4.0

[WS

106.0

87.0

101

Address and AA
valid to WR
assertion

100 MHz:
0.25

× T

- 2.0

[WS = 1]

0.5

0.1

1.25

× T

- 2.0

[WS

10.5

8.4

102

WR assertion

pulse width

100 MHz:
1.5

× T

- 4.0 [WS = 1]

11.0

8.5

All frequencies:
WS

× T

- 4.0

WS 3]

16.0

12.7

(WS

- 0.5) × T

- 4.0

[WS

31.0

---

25.2

103 WR deassertion to

address not valid

100 MHz:
0.25

× T

- 2.0

WS 3]

0.5

0.1

1.25

× T

- 2.0

WS 7]

10.5

8.4

2.25

× T

- 2.0

[WS

20.5

16.7

All frequencies:
1.25

× T

- 4.0

WS 7]

8.5

6.4

2.25

× T

- 4.0

[WS

18.5

14.7

104

Address and AA
valid to input data
valid

, t

100 MHz:
(WS + 0.75)

× T

- 7.0

[WS

10.5

7.6

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Specifications

External Memory Expansion Port (Port A)

MOTOROLA

DSP56362 Advance Information

2-19

105 RD assertion to

input data valid

100 MHz:
(WS + 0.25)

× T

- 7.0

[WS

5.5

3.4

106

RD deassertion to
data not valid (data
hold time)

OHZ

0.0

107 Address valid to

WR deassertion

(WS + 0.75)

× T

- 4.0

[WS

13.5

10.6

108

Data valid to WR
deassertion (data
setup time)

)

100 MHz:
(WS

- 0.25) × T

- 3.0

[WS

4.5

3.2

109

Data hold time

from WR

deassertion

100 MHz:
0.25

× T

- 2.0

WS 3]

0.5

0.1

1.25

× T

- 2.0

WS 7]

10.5

8.4

2.25

× T

- 2.0

[WS

20.5

16.7

110 WR assertion to

data active

0.75

× T

- 3.7

[WS = 1]

2.5

0.25

× T

- 3.7

WS 3]

0.0

-0.25 × T

- 3.7

[WS

0.0

111

WR deassertion to

data high

impedance

0.25

× T

+ 0.2

WS 3]

2.3

1.25

× T

+ 0.2

WS 7]

10.6

2.25

× T

+ 0.2

[WS

18.9

112

Previous RD
deassertion to data
active (write)

1.25

× T

- 4.0

WS 3]

6.4

2.25

× T

- 4.0

WS 7]

14.7

3.25

× T

- 4.0

[WS

23.1

Table 2-8 SRAM Read and Write Accesses 100 and 120 MHz

(Continued)

No.

Characteristics

Symbol

Expression

100 MHz

120 MHz

Unit

Min

Max

Min

Max

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2-20

DSP56362 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

113 RD deassertion

time

100 MHz
0.75

× T

- 4.0

WS 3]

3.5

2.2

1.75

× T

- 4.0

WS 7]

13.5

10.6

2.75

× T

- 4.0

[WS

23.5

18.9

114 WR deassertion

time

100 MHz
0.5

× T

- 4.0

[WS = 1]

1.0

0.2

- 2.0

WS 3]

6.0

6.3

2.5

× T

- 4.0

WS 7]

21.0

16.8

3.5

× T

- 4.0

[WS

31.0

25.2

115 Address valid to

RD assertion

100 MHz
0.5

× T

- 4.0

1.0

0.2

116 RD assertion pulse

width

100 MHz
(WS + 0.25)

× T

-4.0

8.5

6.4

117 RD deassertion to

address not valid

100 MHz
0.25

× T

- 2.0

WS 3]

0.5

0.1

1.25

× T

- 2.0

WS 7]

10.5

8.4

2.25

× T

- 2.0

[WS

20.5

16.7

118

TA setup before
RD or WR
deassertion

0.25

× T

+ 2.0

4.5

4.1

119 TA hold after RD or

WR deassertion

0.0

Notes:

WS is the number of wait states specified in the BCR.

Timings 100, 107 are guaranteed by design, not tested.

All timings for 100 MHz are measured from 0.5

Vcc to .05

Vcc

In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to
remain active

Timing 110, 111, and 112, are not specified for 100 MHz.

Table 2-8 SRAM Read and Write Accesses 100 and 120 MHz

(Continued)

No.

Characteristics

Symbol

Expression

100 MHz

120 MHz

Unit

Min

Max

Min

Max

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2-22

DSP56362 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

DRAM Timing

The selection guides provided in

Figure 2-13

and

Figure 2-16

should be used for primary selection only.

Final selection should be based on the timing provided in the following tables. As an example, the
selection guide suggests that 4 wait states must be used for 100 MHz operation when using Page Mode
DRAM. However, by using the information in the appropriate table, a designer may choose to evaluate
whether fewer wait states might be used by determining which timing prevents operation at 100 MHz,
running the chip at a slightly lower frequency (e.g., 95 MHz), using faster DRAM (if it becomes available),
and control factors such as capacitive and resistive load to improve overall system performance.

Figure 2-13 DRAM Page Mode Wait States Selection Guide

Chip Frequency
(MHz)

DRAM Type

(tRAC ns)

100

1 Wait States

2 Wait States

3 Wait States

4 Wait States

Note:

This figure should be used for primary selection.
For exact and detailed timings see the following
tables.

AA0472

120

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Specifications

External Memory Expansion Port (Port A)

MOTOROLA

DSP56362 Advance Information

2-23

Table 2-9 DRAM Page Mode Timings, One Wait State

(Low-Power Applications)

1, 2, 3

No.

Characteristics

Symbol

Expression

20 MHz

30 MHz

Unit

Min Max

131

Page mode cycle time for
two consecutive accesses of
the same direction

× T

100.0

66.7

Page mode cycle time for
mixed (read and write)
accesses.

1.25 x Tc

62.5

41.7

132 CAS assertion to data valid

(read)

CAC

- 7.5

42.5

25.8

133 Column address valid to

data valid (read)

1.5

× T

- 7.5

67.5

42.5

134 CAS deassertion to data not

valid (read hold time)

OFF

0.0

135 Last CAS assertion to RAS

deassertion

RSH

0.75

× T

- 4.0 33.5

21.0

136 Previous CAS deassertion to

RAS deassertion

RHCP

× T

- 4.0

96.0

62.7

137 CAS assertion pulse width

CAS

0.75

× T

- 4.0 33.5

21.0

138

Last CAS deassertion to
RAS deassertion

CRP

· BRW[1:0] = 00

1.75

× T

- 6.0 81.5

52.3

· BRW[1:0] = 01

3.25

× T

- 6.0 156.5

102.2

· BRW[1:0] = 10

4.25

× T

- 6.0 206.5

135.5

· BRW[1:0] = 11

6.25

× T

6.0 306.5

202.1

139 CAS deassertion pulse width

0.5

× T

- 4.0

21.0

12.7

140 Column address valid to

CAS assertion

ASC

0.5

× T

- 4.0

21.0

12.7

141 CAS assertion to column

address not valid

CAH

0.75

× T

- 4.0 33.5

21.0

142 Last column address valid to

RAS deassertion

RAL

× T

- 4.0

96.0

62.7

143 WR deassertion to CAS

assertion

RCS

0.75

× T

- 3.8 33.7

21.2

144 CAS deassertion to WR

assertion

RCH

0.25

× T

- 3.7

8.8

4.6

145 CAS assertion to WR

deassertion

WCH

0.5

× T

- 4.2

20.8

12.5

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2-24

DSP56362 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

146 WR assertion pulse widt

1.5

× T

- 4.5

70.5

45.5

147 Last WR assertion to RAS

deassertion

RWL

1.75

× T

- 4.3 83.2

54.0

148 WR assertion to CAS

deassertion

CWL

1.75

× T

- 4.3 83.2

54.0

149 Data valid to CAS assertion

(Write)

0.25

× T

- 4.0

8.5

4.3

150 CAS assertion to data not

valid (write)

0.75

× T

- 4.0 33.5

21.0

151 WR assertion to CAS

assertion

WCS

- 4.3

45.7

29.0

152 Last RD assertion to RAS

deassertion

ROH

1.5

× T

- 4.0

71.0

46.0

153 RD assertion to data valid

- 7.5

42.5

25.8

154 RD deassertion to data not

valid

0.0

155 WR assertion to data active

0.75

× T

- 0.3 37.2

24.7

156 WR deassertion to data high

impedance

0.25

× T

12.5

8.3

Notes:

The number of wait states for Page mode access is specified in the DCR.

The refresh period is specified in the DCR.

All the timings are calculated for the worst case. Some of the timings are better for specific cases
(e.g., t

equals 2

× T

for read-after-read or write-after-write sequences).

BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in
each DRAM out-of-page access.

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t

OFF

and

not t

Reduced DSP clock speed allows use of Page Mode DRAM with one Wait state. See

Figure 2-13

Table 2-10 DRAM Page Mode Timings, Two Wait States

1, 2, 3, 7

No.

Characteristics

Symbol

Expression

80 MHz

Unit

Min

Max

131

Page mode cycle time for two
consecutive accesses of the same
direction

× T

37.5

Page mode cycle time for mixed (read
and write) accesses.

2.75 x Tc

34.4

Table 2-9 DRAM Page Mode Timings, One Wait State

(Low-Power Applications)

1, 2, 3

(Continued)

No.

Characteristics

Symbol

Expression

20 MHz

30 MHz

Unit

Min Max

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r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Specifications

External Memory Expansion Port (Port A)

MOTOROLA

DSP56362 Advance Information

2-25

132 CAS assertion to data valid (read)

CAC

1.5

× T

- 6.5

12.3

133 Column address valid to data valid

(read)

2.5

× T

- 6.5

24.8

134 CAS deassertion to data not valid (read

hold time)

OFF

0.0

135 Last CAS assertion to RAS deassertion

RSH

1.75

× T

- 4.0

17.9

136 Previous CAS deassertion to RAS

deassertion

RHCP

3.25

× T

- 4.0

36.6

137 CAS assertion pulse width

CAS

1.5

× T

- 4.0

14.8

138

Last CAS deassertion to RAS
deassertion

CRP

· BRW[1:0] = 00

2.0

× T

- 6.0

19.0

· BRW[1:0] = 01

3.5

× T

- 6.0

37.8

· BRW[1:0] = 10

4.5

× T

- 6.0

50.3

· BRW[1:0] = 11

6.5

× T

- 6.0

75.3

139 CAS deassertion pulse width

1.25

× T

- 4.0

11.6

140 Column address valid to CAS assertion

ASC

- 4.0

8.5

141 CAS assertion to column address not

valid

CAH

1.75

× T

- 4.0

17.9

142 Last column address valid to RAS

deassertion

RAL

× T

- 4.0

33.5

143 WR deassertion to CAS assertion

RCS

1.25

× T

- 3.8

11.8

144 CAS deassertion to WR assertion

RCH

0.5

× T

- 3.7

2.6

145 CAS assertion to WR deassertion

WCH

1.5

× T

- 4.2

14.6

146 WR assertion pulse width

2.5

× T

- 4.5

26.8

147 Last WR assertion to RAS deassertion

RWL

2.75

× T

- 4.3

30.1

148 WR assertion to CAS deassertion

CWL

2.5

× T

- 4.3

27.0

149 Data valid to CAS assertion (write)

0.25

× T

- 3.0

0.1

150 CAS assertion to data not valid (write)

1.75

× T

- 4.0

17.9

151 WR assertion to CAS assertion

WCS

- 4.3

8.2

152 Last RD assertion to RAS deassertion

ROH

2.5

× T

- 4.0

27.3

153 RD assertion to data valid

1.75

× T

- 6.5

15.4

154 RD deassertion to data not valid

0.0

155 WR assertion to data active

0.75

× T

- 0.3

9.1

Table 2-10 DRAM Page Mode Timings, Two Wait States

1, 2, 3, 7

(Continued)

No.

Characteristics

Symbol

Expression

80 MHz

Unit

Min

Max

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

2-26

DSP56362 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

156 WR deassertion to data high

impedance

0.25

× T

3.1

Notes: 1.

The number of wait states for Page mode access is specified in the DCR.

The refresh period is specified in the DCR.

The asynchronous delays specified in the expressions are valid for

DSP56362

All the timings are calculated for the worst case. Some of the timings are better for specific cases
(e.g., t

equals 3

× T

for read-after-read or write-after-write sequences).

BRW[1:0] (DRAM Control Register bits) defines the number of wait states that should be inserted
in each DRAM out-of-page access.

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t

OFF

and not t

GZ.

There are not any fast enough DRAMs to fit to two wait states Page mode @ 100MHz. See

Figure 2-13

Table 2-11 DRAM Page Mode Timings, Three Wait States

1, 2, 3

No.

Characteristics

Symbol

Expression

100 MHz

Unit

Min

Max

131

Page mode cycle time for two
consecutive accesses of the same
direction

× T

40.0

Page mode cycle time for mixed (read
and write) accesses.

3.5 x Tc

35.0

132 CAS assertion to data valid (read)

CAC

100 MHz:

× T

- 7.0

13.0

133 Column address valid to data valid

(read)

100 MHz:

× T

- 7.0

23.0

134 CAS deassertion to data not valid (read

hold time)

OFF

0.0

135 Last CAS assertion to RAS deassertion

RSH

2.5

× T

- 4.0

21.0

136 Previous CAS deassertion to RAS

deassertion

RHCP

4.5

× T

- 4.0

41.0

137 CAS assertion pulse width

CAS

× T

- 4.0

16.0

138

Last CAS deassertion to RAS
assertion

CRP

· BRW[1:0] = 00

2.25

× T

- 6.0

· BRW[1:0] = 01

3.75

× T

- 6.0

· BRW[1:0] = 10

4.75

× T

- 6.0 41.5

· BRW[1:0] = 11

6.75

× T

- 6.0 61.5

Table 2-10 DRAM Page Mode Timings, Two Wait States

1, 2, 3, 7

(Continued)

No.

Characteristics

Symbol

Expression

80 MHz

Unit

Min

Max

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Specifications

External Memory Expansion Port (Port A)

MOTOROLA

DSP56362 Advance Information

2-27

139 CAS deassertion pulse width

1.5

× T

- 4.0

11.0

140 Column address valid to CAS assertion

ASC

- 4.0

6.0

141 CAS assertion to column address not

valid

CAH

2.5

× T

- 4.0

21.0

142 Last column address valid to RAS

deassertion

RAL

× T

- 4.0

36.0

143 WR deassertion to CAS assertion

RCS

100 MHz:

1.25

× T

- 4.0

8.5

144 CAS deassertion to WR assertion

RCH

100 MHz:

0.75

× T

- 4.0

3.5

145 CAS assertion to WR deassertion

WCH

2.25

× T

- 4.2 18.3

146 WR assertion pulse width

3.5

× T

- 4.5

30.5

147 Last WR assertion to RAS deassertion

RWL

3.75

× T

- 4.3 33.2

148 WR assertion to CAS deassertion

CWL

3.25

× T

- 4.3 28.2

149 Data valid to CAS assertion (write)

0.5

× T

- 4.0

1.0

150 CAS assertion to data not valid (write)

2.5

× T

- 4.0

21.0

151 WR assertion to CAS assertion

WCS

1.25

× T

- 4.3

8.2

152 Last RD assertion to RAS deassertion

ROH

3.5

× T

- 4.0

31.0

153 RD assertion to data valid

100 MHz:

2.5

× T

- 7.0

18.0

154 RD deassertion to data not valid

0.0

155 WR assertion to data active

0.75

× T

- 0.3

7.2

156 WR deassertion to data high

impedance

0.25

× T

2.5

Notes:

The number of wait states for Page mode access is specified in the DCR.

The refresh period is specified in the DCR.

The asynchronous delays specified in the expressions are valid for DSP56362

All the timings are calculated for the worst case. Some of the timings are better for specific
cases (e.g., t

equals 4

× T

for read-after-read or write-after-write sequences).

BRW[1:0] (DRAM control register bits) defines the number of wait states that should be
inserted in each DRAM out-of page-access.

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is
t

OFF

and not t

Table 2-11 DRAM Page Mode Timings, Three Wait States

1, 2, 3

(Continued)

No.

Characteristics

Symbol

Expression

100 MHz

Unit

Min

Max

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

2-28

DSP56362 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

Table 2-12 DRAM Page Mode Timings, Four Wait States 100 and 120MHz

1, 2, 3

No.

Characteristics

Symbol

Expression

100 MHz

120 MHz

Unit

Min Max Min Max

131

Page mode cycle time for two
consecutive accesses of the same
direction

× T

50.0

41.7

Page mode cycle time for mixed (read
and write) accesses.

4.5

× T

45.0

37.5

132 CAS assertion to data valid (read)

CAC

100 MHz:

2.75

× T

- 7.0

20.5

15.9

133 Column address valid to data valid

(read)

100 MHz:

3.75

× T

- 7.0

30.5

24.2

134 CAS deassertion to data not valid

(read hold time)

OFF

0.0

135 Last CAS assertion to RAS

deassertion

RSH

3.5

× T

- 4.0 31.0 --

25.2

136 Previous CAS deassertion to RAS

deassertion

RHCP

× T

- 4.0

56.0

46.0

137 CAS assertion pulse width

CAS

2.5

× T

- 4.0 21.0 --

16.8

138

Last CAS deassertion to RAS
assertion

CRP

· BRW[1:0] = 00

2.75

× T

- 6.0

· BRW[1:0] = 01

4.25

× T

- 6.0

· BRW[1:0] = 10

5.25

× T

- 6.0 46.5 --

37.7

· BRW[1:0] = 11

7.25

× T

- 6.0 66.5 --

54.4

139 CAS deassertion pulse width

× T

- 4.0

16.0

12.7

140 Column address valid to CAS

assertion

ASC

- 4.0

6.0

4.3

141 CAS assertion to column address not

valid

CAH

3.5

× T

- 4.0 31.0 --

25.2

142 Last column address valid to RAS

deassertion

RAL

× T

- 4.0

46.0

37.7

143 WR deassertion to CAS assertion

RCS

100 MHz:

1.25

× T

- 4.0

8.5

6.4

144 CAS deassertion to WR assertion

RCH

100 MHz:

1.25

× T

- 4.0

8.5

6.4

145 CAS assertion to WR deassertion

WCH

3.25

× T

- 4.2 28.3 --

22.9

146 WR assertion pulse width

4.5

× T

- 4.5 40.5 --

33.0

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Specifications

External Memory Expansion Port (Port A)

MOTOROLA

DSP56362 Advance Information

2-29

147 Last WR assertion to RAS

deassertion

RWL

4.75

× T

4.3 43.2

35.3

148 WR assertion to CAS deassertion

CWL

3.75

× T

- 4.3 33.2 --

26.9

149 Data valid to CAS assertion (write)

0.5

× T

- 4.0

1.0

0.2

150 CAS assertion to data not valid (write)

3.5

× T

- 4.0 31.0 --

25.2

151 WR assertion to CAS assertion

WCS

1.25

× T

- 4.3 8.2

6.1

152 Last RD assertion to RAS deassertion

ROH

4.5

× T

- 4.0 41.0 --

33.5

153 RD assertion to data valid

100 MHz:

3.25

× T

- 7.0

25.5

20.1

154 RD deassertion to data not valid

0.0

155 WR assertion to data active

0.75

× T

- 0.3 7.2

5.9

156 WR deassertion to data high

impedance

0.25

× T

2.5

2.1

Notes: 1.

The number of wait states for Page mode access is specified in the DCR.

The refresh period is specified in the DCR.

The asynchronous delays specified in the expressions are valid for DSP56362.

All the timings are calculated for the worst case. Some of the timings are better for specific cases
(e.g., t

equals 3

× T

for read-after-read or write-after-write sequences).

BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in
each DRAM out-of-page access.

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t

OFF

and

not t

Table 2-12 DRAM Page Mode Timings, Four Wait States 100 and 120MHz

1, 2, 3

(Continued)

No.

Characteristics

Symbol

Expression

100 MHz

120 MHz

Unit

Min Max Min Max

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

2-32

DSP56362 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

Figure 2-16 DRAM Out-of-Page Wait States Selection Guide

Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States

1, 2

No.

Characteristics

Symbol

Expression

20 MHz

30 MHz

Unit

Min Max

157 Random read or write

cycle time

× T

250.0

166.7

158 RAS assertion to data

valid (read)

RAC

2.75

× T

- 7.5

130.0

84.2

159 CAS assertion to data

valid (read)

CAC

1.25

× T

- 7.5

55.0

34.2

160 Column address valid to

data valid (read)

1.5

× T

- 7.5

67.5

42.5

161 CAS deassertion to data

not valid (read hold time)

OFF

0.0

162 RAS deassertion to RAS

assertion

1.75

× T

- 4.0

83.5

54.3

Chip Frequency
(MHz)

DRAM Type

(tRAC ns)

100

4 Wait States

8 Wait States

11 Wait States

15 Wait States

Note:

This figure should be use for primary selection. For
exact and detailed timings see the following tables.

120

AA0475

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

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.

Specifications

External Memory Expansion Port (Port A)

MOTOROLA

DSP56362 Advance Information

2-33

163 RAS assertion pulse

width

RAS

3.25

× T

- 4.0

158.5

104.3

164 CAS assertion to RAS

deassertion

RSH

1.75

× T

- 4.0

83.5

54.3

165 RAS assertion to CAS

deassertion

CSH

2.75

× T

- 4.0

133.5

87.7

166 CAS assertion pulse

width

CAS

1.25

× T

- 4.0

58.5

37.7

167 RAS assertion to CAS

assertion

RCD

1.5

× T

± 2

73.0

77.0

48.0

52.0

168 RAS assertion to column

address valid

RAD

1.25

× T

± 2

60.5

64.5

39.7

43.7

169 CAS deassertion to RAS

assertion

CRP

2.25

× T

- 4.0

108.5

71.0

170 CAS deassertion pulse

width

1.75

× T

- 4.0

83.5

54.3

171 Row address valid to

RAS assertion

ASR

1.75

× T

- 4.0

83.5

54.3

172 RAS assertion to row

address not valid

RAH

1.25

× T

- 4.0

58.5

37.7

173 Column address valid to

CAS assertion

ASC

0.25

× T

- 4.0

8.5

4.3

174 CAS assertion to column

address not valid

CAH

1.75

× T

- 4.0

83.5

54.3

175 RAS assertion to column

address not valid

3.25

× T

- 4.0

158.5

104.3

176 Column address valid to

RAS deassertion

RAL

× T

- 4.0

96.0

62.7

177 WR deassertion to CAS

assertion

RCS

1.5

× T

- 3.8

71.2

46.2

178 CAS deassertion to WR

assertion

RCH

0.75

× T

- 3.7

33.8

21.3

179 RAS deassertion to WR

assertion

RRH

0.25

× T

- 3.7

8.8

4.6

180 CAS assertion to WR

deassertion

WCH

1.5

× T

- 4.2

70.8

45.8

181 RAS assertion to WR

deassertion

WCR

× T

- 4.2

145.8

95.8

Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States

1, 2

(Continued)

No.

Characteristics

Symbol

Expression

20 MHz

30 MHz

Unit

Min Max

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

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.
.

2-34

DSP56362 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

182 WR assertion pulse width

4.5

× T

- 4.5

220.5

145.5

183 WR assertion to RAS

deassertion

RWL

4.75

× T

- 4.3

233.2

154.0

184 WR assertion to CAS

deassertion

CWL

4.25

× T

- 4.3

208.2

137.4

185 Data valid to CAS

assertion (write)

2.25

× T

- 4.0

108.5

71.0

186 CAS assertion to data not

valid (write)

1.75

× T

- 4.0

83.5

54.3

187 RAS assertion to data not

valid (write)

DHR

3.25

× T

- 4.0 158.5

104.3

188 WR assertion to CAS

assertion

WCS

× T

- 4.3

145.7

95.7

189 CAS assertion to RAS

assertion (refresh)

CSR

0.5

× T

- 4.0

21.0

12.7

190 RAS deassertion to CAS

assertion (refresh)

RPC

1.25

× T

- 4.0

58.5

37.7

191 RD assertion to RAS

deassertion

ROH

4.5

× T

- 4.0

221.0

146.0

192 RD assertion to data valid

× T

- 7.5

192.5

125.8

193 RD deassertion to data

not valid

0.0

194 WR assertion to data

active

0.75

× T

- 0.3

37.2

24.7

195 WR deassertion to data

high impedance

0.25

× T

12.5

8.3

Notes: 1.

The number of wait states for out of page access is specified in the DCR.

The refresh period is specified in the DCR.

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t

OFF

and

not t

Reduced DSP clock speed allows use of DRAM out-of-page access with four Wait states. See

Figure 2-16

Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States

1, 2

(Continued)

No.

Characteristics

Symbol

Expression

20 MHz

30 MHz

Unit

Min Max

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Specifications

External Memory Expansion Port (Port A)

MOTOROLA

DSP56362 Advance Information

2-35

Table 2-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States

1, 2

No.

Characteristics

Symbol

Expression

80 MHz

Unit

Min Max

157 Random read or write cycle time

× T

112.

158 RAS assertion to data valid (read)

RAC

4.75

× T

- 6.5

52.9

159 CAS assertion to data valid (read)

CAC

2.25

× T

- 6.5

21.6

160 Column address valid to data valid (read)

× T

- 6.5

31.0

161 CAS deassertion to data not valid (read

hold time)

OFF

0.0

162 RAS deassertion to RAS assertion

3.25

× T

- 4.0 36.6

163 RAS assertion pulse width

RAS

5.75

× T

- 4.0 67.9

164 CAS assertion to RAS deassertion

RSH

3.25

× T

- 4.0 36.6

165 RAS assertion to CAS deassertion

CSH

4.75

× T

- 4.0 55.4

166 CAS assertion pulse width

CAS

2.25

× T

- 4.0 24.1

167 RAS assertion to CAS assertion

RCD

2.5

× T

± 2

29.3 33.3

168 RAS assertion to column address valid

RAD

1.75

× T

± 2

19.9 23.9

169 CAS deassertion to RAS assertion

CRP

4.25

× T

- 4.0 49.1

170 CAS deassertion pulse width

2.75

× T

- 4.0 30.4

171 Row address valid to RAS assertion

ASR

3.25

× T

- 4.0 36.6

172 RAS assertion to row address not valid

RAH

1.75

× T

- 4.0 17.9

173 Column address valid to CAS assertion

ASC

0.75

× T

- 4.0

5.4

174 CAS assertion to column address not valid

CAH

3.25

× T

- 4.0 36.6

175 RAS assertion to column address not valid

5.75

× T

- 4.0 67.9

176 Column address valid to RAS deassertion

RAL

× T

- 4.0

46.0

177 WR deassertion to CAS assertion

RCS

× T

- 3.8

21.2

178 CAS deassertion to WR

assertion

RCH

1.25

× T

- 3.7 11.9

179 RAS deassertion to WR

assertion

RRH

0.25

× T

- 3.0

0.1

180 CAS assertion to WR deassertion

WCH

× T

- 4.2

33.3

181 RAS assertion to WR deassertion

WCR

5.5

× T

- 4.2

64.6

182 WR assertion pulse width

8.5

× T

- 4.5

101.

183 WR assertion to RAS deassertion

RWL

8.75

× T

- 4.3

105.

184 WR assertion to CAS deassertion

CWL

7.75

× T

- 4.3 92.6

185 Data valid to CAS assertion (write)

4.75

× T

- 4.0 55.4

r
e

s
c

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c

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Freescale Semiconductor, Inc.

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.

2-36

DSP56362 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

186 CAS assertion to data not valid (write)

3.25

× T

- 4.0 36.6

187 RAS assertion to data not valid (write)

DHR

5.75

× T

- 4.0 67.9

188 WR assertion to CAS assertion

WCS

5.5

× T

- 4.3

64.5

189 CAS assertion to RAS assertion (refresh)

CSR

1.5

× T

- 4.0

14.8

190 RAS deassertion to CAS assertion (refresh)

RPC

1.75

× T

- 4.0 17.9

191 RD assertion to RAS deassertion

ROH

8.5

× T

- 4.0

102.

192 RD assertion to data valid

7.5

× T

- 6.5

87.3

193 RD deassertion to data not valid

0.0

194 WR assertion to data active

0.75

× T

- 0.3

9.1

195 WR deassertion to data high impedance

0.25

× T

3.1

Notes:

The number of wait states for out-of-page access is specified in the DCR.

The refresh period is specified in the DCR.

The asynchronous delays specified in the expressions are valid for DSP56362.

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t

OFF

and not t

Either t

RCH

or t

RRH

must be satisfied for read cycles.

Table 2-15 DRAM Out-of-Page and Refresh Timings,

Eleven Wait States

1, 2

No.

Characteristics

Symbol

Expression

100 MHz

Unit

Min

Max

157 Random read or write cycle time

× T

120.0

158 RAS assertion to data valid (read)

RAC

6.25

× T

- 7.0

55.5

159 CAS assertion to data valid (read)

CAC

3.75

× T

- 7.0

30.5

160 Column address valid to data valid

(read)

4.5

× T

- 7.0

38.0

161 CAS deassertion to data not valid (read

hold time)

OFF

0.0

162 RAS deassertion to RAS assertion

4.25

× T

- 4.0

38.5

163 RAS assertion pulse width

RAS

7.75

× T

- 4.0

73.5

164 CAS assertion to RAS deassertion

RSH

5.25

× T

- 4.0

48.5

165 RAS assertion to CAS deassertion

CSH

6.25

× T

- 4.0

58.5

Table 2-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States

1, 2

(Continued)

No.

Characteristics

Symbol

Expression

80 MHz

Unit

Min Max

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Specifications

External Memory Expansion Port (Port A)

MOTOROLA

DSP56362 Advance Information

2-37

166 CAS assertion pulse width

CAS

3.75

× T

- 4.0

33.5

167 RAS assertion to CAS assertion

RCD

2.5

× T

± 4.0

21.0

29.0

168 RAS assertion to column address valid

RAD

1.75

× T

± 4.0

13.5

21.5

169 CAS deassertion to RAS assertion

CRP

5.75

× T

- 4.0

53.5

170 CAS deassertion pulse width

4.25

× T

- 4.0

38.5

171 Row address valid to RAS assertion

ASR

4.25

× T

- 4.0

38.5

172 RAS assertion to row address not valid

RAH

1.75

× T

- 4.0

13.5

173 Column address valid to CAS assertion

ASC

0.75

× T

- 4.0

3.5

174 CAS assertion to column address not

valid

CAH

5.25

× T

- 4.0

48.5

175 RAS assertion to column address not

valid

7.75

× T

- 4.0

73.5

176 Column address valid to RAS

deassertion

RAL

× T

- 4.0

56.0

177 WR deassertion to CAS assertion

RCS

3.0

× T

- 4.0

26.0

178 CAS deassertion to WR

assertion

RCH

1.75

× T

- 4.0

13.5

179 RAS deassertion to WR

assertion

RRH

0.25

× T

- 3.0

0.25

× T

- 2.0

0.5

180 CAS assertion to WR deassertion

WCH

× T

- 4.2

45.8

181 RAS assertion to WR deassertion

WCR

7.5

× T

- 4.2

70.8

182 WR assertion pulse width

11.5

× T

- 4.5 110.5

183 WR assertion to RAS deassertion

RWL

11.75

× T

- 4.3 113.2

184 WR assertion to CAS deassertion

CWL

10.25

× T

- 4.3 103.2

185 Data valid to CAS assertion (write)

5.75

× T

- 4.0

53.5

186 CAS assertion to data not valid (write)

5.25

× T

- 4.0

48.5

187 RAS assertion to data not valid (write)

DHR

7.75

× T

- 4.0

73.5

188 WR assertion to CAS assertion

WCS

6.5

× T

- 4.3

60.7

189 CAS assertion to RAS assertion

(refresh)

CSR

1.5

× T

- 4.0

11.0

190 RAS deassertion to CAS assertion

(refresh)

RPC

2.75

× T

- 4.0

23.5

191 RD assertion to RAS deassertion

ROH

11.5

× T

- 4.0 111.0

192 RD assertion to data valid

× T

- 7.0

93.0

Table 2-15 DRAM Out-of-Page and Refresh Timings,

Eleven Wait States

1, 2

(Continued)

No.

Characteristics

Symbol

Expression

100 MHz

Unit

Min

Max

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2-38

DSP56362 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

193 RD deassertion to data not valid

0.0

194 WR assertion to data active

0.75

× T

- 0.3

7.2

195 WR deassertion to data high

impedance

0.25

× T

2.5

Notes: 1.

The number of wait states for out-of-page access is specified in the DCR.

The refresh period is specified in the DCR.

The asynchronous delays specified in the expressions are valid for DSP56362.

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is
t

OFF

and not t

Either t

RCH

or t

RRH

must be satisfied for read cycles.

Table 2-16 DRAM Out-of-Page and Refresh Timings,

Fifteen Wait States 100 and 120MHz

1, 2

No.

Characteristics

Symbol

Expression

100 MHz

120 MHz

Unit

Min

Max

Min

Max

157 Random read or write cycle time

× T

160.0

133.3

158 RAS assertion to data valid (read)

RAC

8.25

× T

- 5.7

76.8

63.0

159 CAS assertion to data valid (read)

CAC

4.75

× T

- 5.7

41.8

33.9

160 Column address valid to data valid

(read)

5.5

× T

- 5.7

49.3

40.1

161 CAS deassertion to data not valid

(read hold time)

OFF

0.0

162 RAS deassertion to RAS assertion

6.25

× T

- 4.0

58.5

48.1

163 RAS assertion pulse width

RAS

9.75

× T

- 4.0

93.5

77.2

164 CAS assertion to RAS deassertion

RSH

6.25

× T

- 4.0

58.5

48.1

165 RAS assertion to CAS deassertion

CSH

8.25

× T

- 4.0

78.5

64.7

166 CAS assertion pulse width

CAS

4.75

× T

- 4.0

43.5

35.6

167 RAS assertion to CAS assertion

RCD

3.5

× T

± 2

33.0

37.0

27.2

31.2

168 RAS assertion to column address

valid

RAD

2.75

× T

± 2

25.5

29.5

20.9

24.9

169 CAS deassertion to RAS assertion

CRP

7.75

× T

- 4.0

73.5

60.6

170 CAS deassertion pulse width

6.25

× T

- 4.0

58.5

48.1

171 Row address valid to RAS

assertion

ASR

6.25

× T

- 4.0

58.5

48.1

Table 2-15 DRAM Out-of-Page and Refresh Timings,

Eleven Wait States

1, 2

(Continued)

No.

Characteristics

Symbol

Expression

100 MHz

Unit

Min

Max

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Specifications

External Memory Expansion Port (Port A)

MOTOROLA

DSP56362 Advance Information

2-39

172 RAS assertion to row address not

valid

RAH

2.75

× T

- 4.0

23.5

18.9

173 Column address valid to CAS

assertion

ASC

0.75

× T

- 4.0

3.5

2.2

174 CAS assertion to column address

not valid

CAH

6.25

× T

- 4.0

58.5

48.1

175 RAS assertion to column address

not valid

9.75

× T

- 4.0

93.5

77.2

176 Column address valid to RAS

deassertion

RAL

× T

- 4.0

66.0

54.3

177 WR deassertion to CAS assertion

RCS

× T

- 3.8

46.2

37.9

178 CAS deassertion to WR

assertion

RCH

1.75

× T

- 3.7

13.8

10.9

179 RAS deassertion to WR

assertion

RRH

0.25

× T

- 2.0

0.5

0.1

180 CAS assertion to WR deassertion

WCH

× T

- 4.2

55.8

45.8

181 RAS assertion to WR deassertion

WCR

9.5

× T

- 4.2

90.8

75.0

182 WR assertion pulse width

15.5

× T

- 4.5 150.5

124.7

183 WR assertion to RAS deassertion

RWL

15.75

× T

- 4.3 153.2

126.9

184 WR assertion to CAS deassertion

CWL

14.25

× T

- 4.3 138.2

114.4

185 Data valid to CAS assertion (write)

8.75

× T

- 4.0

83.5

68.9

186 CAS assertion to data not valid

(write)

6.25

× T

- 4.0

58.5

48.1

187 RAS assertion to data not valid

(write)

DHR

9.75

× T

- 4.0

93.5

77.2

188 WR assertion to CAS assertion

WCS

9.5

× T

- 4.3

90.7

74.9

189 CAS assertion to RAS assertion

(refresh)

CSR

1.5

× T

- 4.0

11.0

8.5

190 RAS deassertion to CAS assertion

(refresh)

RPC

4.75

× T

- 4.0

43.5

35.6

191 RD assertion to RAS deassertion

ROH

15.5

× T

- 4.0 151.0

125.2

192 RD assertion to data valid

× T

- 5.7

134.3

111.0

193 RD deassertion to data not valid

0.0

194 WR assertion to data active

0.75

× T

- 0.3

7.2

5.9

195 WR deassertion to data high

impedance

0.25

× T

2.5

2.1

Table 2-16 DRAM Out-of-Page and Refresh Timings,

Fifteen Wait States 100 and 120MHz

1, 2

(Continued)

No.

Characteristics

Symbol

Expression

100 MHz

120 MHz

Unit

Min

Max

Min

Max

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2-40

DSP56362 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

Figure 2-17 DRAM Out-of-Page Read Access

Notes:

The number of wait states for out-of-page access is specified in the DCR.

The refresh period is specified in the DCR.

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t

OFF

and not t

Either t

RCH

or t

RRH

must be satisfied for read cycles.

Table 2-16 DRAM Out-of-Page and Refresh Timings,

Fifteen Wait States 100 and 120MHz

1, 2

(Continued)

No.

Characteristics

Symbol

Expression

100 MHz

120 MHz

Unit

Min

Max

Min

Max

RAS

CAS

A0A17

D0D23

Data

Row Address

Column Address

157

163

165

162

169

170

171

168

167

164

166

173

174

175

172

177

176

191

160

168

159

193

161

192

158

179

AA0476

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Specifications

External Memory Expansion Port (Port A)

MOTOROLA

DSP56362 Advance Information

2-43

Synchronous Timings (SRAM)

Table 2-17 External Bus Synchronous Timings (SRAM Access)

No.

Characteristics

Expression

1, 2

100 MHz

Unit

Min Max

198 CLKOUT high to address, and

AA valid

0.25

× T

+ 4.0

6.5

199 CLKOUT high to address, and

AA invalid

0.25

× T

2.5

200 TA valid to CLKOUT high

(setup time)

4.0

201 CLKOUT high to TA invalid

(hold time)

0.0

202 CLKOUT high to data out active

0.25

× T

2.5

203 CLKOUT high to data out valid 0.25 × T

+ 4.0

3.3

6.5

204 CLKOUT high to data out

invalid

0.25

× T

2.5

205 CLKOUT high to data out high

impedance

0.25

× T

2.5

206 Data in valid to CLKOUT high

(setup)

4.0

207 CLKOUT high to data in invalid

(hold)

0.0

208 CLKOUT high to RD assertion

0.75

× T

+ 4.0

8.2

11.5

209 CLKOUT high to RD

deassertion

0.0

4.0

210 CLKOUT high to WR assertion

0.5

× T

+ 4.3

[WS = 1 or

6.3

9.3

All frequencies:

WS 3]

1.3

4.3

211 CLKOUT high to WR

deassertion

0.0

3.8

Notes: 1.

WS is the number of wait states specified in the BCR.

The asynchronous delays specified in the expressions are valid for
DSP56362.

If WS > 1, WR assertion refers to the next rising edge of CLKOUT.

External bus synchronous timings should be used only for reference
to the clock and not for relative timings.

T198 and T199 are valid for Address Trace mode if the ATE bit in
the OMR is set. Use the status of BR (See T212) to determine
whether the access referenced by A0A23 is internal or external,
when this mode is enabled

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2-46

DSP56362 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

Arbitration Timings

Table 2-18 Arbitration Bus Timings

No.

Characteristics

Expression

100 MHz

Unit

Min Max

212 CLKOUT high to BR assertion/

deassertion

1.0

4.0

213 BG asserted/deasserted to

CLKOUT high (setup)

4.0

214 CLKOUT high to BG deasserted/

asserted (hold)

0.0

215 BB deassertion to CLKOUT high

(input setup)

4.0

216 CLKOUT high to BB assertion

(input hold)

0.0

217 CLKOUT high to BB assertion

(output)

1.0

4.0

218 CLKOUT high to BB deassertion

(output)

1.0

4.0

219 BB high to BB high impedance

(output)

4.5

220 CLKOUT high to address and

controls active

0.25

× T

2.5

221 CLKOUT high to address and

controls high impedance

0.25

× T

2.5

222 CLKOUT high to AA active

0.25

× T

2.5

223 CLKOUT high to AA deassertion

0.25

× T

+ 4.0 3.2

6.5

224 CLKOUT high to AA high

impedance

0.75

× T

7.5

Notes:

The asynchronous delays specified in the expressions are valid for
DSP56362.

T212 is valid for Address Trace mode when the ATE bit in the OMR is
set. BR is deasserted for internal accesses and asserted for external
accesses.

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Specifications

External Memory Expansion Port (Port A)

MOTOROLA

DSP56362 Advance Information

2-49

Figure 2-24 Bus Release Timings Case 2 (BRT Bit in OMR Set)

Table 2-19 Asynchronous Bus Arbitration timing

No.

Characteristics

Expression

100 MHz

Unit

Min

Max

250

BB assertion window from BG
input negation.

2 .5* Tc + 5

251

Delay from BB assertion to BG
assertion

2 * Tc + 5

Comments:

Bit 13 in the OMR register must be set to enter Asynchro-
nous Arbitration mode

At 100 MHz it is recommended to use Asynchronous Arbi-
tration mode.

If Asynchronous Arbitration mode is active, none of the tim-
ings in

Table 2-19

is required.

In order to guarantee timings 250, and 251, it is recommend-
ed to assert BG inputs to different 56300 devices (on the
same bus) in a non overlap manner as shown in

Figure

2-25

A0A17

AA0AA3

CLKOUT

RD, WR

223

218

219

214

212

213

221

224

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2-50

DSP56362 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

Figure 2-25 Asynchronous Bus Arbitration Timing

Figure 2-26 Asynchronous Bus Arbitration Timing

Background explanation for Asynchronous Bus Arbitration:

The asynchronous bus arbitration is enabled by internal synchronization circuits on BG, and BB inputs.
These synchronization circuits add delay from the external signal until it is exposed to internal logic. As a
result of this delay, a 56300 part may assume mastership and assert BB, for some time after BG is
negated. This is the reason for timing 250.

Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is
exposed to other 56300 components which are potential masters on the same bus. If BG input is asserted
before that time, a situation of BG asserted, and BB negated, may cause another 56300 component to
assume mastership at the same time. Therefore some non-overlap period between one BG input active to
another BG input active, is required. Timing 251 ensures that such a situation is avoided.

BG1

250

251

BG2

BG1

BG2

250+251

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Specifications

Parallel Host Interface (HDI08) Timing

MOTOROLA

DSP56362 Advance Information

2-51

PARALLEL HOST INTERFACE (HDI08) TIMING

Table 2-20 Host Interface (HDI08) Timing

1, 2

No.

Characteristics

Expression

100 MHz

Unit

Min Max

317 Read data strobe assertion width

HACK read assertion width

+ 9.9

19.9

318 Read data strobe deassertion width

HACK read deassertion width

9.9

319

Read data strobe deassertion width

after "Last

Data Register" reads

5,6

, or between two

consecutive CVR, ICR, or ISR reads

HACK deassertion width after "Last Data
Register" reads

5,6

2.5

× T

+ 6.6 31.6

320 Write data strobe assertion width

HACK write assertion width

13.2

321

Write data strobe deassertion width

HACK write deassertion width
· after ICR, CVR and "Last Data Register"

writes

2.5

× T

+ 6.6

31.6

· after IVR writes, or
· after TXH:TXM writes (with HBE=0), or

after TXL:TXM writes (with HBE=1)

16.5

322 HAS assertion width

9.9

323

HAS deassertion to data strobe assertion

0.0

324

Host data input setup time before write data
strobe deassertion

Host data input setup time before HACK write
deassertion

9.9

325

Host data input hold time after write data strobe
deassertion

Host data input hold time after HACK write
deassertion

3.3

326

Read data strobe assertion to output data active
from high impedance

HACK read assertion to output data active from
high impedance

3.3

327 Read data strobe assertion to output data valid

HACK read assertion to output data valid

24.2

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2-52

DSP56362 Advance Information

MOTOROLA

Specifications

Parallel Host Interface (HDI08) Timing

328

Read data strobe deassertion to output data
high impedance

HACK read deassertion to output data high
impedance

9.9

329

Output data hold time after read data strobe
deassertion

Output data hold time after HACK read
deassertion

3.3

330 HCS assertion to read data strobe deassertion

+9.9

19.9

331 HCS assertion to write data strobe deassertion

9.9

332 HCS assertion to output data valid

19.1

333 HCS hold time after data strobe deassertion

0.0

334 Address (AD7AD0) setup time before HAS

deassertion (HMUX=1)

4.7

335 Address (AD7AD0) hold time after HAS

deassertion (HMUX=1)

3.3

336

A10A8 (HMUX=1), A2A0 (HMUX=0), HR/W
setup time before data strobe assertion

· Read

· Write

4.7

337 A10A8 (HMUX=1), A2A0 (HMUX=0), HR/W

hold time after data strobe deassertion

3.3

338

Delay from read data strobe deassertion to host
request assertion for "Last Data Register" read

5, 10

339

Delay from write data strobe deassertion to host
request assertion for "Last Data Register"
write

5, 8, 10

× T

340

Delay from data strobe assertion to host request
deassertion for "Last Data Register" read or
write (HROD = 0)

5, 9, 10

19.1

341

Delay from data strobe assertion to host request
deassertion for "Last Data Register" read or
write (HROD = 1, open drain Host Request)

5, 9,

10, 11

300.

Table 2-20 Host Interface (HDI08) Timing

1, 2

(Continued)

No.

Characteristics

Expression

100 MHz

Unit

Min Max

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Specifications

Parallel Host Interface (HDI08) Timing

MOTOROLA

DSP56362 Advance Information

2-53

342

Delay from DMA HACK deassertion to HOREQ
assertion
· For "Last Data Register" read

× T

+ 19.1

39.1

· For "Last Data Register" write

1.5

× T

+ 19.1 34.1

· For other cases

0.0

343

Delay from DMA HACK assertion to HOREQ
deassertion
· HROD = 0

20.2

344

Delay from DMA HACK assertion to HOREQ
deassertion for "Last Data Register" read or
write
· HROD = 1, open drain Host Request

5, 11

300.

Notes:

See Host Port Usage Considerations in the DSP56362 User Design Manual.

In the timing diagrams below, the controls pins are drawn as active low. The pin
polarity is programmable.

= 3.3 V

± 0.16 V; T

0°C to +100°C, C

= 50 pF

The read data strobe is HRD in the dual data strobe mode and HDS in the single
data strobe mode.

The "last data register" is the register at address $7, which is the last location to be
read or written in data transfers. This is RXL/TXL in the little endian mode (HBE = 0),
or RXH/TXH in the big endian mode (HBE = 1).

This timing is applicable only if a read from the "last data register" is followed by a
read from the RXL, RXM, or RXH registers without first polling RXDF or HREQ bits,
or waiting for the assertion of the HOREQ signal.

This timing is applicable only if two consecutive reads from one of these registers
are executed.

The write data strobe is HWR in the dual data strobe mode and HDS in the single
data strobe mode.

The data strobe is host read (HRD) or host write (HWR) in the dual data strobe
mode and host data strobe (HDS) in the single data strobe mode.

10. The host request is HOREQ in the single host request mode and HRRQ and HTRQ

in the double host request mode.

11. In this calculation, the host request signal is pulled up by a 4.7 k

resistor in the

open-drain mode.

Table 2-20 Host Interface (HDI08) Timing

1, 2

(Continued)

No.

Characteristics

Expression

100 MHz

Unit

Min Max

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2-58

DSP56362 Advance Information

MOTOROLA

Specifications

Serial Host Interface SPI Protocol Timing

Figure 2-33 Host DMA Read Timing Diagram

SERIAL HOST INTERFACE SPI PROTOCOL TIMING

Table 2-21 Serial Host Interface SPI Protocol Timing

No.

Characteristics

Mode

Filter

Mode

Expression

100MHz

Unit

Min

Max

140 Tolerable spike width

on clock or data in

Bypassed

Narrow

Wide

100

141 Minimum serial clock

cycle =

SPICC

(min)

Master

Bypassed

×T

+46

106

Narrow

×T

+152

212

Wide

×T

+223

283

326

317

318

327

328

329

Data
Valid

HOREQ

(Output)

HACK

(Input)

H0-H7

(Output)

RXH
Read

343

342

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Specifications

Serial Host Interface SPI Protocol Timing

MOTOROLA

DSP56362 Advance Information

2-59

142 Serial clock high period

Master

Bypassed

0.5

×t

SPICC

Narrow

0.5

×t

SPICC

Wide

0.5

×t

SPICC

131

Slave

Bypassed

2.5

×T

+12

Narrow

2.5

×T

+102

127

Wide

2.5

×T

+189

214

143 Serial clock low period

Master

Bypassed

0.5

×t

SPICC

Narrow

0.5

×t

SPICC

Wide

0.5

×t

SPICC

131

Slave

Bypassed

2.5

×T

+12

Narrow

2.5

×T

+102

127

Wide

2.5

×T

+189

214

144 Serial clock rise/fall

time

Master

Slave

2000

146

SS assertion to first
SCK edge CPHA = 0

Slave

Bypassed

3.5

×T

+15

Narrow

Wide

CPHA = 1

Slave

Bypassed

Narrow

Wide

147 Last SCK edge to SS

not asserted

slave

Bypassed

Narrow

102

Wide

189

148

Data input valid to SCK
edge (data input set-up
time)

Master

/Slave

Bypassed

Narrow

MAX{(20-T

), 0}

Wide

MAX{(40-T

), 0}

149

SCK last sampling
edge to data input not
valid

Master

/Slave

Bypassed

2.5

×T

+10

Narrow

2.5

×T

+30

Wide

2.5

×T

+50

150 SS assertion to data

out active

Slave

151 SS deassertion to data

high impedance

Slave

152

SCK edge to data out
valid (data out delay
time)

Master

/Slave

Bypassed

×T

+33

Narrow

×T

+123

143

Wide

×T

+210

230

Table 2-21 Serial Host Interface SPI Protocol Timing (Continued)

No.

Characteristics

Mode

Filter

Mode

Expression

100MHz

Unit

Min

Max

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2-60

DSP56362 Advance Information

MOTOROLA

Specifications

Serial Host Interface SPI Protocol Timing

153

SCK edge to data out
not valid
(data out hold time)

Master

/Slave

Bypassed

Narrow

+55

Wide

+106

116

154 SS assertion to data

out valid (CPHA = 0)

Slave

+33

157

First SCK sampling
edge to HREQ output
deassertion

Slave

Bypassed

2.5

×T

+30

Narrow

2.5

×T

+120

145

Wide

2.5

×T

+217

242

158

Last SCK sampling
edge to HREQ output
not deasserted
(CPHA = 1)

Slave

Bypassed

2.5

×T

+30

Narrow

2.5

×T

+80

105

Wide

2.5

×T

+136

161

159

SS deassertion to
HREQ output not
deasserted (CPHA = 0)

Slave

2.5

×T

+30

160 SS deassertion pulse

width (CPHA = 0)

Slave

161 HREQ in assertion to

first SCK edge

Master

Bypassed

0.5

× t

SPICC

2.5

×T

+43

121

Narrow

0.5

×t

SPICC

2.5

×T

+43

174

Wide

0.5

×t

SPICC

2.5

×T

+43

209

162

HREQ in deassertion
to last SCK sampling
edge (HREQ in set-up
time) (CPHA = 1)

Master

163

First SCK edge to
HREQ in not asserted
(HREQ in hold time)

Master

Note:

Periodically sampled, not 100% tested

Table 2-21 Serial Host Interface SPI Protocol Timing (Continued)

No.

Characteristics

Mode

Filter

Mode

Expression

100MHz

Unit

Min

Max

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2-66

DSP56362 Advance Information

MOTOROLA

Specifications

Serial Host Interface (SHI) I

C Protocol Timing

SERIAL HOST INTERFACE (SHI) I

C PROTOCOL TIMING

Table 2-22 SHI I

C Protocol Timing

Standard I

No.

Characteristics

Symbol/

Expression

Standard Fast-Mode

Unit

Min

Max

Min

Max

Tolerable spike width on SCL or SDA

Filters bypassed

Narrow filters enabled

Wide filters enabled

100

171 SCL clock frequency

SCL

100

400

kHz

172 Bus free time

BUF

4.7

1.3

µs

173 Start condition set-up time

SU;STA

4.7

0.6

µs

174 Start condition hold time

HD;STA

4.0

0.6

µs

175 SCL low period

LOW

4.7

1.3

µs

176 SCL high period

HIGH

4.0

1.3

µs

177 SCL and SDA rise time

1000 20 + 0.1

300

178 SCL and SDA fall time

300

20 + 0.1

300

179 Data set-up time

SU;DAT

250

100

180 Data hold time

HD;DAT

0.0

0.9

µs

181 Stop condition set-up time

SU;STO

4.0

0.6

µs

182 Capacitive load for each line

400

183

DSP clock frequency

DSP

Filters bypassed

10.6

28.5

MHz

Narrow filters enabled

11.8

39.7

MHz

Wide filters enabled

13.1

61.0

MHz

184 HREQ in deassertion to last SCL edge

(HREQ in set-up time)

SU;RQI

0.0

186

First SCL sampling edge to HREQ
output deassertion

NG;RQO

Filters bypassed 2

+ 30

Narrow filters enabled 2

+ 120

140

Wide filters enabled 2

+ 208

228

187

Last SCL edge to HREQ output not
deasserted

AS;RQO

Filters bypassed 2

+ 30

Narrow filters enabled 2

+ 80

100

Wide filters enabled 2

+ 135

155

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Specifications

Serial Host Interface (SHI) I

C Protocol Timing

MOTOROLA

DSP56362 Advance Information

2-67

Programming the Serial Clock

The programmed serial clock cycle, T

CCP

, is specified by the value of the HDM[5:0] and HRS bits of the

HCKR (SHI clock control register).

The expression for T

CCP

= [T

× 2 × (HDM[7:0] + 1) × (7 × (1 HRS) + 1)]

where

HRS is the prescaler rate select bit. When HRS is cleared, the fixed

divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed.

HDM[7:0] are the divider modulus select bits.

A divide ratio from 1 to 64 (HDM[5:0] = 0 to $3F) may be selected.

In I

C mode, the user may select a value for the programmed serial clock cycle from

× T

(if HDM[5:0] = $02 and HRS = 1)

4096

× T

(if HDM[7:0] = $FF and HRS = 0)

The programmed serial clock cycle (T

CCP

), SCL rise time (T

), and the filters selected should be chosen

in order to achieve the desired SCL frequency, as shown in

Table 2-23

188

HREQ in assertion to first SCL edge

AS;RQI

0.5

CCP

0.5

- 21

Filters bypassed

4327

927

Narrow filters enabled

4282

882

Wide filters enabled

4238

838

Note:

(min) = 1.5 k¾

Table 2-22 SHI I

C Protocol Timing (Continued)

Standard I

No.

Characteristics

Symbol/

Expression

Standard Fast-Mode

Unit

Min

Max

Min

Max

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2-68

DSP56362 Advance Information

MOTOROLA

Specifications

Serial Host Interface (SHI) I

C Protocol Timing

EXAMPLE:

For DSP clock frequency of 100 MHz (i.e. T

= 10ns), operating in a standard-mode I

C environment

SCL

= 100 KHz (i.e. T

SCL

= 10

µs), T

= 1000ns), with filters bypassed

CCP

= 10

µs - 2.5×10ns - 45ns - 1000ns = 8930ns

Choosing HRS = 0 gives

HDM[7:0] = 8930ns / (2

× 10ns× 8) - 1 = 55.8

Thus the HDM[7:0] value should be programmed to $38 (=56).

Figure 2-39 I

C Timing

Table 2-23 SCL Serial Clock Cycle generated as Master

Filters bypassed

CCP

+ 2.5

+ 45ns +

Narrow filters enabled

CCP

+ 2.5

+ 135ns +

Wide filters enabled

CCP

+ 2.5

+ 223ns +

Start

SCL

HREQ

SDA

ACK

MSB

LSB

Stop

171

Stop

173

176

175

177

178

180

179

172

186

182

183

189

174

188

184

187

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Specifications

Enhanced Serial Audio Interface Timing

MOTOROLA

DSP56362 Advance Information

2-69

ENHANCED SERIAL AUDIO INTERFACE TIMING

Table 2-24 Enhanced Serial Audio Interface Timing

No.

Characteristics

1, 2, 3

Symbol Expression

100 MHz

Cond-ition

Unit

Min Max

430 Clock cycle

SSICC

4 x T

40.0 --

i ck

RXC:3 xT

x ck

TXC:

MAX

[3xT

454

]

x ck

431

Clock high period
· For internal clock

× T

- 10.0 10.0 --

· For external clock

1.5

× T

15.0 --

432

Clock low period
· For internal clock

× T

- 10.0 10.0 --

· For external clock

1.5

× T

15.0 --

433 RXC rising edge to FSR out (bl)

high

-- 37.0

x ck

-- 22.0

i ck a

434 RXC rising edge to FSR out (bl) low

-- 37.0

x ck

-- 22.0

i ck a

435 RXC rising edge to FSR out (wr)

high

-- 39.0

x ck

-- 24.0

i ck a

436 RXC rising edge to FSR out (wr)

low

39.0

x ck

-- 24.0

i ck a

437 RXC rising edge to FSR out (wl)

high

-- 36.0

x ck

-- 21.0

i ck a

438 RXC rising edge to FSR out (wl)

low

-- 37.0

x ck

-- 22.0

i ck a

439

Data in setup time before RXC
(TXC in synchronous mode) falling
edge

0.0

x ck

19.0 --

i ck

440 Data in hold time after RXC falling

edge

5.0

x ck

3.0

i ck

441 FSR input (bl, wr) high before

RXC falling edge

23.0 --

x ck

1.0

i ck a

442 FSR input (wl) high before RXC

falling edge

1.0

x ck

23.0 --

i ck a

443 FSR input hold time after RXC

falling edge

3.0

x ck

0.0

i ck a

444 Flags input setup before RXC

falling edge

0.0

x ck

19.0 --

i ck s

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2-70

DSP56362 Advance Information

MOTOROLA

Specifications

Enhanced Serial Audio Interface Timing

445 Flags input hold time after RXC

falling edge

6.0

x ck

0.0

i ck s

446 TXC rising edge to FST out (bl)

high

-- 29.0

x ck

-- 15.0

i ck

447 TXC rising edge to FST out (bl) low

-- 31.0

x ck

-- 17.0

i ck

448 TXC rising edge to FST out (wr)

high

-- 31.0

x ck

-- 17.0

i ck

449 TXC rising edge to FST out (wr)

low

-- 33.0

x ck

-- 19.0

i ck

450 TXC rising edge to FST out (wl)

high

-- 30.0

x ck

-- 16.0

i ck

451 TXC rising edge to FST out (wl) low

-- 31.0

x ck

-- 17.0

i ck

452 TXC rising edge to data out enable

from high impedance

-- 31.0

x ck

-- 17.0

i ck

453 TXC rising edge to transmitter drive

enable assertion

-- 34.0

x ck

-- 20.0

i ck

454 TXC rising edge to data out valid

23 + 0.5

× T

21.0

-- 28.0

x ck

-- 21.0

i ck

455 TXC rising edge to data out high

impedance

-- 31.0

x ck

-- 16.0

i ck

456 TXC rising edge to transmitter drive

enable deassertion

-- 34.0

x ck

-- 20.0

i ck

457 FST input (bl, wr) setup time before

TXC falling edge

2.0

x ck

21.0 --

i ck

458 FST input (wl) to data out enable

from high impedance

-- 27.0

459 FST input (wl) to transmitter drive

enable assertion

-- 31.0

460 FST input (wl) setup time before

TXC falling edge

2.0

x ck

21.0 --

i ck

461 FST input hold time after TXC

falling edge

4.0 ----

x ck

0.0

i ck

462 Flag output valid after TXC rising

edge

-- 32.0

x ck

-- 18.0

i ck

463 HCKR/HCKT clock cycle

40.0 --

Table 2-24 Enhanced Serial Audio Interface Timing (Continued)

No.

Characteristics

1, 2, 3

Symbol Expression

100 MHz

Cond-ition

Unit

Min Max

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Specifications

Enhanced Serial Audio Interface Timing

MOTOROLA

DSP56362 Advance Information

2-71

464 HCKT input rising edge to TXC

output

-- 27.5

465 HCKR input rising edge to RXC

output

-- 27.5

Notes:

= 3.3 V

± 0.16 V; T

0°C to +100°C, C

= 50 pF

i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode

(asynchronous implies that TXC and RXC are two different clocks)

i ck s = internal clock, synchronous mode

(synchronous implies that TXC and RXC are the same clock)

bl = bit length
wl = word length
wr = word length relative

TXC(SCKT pin) = transmit clock
RXC(SCKR pin) = receive clock
FST(FST pin) = transmit frame sync
FSR(FSR pin) = receive frame sync
HCKT(HCKT pin) = transmit high frequency clock
HCKR(HCKR pin) = receive high frequency clock

For the internal clock, the clock cycle at the pin is defined by Icyc and the ESAI control registers.

The word-relative frame sync signal waveform relative to the clock operates in the same manner
as the bit-length frame sync signal waveform, but spreads from one serial clock before first bit
clock (same as bit length frame sync signal), until the one before last bit clock of the first word in
frame.

Periodically sampled and not 100% tested

Table 2-24 Enhanced Serial Audio Interface Timing (Continued)

No.

Characteristics

1, 2, 3

Symbol Expression

100 MHz

Cond-ition

Unit

Min Max

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2-72

DSP56362 Advance Information

MOTOROLA

Specifications

Enhanced Serial Audio Interface Timing

Figure 2-40 ESAI Transmitter Timing

Last Bit

See Note

TXC

(Input/Output)

FST (Bit)

Out

FST (Word)

Out

Data Out

Transmitter

Drive Enable

FST (Bit) In

FST (Word) In

Flags Out

Note:

In network mode, output flag transitions can occur at the start of each time slot
within the frame. In normal mode, the output flag state is asserted for the entire
frame period.

First Bit

430

432

446

447

450

451

455

454

452

459

456

453

461

457

458

460

461

462

431

AA0490

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2-74

DSP56362 Advance Information

MOTOROLA

Specifications

Digital Audio Transmitter Timing

Figure 2-43 ESAI HCKR Timing

DIGITAL AUDIO TRANSMITTER TIMING

Table 2-25 Digital Audio Transmitter Timing

No.

Characteristic

Expression

100 MHz

Unit

Min

Max

ACI frequency (see note)

MHz

220

ACI period

× T

221

ACI high duration

0.5

× T

222

ACI low duration

0.5

× T

223

ACI rising edge to ADO valid

1.5

× T

Note:

In order to assure proper operation of the DAX, the ACI frequency should be
less than 1/2 of the DSP56362 internal clock frequency. For example, if the
DSP56362 is running at 100 MHz internally, the ACI frequency should be less
than 50 MHz.

HCKR

SCKR (output)

465

463

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Specifications

Timer Timing

MOTOROLA

DSP56362 Advance Information

2-75

Figure 2-44 Digital Audio Transmitter Timing

TIMER TIMING

Table 2-26 Timer Timing

No.

Characteristics

Expression

100 MHz

Unit

Min Max

480 TIO Low

× T

+ 2.0

22.0

481 TIO High

× T

+ 2.0

22.0

482 Timer setup time from TIO (Input)

assertion to CLKOUT rising edge

9.0

10.0

483

Synchronous timer delay time from
CLKOUT rising edge to the external
memory access address out valid
caused by first interrupt instruction
execution

10.25

× T

+ 1.0

103.

484

CLKOUT rising edge to TIO (Output)
assertion
· Minimum

0.5

× T

+ 3.5

8.5

· Maximum

0.5

× T

+ 19.8

24.8

485

CLKOUT rising edge to TIO (Output)
deassertion

· Minimum

60.5

× T

+ 3.5

8.5

· Maximum

0.5

× T

+ 19.0

24.8

Note:

= 3.3 V

± 0.16 V; T

0°C to +100°C, C

= 50 pF

ACI

ADO

220

223

AA1280

221

222

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2-76

DSP56362 Advance Information

MOTOROLA

Specifications

GPIO Timing

Figure 2-45 TIO Timer Event Input Restrictions

Figure 2-46 Timer Interrupt Generation

Figure 2-47 External Pulse Generation

GPIO TIMING

Table 2-27 GPIO Timing

No.

Characteristics

Expression

100 MHz

Unit

Min Max

490 CLKOUT edge to GPIO out valid (GPIO

out delay time)

31.0

491 CLKOUT edge to GPIO out not valid

(GPIO out hold time)

3.0

TIO

481

480

AA0492

CLKOUT

TIO (Input)

First Interrupt Instruction Execution

Address

482

483

AA0493

CLKOUT

TIO (Output)

484

485

AA0494

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Specifications

GPIO Timing

MOTOROLA

DSP56362 Advance Information

2-77

Figure 2-48 GPIO Timing

492 GPIO In valid to CLKOUT edge (GPIO

in set-up time)

12.0

493 CLKOUT edge to GPIO in not valid

(GPIO in hold time)

0.0

494 Fetch to CLKOUT edge before GPIO

change

6.75

× T

67.5

495 GPIO out rise time

496 GPIO out fall time

Note:

= 3.3 V

± 0.16 V; T

0°C to +100°C, C

= 50 pF

Table 2-27 GPIO Timing (Continued)

No.

Characteristics

Expression

100 MHz

Unit

Min Max

Valid

GPIO

(Input)

GPIO

(Output)

CLKOUT

(Output)

Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO
and R0 contains the address of GPIO data register.

A0A17

490

491

492

494

493

AA0495

GPIO

(Output)

495

496

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2-78

DSP56362 Advance Information

MOTOROLA

Specifications

JTAG Timing

JTAG TIMING

Figure 2-49 Test Clock Input Timing Diagram

Table 2-28 JTAG Timing

No.

Characteristics

All frequencies

Unit

Min Max

500 TCK frequency of operation (1/(T

× 3); maximum 22 MHz)

0.0

22.0

MHz

501 TCK cycle time in Crystal mode

45.0

502 TCK clock pulse width measured at 1.5 V

20.0

503 TCK rise and fall times

0.0

3.0

504 Boundary scan input data setup time

5.0

505 Boundary scan input data hold time

24.0

506 TCK low to output data valid

0.0

40.0

507 TCK low to output high impedance

0.0

40.0

508 TMS, TDI data setup time

5.0

509 TMS, TDI data hold time

25.0

510 TCK low to TDO data valid

0.0

44.0

511 TCK low to TDO high impedance

0.0

44.0

512 TRST assert time

100.0

513 TRST setup time to TCK low

40.0

Notes:

= 3.3 V

± 0.16V; T

0°C to +100°C, C

= 50 pF

All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.

TCK

(Input)

501

502

503

AA0496

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2-80

DSP56362 Advance Information

MOTOROLA

Specifications

OnCE Module TimIng

Figure 2-52 TRST Timing Diagram

CE MODULE TIMING

Figure 2-53 OnCE--Debug Request

OnCE Module Timing

No.

Characteristics

Expression

100 MHz

Unit

Min Max

500 TCK frequency of operation

1/(T

× 3),

max 22.0 MHz

0.0 22.0 MHz

514 DE assertion time in order to enter

Debug mode

1.5

× T

+ 10.0

25.0

515

Response time when DSP56362 is
executing NOP instructions from
internal memory

5.5

× T

+ 30.0

85.0

516 Debug acknowledge assertion time

× T

+ 10.0

40.0

Note:

= 3.3 V

± 0.16 V; T

0°C to +100°C, C

= 50 pF

TCK

(Input)

TRST

(Input)

513

512

AA0499

516

515

514

AA0500

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3-2

DSP56362 Advance Information

MOTOROLA

Packaging

Pin-out and Package Information

LQFP Package Description

Top view of the LQFP package is shown in

Figure 3-1

with its pin-outs. The LQFP package mechanical

drawing is shown in

Figure 3-2

Figure 3-1 DSP56362 Thin Quad Flat Pack (LQFP), Top View

REQ

CCS

HCK

CCQL

CCQH

HDS

HRW

ACK

REQ

CCS

HCS

HAD4

CCH

GND

HAD3

HAD2

HAD1

HAD0

RESET

CCP

PCAP

GND

VCCQH

AA3

AA2

CAS

GND

EXTAL

CCQL

CCC

GNDC

CLKOUT

PINIT

CCC

GND

AA1

AA0

D7
D8

CCD

GND

D10

D11

D12
D13
D14

CCD

GND

D15
D16
D17
D18
D19

CCQL

GND

D20

CCD

GND

D21
D22
D23

TRST

TDO

TDI

TCK

TMS

MOSI
MISO

109

(Top View)

Orientation Mark

CCA

CCQL

CCQ

CCD

AA0301

MODD
MODC

MODB
MODA

Note:

Because of size constraints in this figure, only one name is shown for multiplexed pins. Refer to

Table 3-1

and

Table 3-2

for detailed information about pin functions and signal names.

DSP56362

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MOTOROLA

DSP56362 Advance Information

3-3

Table 3-1 DSP56362 LQFP Signal Identification by Pin Number

Pin

No.

Signal Name

Pin
No.

Signal Name

Pin
No.

Signal Name

SCK/SCL

26 GND

AA2/RAS2

SS/HA2

27 ADO or PD1

CAS

HREQ

28 ACI or PD0

SDO0 or PC11

29 TIO0

GND

SDO1 or PC10

30 HCS/HCS, HA10, or PB13

EXTAL

SDO2/SDI3 or PC9

31 HA2, HA9, or PB10

CCQL

SDO3/SDI2 or PC8

32 HA1, HA8, or PB9

CCC

CCS

33 HA0, HAS/HAS, or PB8

GND

34 H7, HAD7, or PB7

CLKOUT

SDO4/SDI1 or PC7

35 H6, HAD6, or PB6

NC (not connected)

SDO5/SDI0 or PC6

36 H5, HAD5, or PB5

PINIT/NMI

FST or PC4

37 H4, HAD4, or PB4

FSR or PC1

38 V

CCH

SCKT or PC3

39 GND

SCKR or PC0

40 H3, HAD3, or PB3

CCC

HCKT or PC5

41 H2, HAD2, or PB2

GND

HCKR or PC2

42 H1, HAD1, or PB1

CCQL

43 H0, HAD0, or PB0

GND

44 RESET

AA1/RAS1

CCQH

45 V

CCP

AA0/RAS0

HDS/HDS, HWR/HWR, or
PB12

46 PCAP

HRW, HRD/HRD, or PB11

47 GND

HACK/HACK,
HRRQ/HRRQ, or PB15

48 GND

HOREQ/HOREQ,
HTRQ/HTRQ, or PB14

49 V

CCQH

CCA

CCS

50 AA3/RAS3

GND

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3-4

DSP56362 Advance Information

MOTOROLA

Packaging

Pin-out and Package Information

A17

122

D16

100

123

D17

101

124

D18

102

125

D19

CCA

103

CCD

126

CCQL

GND

104

GND

127

GND

105

128

D20

106

129

CCD

107

130

GND

108

131

D21

CCA

109

132

D22

GND

110

133

D23

A10

111

CCD

134

MODD/IRQD

A11

112

GND

135

MODC/IRQC

GND

113

136

MODB/IRQB

CCQL

114

D10

137

MODA/IRQA

A12

115

D11

138

TRST

A13

116

D12

139

TDO

A14

117

D13

140

TDI

CCQH

118

D14

141

TCK

GND

119

CCD

142

TMS

A15

120

GND

143

MOSI/HA0

A16

121

D15

144

MISO/SDA

Note:

Signal names are based on configured functionality. Most pins supply a single signal. Some pins
provide a signal with dual functionality, such as the MODx/IRQx pins that select an operating mode
after RESET is deasserted, but act as interrupt lines during operation. Some signals have configurable
polarity; these names are shown with and without overbars, such as HAS/HAS. Some pins have two or
more configurable functions; names assigned to these pins indicate the function for a specific
configuration. For example, pin 34 is data line H7 in nonmultiplexed bus mode, data/address line HAD7
in multiplexed bus mode, or GPIO line PB7 when the GPIO function is enabled for this pin.

Table 3-2 DSP56362 LQFP Signal Identification by Name

Signal Name

Pin
No.

Signal Name

Pin
No.

Signal Name

Pin
No.

not connected

D13

117

GND

D14

118

GND

D15

121

GND

Table 3-1 DSP56362 LQFP Signal Identification by Pin Number (Continued)

Pin

No.

Signal Name

Pin
No.

Signal Name

Pin
No.

Signal Name

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MOTOROLA

DSP56362 Advance Information

3-5

A10

D16

122

GND

A11

D17

123

GND

127

A12

D18

124

GND

A13

D19

125

GND

A14

102

A15

D20

128

A16

D21

131

A17

D22

132

D23

133

105

106

107

108

HA0

109

HA0

143

110

HA1

113

HA10

AA0

HA2

AA1

EXTAL

HA2

AA2

FSR

HA8

AA3

FST

HA9

ACI

GND

HACK/HACK

ADO

GND

HAD0

GND

HAD1

GND

HAD2

GND

HAD3

CAS

GND

HAD4

CLKOUT

GND

104

HAD5

100

GND

112

HAD6

101

GND

120

HAD7

D10

114

GND

130

HAS/HAS

D11

115

GND

HCS/HCS

D12

116

GND

HDS/HDS

Table 3-2 DSP56362 LQFP Signal Identification by Name (Continued)

Signal Name

Pin
No.

Signal Name

Pin
No.

Signal Name

Pin
No.

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3-6

DSP56362 Advance Information

MOTOROLA

Packaging

Pin-out and Package Information

HOREQ/HOREQ

PB9

SDO3

HRD/HRD

PC0

SDO4

HREQ

PC1

SDO5

HRRQ/HRRQ

PC10

HRW

PC11

HCKR

PC2

TCK

141

HCKT

PC3

TDI

140

HTRQ/HTRQ

PC4

TDO

139

HWR/HWR

PC5

TIO0

IRQA

137

PC6

TMS

142

IRQB

136

PC7

TRST

138

IRQC

135

PC8

CCA

IRQD

134

PC9

CCA

MISO

144

PCAP

CCA

MODA

137

PD0

CCC

MODB

136

PD1

CCC

MODC

135

PINIT

CCD

103

MODD

134

RAS0

CCD

111

MOSI

143

RAS1

CCD

119

NMI

RAS2

CCD

129

PB0

RAS3

CCH

PB1

CCP

PB10

RESET

CCQH

PB11

SCK

CCQH

PB12

SCKR

CCQH

PB13

SCKT

CCQL

PB14

SCL

CCQL

PB15

SDA

144

CCQL

PB2

SDI0

CCQL

126

PB3

SDI1

CCS

PB4

SDI2

CCS

PB5

SDI3

PB6

SDO0

PB7

SDO1

PB8

SDO2

Table 3-2 DSP56362 LQFP Signal Identification by Name (Continued)

Signal Name

Pin
No.

Signal Name

Pin
No.

Signal Name

Pin
No.

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DSP56362 Advance Information

4-1

SECTION 4

DESIGN CONSIDERATIONS

THERMAL DESIGN CONSIDERATIONS

An estimation of the chip junction temperature, T

, in °C can be obtained from the following equation:

Where:

= ambient temperature °C

qJA

= package junction-to-ambient thermal resistance °C/W

= power dissipation in package W

Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance
and a case-to-ambient thermal resistance.

Where:

= package junction-to-ambient thermal resistance °C/W

= package junction-to-case thermal resistance °C/W

= package case-to-ambient thermal resistance °C/W

is device-related and cannot be influenced by the user. The user controls the thermal environment to

change the case-to-ambient thermal resistance, R

. For example, the user can change the air flow

around the device, add a heat sink, change the mounting arrangement on the printed circuit board (PCB),
or otherwise change the thermal dissipation capability of the area surrounding the device on a PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated
through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations
where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of
the device thermal performance may need the additional modeling capability of a system level thermal
simulation tool.

The thermal performance of plastic packages is more dependent on the temperature of the PCB to which
the package is mounted. Again, if the estimations obtained from R

do not satisfactorily answer whether

the thermal performance is adequate, a system level model may be appropriate.

A complicating factor is the existence of three common ways for determining the junction-to-case thermal
resistance in plastic packages.

To minimize temperature variation across the surface, the thermal resistance is measured from
the junction to the outside surface of the package (case) closest to the chip mounting area when
that surface has a proper heat sink.

To define a value approximately equal to a junction-to-board thermal resistance, the thermal
resistance is measured from the junction to where the leads are attached to the case.

TJ TA PD RJA

(

)

RJA RJC RCA

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4-2

DSP56362 Advance Information

MOTOROLA

Design Considerations

Electrical Design Considerations

If the temperature of the package case (T

) is determined by a thermocouple, the thermal

resistance is computed using the value obtained by the equation
(T

)/P

As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using
the first definition. From a practical standpoint, that value is also suitable for determining the junction
temperature from a case thermocouple reading in forced convection environments. In natural convection,
using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple
reading on the case of the package will estimate a junction temperature slightly hotter than actual
temperature. Hence, the new thermal metric, thermal characterization parameter or

, has been defined

to be (T

)/P

. This value gives a better estimate of the junction temperature in natural convection

when using the surface temperature of the package. Remember that surface temperature readings of
packages are subject to significant errors caused by inadequate attachment of the sensor to the surface
and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge
thermocouple wire and bead to the top center of the package with thermally conductive epoxy.

ELECTRICAL DESIGN CONSIDERATIONS

Use the following list of recommendations to assure correct DSP operation:

Provide a low-impedance path from the board power supply to each V

pin on the DSP and from

the board ground to each GND pin.

Use at least six 0.010.1

µF bypass capacitors positioned as close as possible to the four sides of

the package to connect the V

power source to GND.

Ensure that capacitor leads and associated printed circuit traces that connect to the chip V

and

GND pins are less than 1.2 cm (0.5 inch) per capacitor lead.

Use at least a four-layer PCB with two inner layers for V

and GND.

Because the DSP output signals have fast rise and fall times, PCB trace lengths should be
minimal. This recommendation particularly applies to the address and data buses as well as the
IRQA, IRQB, IRQC, IRQD, TA, and BG pins. Maximum PCB trace lengths on the order of 15 cm
(6 inches) are recommended.

CAUTION

This device contains circuitry protecting
against damage due to high static voltage or
electrical fields. However, normal precautions
should be taken to avoid exceeding maximum
voltage ratings. Reliability of operation is
enhanced if unused inputs are tied to an
appropriate logic voltage level (e.g., either
GND or V

). The suggested value for a

pullup or pulldown resistor is 10 k ohm.

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Design Considerations

Power Consumption Considerations

MOTOROLA

DSP56362 Advance Information

4-3

Consider all device loads as well as parasitic capacitance due to PCB traces when calculating
capacitance. This is especially critical in systems with higher capacitive loads that could create
higher transient currents in the V

and GND circuits.

All inputs must be terminated (i.e., not allowed to float) using CMOS levels, except for the pins with
internal pull-up resistors (TRST, TMS, DE, TCK, and TDI).

Take special care to minimize noise levels on the V

CCP

, GND

, and GND

pins.

If multiple DSP56362 devices are on the same board, check for cross-talk or excessive spikes on
the supplies due to synchronous operation of the devices.

RESET must be asserted when the chip is powered up. A stable EXTAL signal should be supplied
before deassertion of RESET.

At power-up, ensure that the voltage difference between the 5 V tolerant pins and the chip V

never exceeds 3.95 V.

POWER CONSUMPTION CONSIDERATIONS

Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current
consumption are described in this section. Most of the current consumed by CMOS devices is alternating
current (ac), which is charging and discharging the capacitances of the pins and internal nodes.

Current consumption is described by the following formula:

where

C = node/pin capacitance

V = voltage swing

f = frequency of node/pin toggle

The maximum internal current (I

CCI

max) value reflects the typical possible switching of the internal buses

on best-case operation conditions, which is not necessarily a real application case. The typical internal
current (I

CCItyp

) value reflects the average switching of the internal buses on typical operating conditions.

For applications that require very low current consumption, do the following:

Set the EBD bit when not accessing external memory.

Minimize external memory accesses and use internal memory accesses.

Example 1 Current Consumption

For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, and with a 100 MHz clock, toggling
at its maximum possible rate (50 MHz), the current consumption is

C V f

50 10

3.3

8.25mA

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4-4

DSP56362 Advance Information

MOTOROLA

Design Considerations

PLL Performance Issues

Minimize the number of pins that are switching.

Minimize the capacitive load on the pins.

Connect the unused inputs to pull-up or pull-down resistors.

Disable unused peripherals.

Disable unused pin activity (e.g., CLKOUT, XTAL).

One way to evaluate power consumption is to use a current per MIPS measurement methodology to
minimize specific board effects (i.e., to compensate for measured board current not caused by the DSP). A
benchmark power consumption test algorithm is listed in Appendix A. Use the test algorithm, specific test
current measurements, and the following equation to derive the current per MIPS value.

where :

typF2

= current at F2

typF1

= current at F1

F2 = high frequency (any specified operating frequency)
F1 = low frequency (any specified operating frequency lower than F2)

Note: F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1

could be 33 MHz. The degree of difference between F1 and F2 determines the
amount of precision with which the current rating can be determined for an application.

PLL PERFORMANCE ISSUES

The following explanations should be considered as general observations on expected PLL behavior.
There is no testing that verifies these exact numbers. These observations were measured on a limited
number of parts and were not verified over the entire temperature and voltage ranges.

Phase Skew Performance

The phase skew of the PLL is defined as the time difference between the falling edges of EXTAL and
CLKOUT for a given capacitive load on CLKOUT, over the entire process, temperature, and voltage
ranges. As defined in Figure 2-1, for input frequencies greater than 15 MHz and the MF

4, this skew is

greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is not guaranteed. However, for
MF < 10 and input frequencies greater than 10 MHz, this skew is between

-1.4 ns and +3.2 ns.

Phase Jitter Performance

The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL and
CLKOUT for a given device in specific temperature, voltage, input frequency, MF, and capacitive load on
CLKOUT. These variations are a result of the PLL locking mechanism. For input frequencies greater than
15 MHz and MF

4, this jitter is less than ±0.6 ns; otherwise, this jitter is not guaranteed. However, for MF

< 10 and input frequencies greater than 10 MHz, this jitter is less than

±2 ns.

I MIPS

I MHz

ItypF2 ItypF1

(

)

F2 F1

(

)

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Design Considerations

Host Port Considerations

MOTOROLA

DSP56362 Advance Information

4-5

Frequency Jitter Performance

The frequency jitter of the PLL is defined as the variation of the frequency of CLKOUT. For small MF (MF <
10) this jitter is smaller than 0.5%. For mid-range MF (10 < MF < 500) this jitter is between 0.5% and
approximately 2%. For large MF (MF > 500), the frequency jitter is 23%.

Input (EXTAL) Jitter Requirements

The allowed jitter on the frequency of EXTAL is 0.5%. If the rate of change of the frequency of EXTAL is
slow (i.e., it does not jump between the minimum and maximum values in one cycle) or the frequency of
the jitter is fast (i.e., it does not stay at an extreme value for a long time), then the allowed jitter can be 2%.
The phase and frequency jitter performance results are only valid if the input jitter is less than the
prescribed values.

HOST PORT CONSIDERATIONS

Careful synchronization is required when reading multi-bit registers that are written by another
asynchronous system. This synchronization is a common problem when two asynchronous systems are
connected, as they are in the host interface. The following paragraphs present considerations for proper
operation.

Host Programming Considerations

Unsynchronized Reading of Receive Byte Registers--When reading the receive byte
registers, receive register high (RXH), receive register middle (RXM), or receive register low
(RXL), the host interface programmer should use interrupts or poll the receive register data full
(RXDF) flag that indicates whether data is available. This ensures that the data in the receive byte
registers will be valid.

Overwriting Transmit Byte Registers--The host interface programmer should not write to the
transmit byte registers, transmit register high (TXH), transmit register middle (TXM), or transmit
register low (TXL), unless the transmit register data empty (TXDE) bit is set, indicating that the
transmit byte registers are empty. This ensures that the transmit byte registers will transfer valid
data to the host receive (HRX) register.

Synchronization of Status Bits from DSP to Host--HC, HOREQ, DMA, HF3, HF2, TRDY,
TXDE, and RXDF status bits are set or cleared from inside the DSP and read by the host
processor (refer to the user's manual for descriptions of these status bits). The host can read these
status bits very quickly without regard to the clock rate used by the DSP, but the state of the bit
could be changing during the read operation. This is not generally a system problem, because the bit
will be read correctly in the next pass of any host polling routine.

However, if the host asserts HEN for more than timing number 31, with
a minimum cycle time of timing number 31 + 32, then these status bits are guaranteed to be

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4-6

DSP56362 Advance Information

MOTOROLA

Design Considerations

Host Port Considerations

stable. Exercise care when reading status bits HF3 and HF2 as an encoded pair. If the DSP
changes HF3 and HF2 from 00 to 11, there is a small probability that the host could read the bits
during the transition and receive 01 or 10 instead of 11. If the combination of HF3 and HF2 has
significance, the host could read the wrong combination. Therefore, read the bits twice and
check for consensus.

Overwriting the Host Vector--The host interface programmer should change the host vector
(HV) register only when the host command (HC) bit is clear. This ensures that the DSP interrupt
control logic will receive a stable vector.

Cancelling a Pending Host Command Exception--The host processor may elect to clear the
HC bit to cancel the host command exception request at any time before it is recognized by the
DSP. Because the host does not know exactly when the exception will be recognized (due to
exception processing synchronization and pipeline delays), the DSP may execute the host
command exception after the HC bit is cleared. For these reasons, the HV bits must not be
changed at the same time that the HC bit is cleared.

Variance in the Host Interface Timing--The host interface (HDI) may vary (e.g. due to the PLL
lock time at reset). Therefore, a host which attempts to load (bootstrap) the DSP should first make
sure that the part has completed its HI port programming (e.g., by setting the INIT bit in ICR then
polling it and waiting it to be cleared, then reading the ISR or by writing the TREQ/RREQ together
with the INIT and then polling INIT, ISR, and the HOREQ pin).

DSP Programming Considerations

Synchronization of Status Bits from Host to DSP--DMA, HF1, HF0, HCP, HTDE, and HRDF
status bits are set or cleared by the host processor side of the interface. These bits are individually
synchronized to the DSP clock. (Refer to the user's manual for descriptions of these status bits.)

Reading HF0 and HF1 as an Encoded Pair--Care must be exercised when reading status bits
HF0 and HF1 as an encoded pair, (i.e., the four combinations 00, 01, 10, and 11 each have
significance). A very small probability exists that the DSP will read the status bits synchronized
during transition. Therefore, HF0 and HF1 should be read twice and checked for consensus.

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MOTOROLA

DSP56362 Advance Information

Appendix A-1

APPENDIX A

POWER CONSUMPTION BENCHMARK

The following benchmark program permits evaluation of DSP power usage in a test situation. It enables
the PLL, disables the external clock, and uses repeated
multiply-accumulate instructions with a set of synthetic DSP application data to emulate intensive
sustained DSP operation.

;********************************************************************;**

******************************************************************

;* ;* CHECKS

Typical Power Consumption

;********************************************************************

page

200,55,0,0,0

nolist

I_VEC EQU $000000

; Interrupt vectors for program debug only

START EQU $8000

; MAIN (external) program starting address

INT_PROG

EQU $100 ; INTERNAL program memory starting address

INT_XDAT

EQU $0

; INTERNAL X-data memory starting address

INT_YDAT

EQU $0

; INTERNAL Y-data memory starting address

INCLUDE "ioequ.asm"

INCLUDE "intequ.asm"

list

org

P:START

;

movep #$0123FF,x:M_BCR; BCR: Area 3 : 1 w.s (SRAM)

; Default: 1 w.s (SRAM)

;

movep

#$0d0000,x:M_PCTL

; XTAL disable

; PLL enable

; CLKOUT disable

;

; Load the program

;

move

#INT_PROG,r0

move

#PROG_START,r1

#(PROG_END-PROG_START),PLOAD_LOOP

move

p:(r1)+,x0

move

x0,p:(r0)+

nop

PLOAD_LOOP

;

; Load the X-data

;

move

#INT_XDAT,r0

move

#XDAT_START,r1

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Appendix A-2

DSP56362 Advance Information

MOTOROLA

Power Consumption Benchmark

#(XDAT_END-XDAT_START),XLOAD_LOOP

move

p:(r1)+,x0

move

x0,x:(r0)+

XLOAD_LOOP

;

; Load the Y-data

;

move

#INT_YDAT,r0

move

#YDAT_START,r1

#(YDAT_END-YDAT_START),YLOAD_LOOP

move

p:(r1)+,x0

move

x0,y:(r0)+

YLOAD_LOOP

;

jmp

INT_PROG

PROG_START

move

#$0,r0

move

#$0,r4

move

#$3f,m0

move

#$3f,m4

;

clr

move

#$0,x0

move

#$0,x1

move

#$0,y0

move

#$0,y1

bset

#4,omr

; ebd

;

sbr

dor

#60,_end

mac

x0,y0,a

x:(r0)+,x1

y:(r4)+,y1

mac

x1,y1,a

x:(r0)+,x0

y:(r4)+,y0

add

a,b

mac

x0,y0,a

x:(r0)+,x1

mac

x1,y1,a

y:(r4)+,y0

move

b1,x:$ff

_end

bra

sbr

nop

PROG_END

nop

XDAT_START

;

org

x:0

$262EB9

$86F2FE

$E56A5F

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Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
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Power Consumption Benchmark

MOTOROLA

DSP56362 Advance Information

Appendix A-3

$616CAC

$8FFD75

$9210A

$A06D7B

$CEA798

$8DFBF1

$A063D6

$6C6657

$C2A544

$A3662D

$A4E762

$84F0F3

$E6F1B0

$B3829

$8BF7AE

$63A94F

$EF78DC

$242DE5

$A3E0BA

$EBAB6B

$8726C8

$CA361

$2F6E86

$A57347

$4BE774

$8F349D

$A1ED12

$4BFCE3

$EA26E0

$CD7D99

$4BA85E

$27A43F

$A8B10C

$D3A55

$25EC6A

$2A255B

$A5F1F8

$2426D1

$AE6536

$CBBC37

$6235A4

$37F0D

$63BEC2

$A5E4D3

$8CE810

$3FF09

$60E50E

$CFFB2F

$40753C

$8262C5

$CA641A

$EB3B4B

$2DA928

$AB6641

r
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Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

Appendix A-4

DSP56362 Advance Information

MOTOROLA

Power Consumption Benchmark

$28A7E6

$4E2127

$482FD4

$7257D

$E53C72

$1A8C3

$E27540

XDAT_END

YDAT_START

;

org

y:0

$5B6DA

$C3F70B

$6A39E8

$81E801

$C666A6

$46F8E7

$AAEC94

$24233D

$802732

$2E3C83

$A43E00

$C2B639

$85A47E

$ABFDDF

$F3A2C

$2D7CF5

$E16A8A

$ECB8FB

$4BED18

$43F371

$83A556

$E1E9D7

$ACA2C4

$8135AD

$2CE0E2

$8F2C73

$432730

$A87FA9

$4A292E

$A63CCF

$6BA65C

$E06D65

$1AA3A

$A1B6EB

$48AC48

$EF7AE1

$6E3006

$62F6C7

$6064F4

$87E41D

$CB2692

$2C3863

$C6BC60

r
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Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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MOTOROLA

DSP56362 Advance Information

Appendix B-1

APPENDIX B

IBIS MODEL

[IBIS ver]

2.1

[File name]

56362.ibs

[File Rev]

0.0

[Date]

29/6/2000

[Component]

56362

[Manufacturer]

Motorola

[Package]

|variable

typ

min

max

R_pkg

45m

22m

75m

L_pkg

2.5nH

1.1nH

4.3nH

C_pkg

1.3pF

1.2pF

1.4pF

[Pin]signal_name model_name

1 sck

ip5b_io

2 ss_

ip5b_io

3 hreq_

ip5b_io

4 sdo0

ip5b_io

5 sdo1

ip5b_io

6 sdoi23

ip5b_io

7 sdoi32

ip5b_io

8 svcc

power

9 sgnd

gnd

10 sdoi41

ip5b_io

11 sdoi50

ip5b_io

12 fst

ip5b_io

13 fsr

ip5b_io

14 sckt

ip5b_io

15 sckr

ip5b_io

16 hsckt

ip5b_io

17 hsckr

ip5b_io

18 qvccl

power

19 gnd

gnd

20 qvcch

power

21 hp12

ip5b_io

22 hp11

ip5b_io

23 hp15

ip5b_io

24 hp14

ip5b_io

25 svcc

power

26 sgnd

gnd

27 ado

ip5b_io

28 aci

ip5b_io

29 tio

ip5b_io

30 hp13

ip5b_io

31 hp10

ip5b_io

32 hp9

ip5b_io

33 hp8

ip5b_io

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IBIS Model

Appendix B-2

DSP56362 Advance Information

MOTOROLA

34 hp7

ip5b_io

35 hp6

ip5b_io

36 hp5

ip5b_io

37 hp4

ip5b_io

38 svcc

power

39 sgnd

gnd

40 hp3

ip5b_io

41 hp2

ip5b_io

42 hp1

ip5b_io

43 hp0

ip5b_io

44 ires_

ip5b_i

45 pvcc

power

46 pcap

power

47 pgnd

gnd

48 pgnd1

gnd

49 qvcch

power

50 aa3

icbc_o

51 aa2

icbc_o

52 cas_

icbc_o

53 de_

ipbw_io

54 qgnd

gnd

55 cxtldis_

iexlh_i

56 qvccl

power

57 cvcc

power

58 cgnd

gnd

59 clkout

icba_o

61 nmi_

ipbw_i

62 ta_

icbc_o

63 br_

icbc_o

64 bb_

icbc_o

65 cvcc

power

66 cgnd

gnd

67 wr_

icbc_o

68 rd_

icbc_o

69 aa1

icbc_o

70 aa0

icbc_o

71 bg_

icbc_o

72 eab0

icba_o

73 eab1

icba_o

74 avcc

power

75 agnd

gnd

76 eab2

icba_o

77 eab3

icba_o

78 eab4

icba_o

79 eab5

icba_o

80 avcc

power

81 agnd

gnd

82 eab6

icba_o

83 eab7

icba_o

84 eab8

icba_o

85 eab9

icba_o

86 avcc

power

87 agnd

gnd

88 eab10

icba_o

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IBIS Model

MOTOROLA

DSP56362 Advance Information

Appendix B-3

89 eab11

icba_o

90 qgnd

gnd

91 qvcc

power

92 eab12

icba_o

93 eab13

icba_o

94 eab14

icba_o

95 qvcch

power

96 agnd

gnd

97 eab15

icba_o

98 eab16

icba_o

99 eab17

icba_o

100 edb0

icba_io

101 edb1

icba_io

102 edb2

icba_io

103 dvcc

power

104 dgnd

gnd

105 edb3

icba_io

106 edb4

icba_io

107 edb5

icba_io

108 edb6

icba_io

109 edb7

icba_io

110 edb8

icba_io

111 dvcc

power

112 dgnd

gnd

113 edb9

icba_io

114 edb10

icba_io

115 edb11

icba_io

116 edb12

icba_io

117 edb13

icba_io

118 edb14

icba_io

119 dvcc

power

120 dgnd

gnd

121 edb15

icba_io

122 edb16

icba_io

123 edb17

icba_io

124 edb18

icba_io

125 edb19

icba_io

126 qvccl

power

127 qgnd

gnd

128 edb20

icba_io

129 dvcc

power

130 dgnd

gnd

131 edb21

icba_io

132 edb22

icba_io

133 edb23

icba_io

134 irqd_

ip5b_i

135 irqc_

ip5b_i

136 irqb_

ip5b_i

137 irqa_

ip5b_i

138 trst_

ip5b_i

139 tdo

ip5b_o

140 tdi

ip5b_i

141 tck

ip5b_i

142 tms

ip5b_i

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Freescale Semiconductor, Inc.

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IBIS Model

Appendix B-4

DSP56362 Advance Information

MOTOROLA

143 mosi

ip5b_io

144 sda

ip5b_io

[Model]

ip5b_i

Model_type

Input

Polarity

Non-Inverting

Vinl= 0.8000v

Vinh= 2.000v

C_comp

5.00pF

[Voltage Range]

3.3v

3.6v

[GND_clamp]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

-5.21e+02

-3.65e+02

-5.18e+02

-3.10e+00

-4.69e+02

-3.30e+02

-4.67e+02

-2.90e+00

-4.18e+02

-2.94e+02

-4.16e+02

-2.70e+00

-3.67e+02

-2.59e+02

-3.65e+02

-2.50e+00

-3.16e+02

-2.23e+02

-3.14e+02

-2.30e+00

-2.65e+02

-1.88e+02

-2.63e+02

-2.10e+00

-2.14e+02

-1.52e+02

-2.12e+02

-1.90e+00

-1.63e+02

-1.17e+02

-1.61e+02

-1.70e+00

-1.13e+02

-9.25e+01

-1.10e+02

-1.50e+00

-7.83e+01

-6.88e+01

-7.58e+01

-1.30e+00

-4.43e+01

-4.52e+01

-4.17e+01

-1.10e+00

-1.02e+01

-2.15e+01

-7.67e+00

-9.00e-01

-9.69e-03

-1.18e+00

-7.81e-03

-7.00e-01

-2.83e-04

-5.70e-03

-8.42e-04

-5.00e-01

-1.35e-06

-4.53e-05

-1.00e-05

-3.00e-01

-1.31e-09

-3.74e-07

-8.58e-09

-1.00e-01

-2.92e-11

-3.00e-09

-3.64e-11

0.000e+00

-2.44e-11

-5.14e-10

-2.79e-11

[Model]

ip5b_io

Model_type

I/O

Polarity

Non-Inverting

Vinl= 0.8000v

Vinh= 2.000v

C_comp

5.00pF

[Voltage Range]

3.3v

3.6v

[Pulldown]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

-5.21e+02

-3.65e+02

-5.18e+02

-3.10e+00

-4.69e+02

-3.30e+02

-4.67e+02

-2.90e+00

-4.18e+02

-2.94e+02

-4.16e+02

-2.70e+00

-3.67e+02

-2.59e+02

-3.65e+02

-2.50e+00

-3.16e+02

-2.23e+02

-3.14e+02

-2.30e+00

-2.65e+02

-1.88e+02

-2.63e+02

-2.10e+00

-2.14e+02

-1.52e+02

-2.12e+02

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Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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IBIS Model

MOTOROLA

DSP56362 Advance Information

Appendix B-5

-1.90e+00

-1.63e+02

-1.17e+02

-1.61e+02

-1.70e+00

-1.13e+02

-9.25e+01

-1.10e+02

-1.50e+00

-7.83e+01

-6.88e+01

-7.58e+01

-1.30e+00

-4.43e+01

-4.52e+01

-4.17e+01

-1.10e+00

-1.02e+01

-2.15e+01

-7.69e+00

-9.00e-01

-5.10e-02

-1.18e+00

-5.63e-02

-7.00e-01

-3.65e-02

-2.25e-02

-4.28e-02

-5.00e-01

-2.65e-02

-1.38e-02

-3.12e-02

-3.00e-01

-1.62e-02

-8.35e-03

-1.91e-02

-1.00e-01

-5.49e-03

-2.80e-03

-6.52e-03

1.000e-01

5.377e-03

2.744e-03

6.427e-03

3.000e-01

1.516e-02

7.871e-03

1.823e-02

5.000e-01

2.370e-02

1.252e-02

2.869e-02

7.000e-01

3.098e-02

1.667e-02

3.776e-02

9.000e-01

3.700e-02

2.026e-02

4.544e-02

1.100e+00

4.175e-02

2.324e-02

5.171e-02

1.300e+00

4.531e-02

2.553e-02

5.660e-02

1.500e+00

4.779e-02

2.709e-02

6.023e-02

1.700e+00

4.935e-02

2.803e-02

6.271e-02

1.900e+00

5.013e-02

2.851e-02

6.419e-02

2.100e+00

5.046e-02

2.876e-02

6.494e-02

2.300e+00

5.063e-02

2.892e-02

6.525e-02

2.500e+00

5.075e-02

2.904e-02

6.540e-02

2.700e+00

5.085e-02

2.912e-02

6.549e-02

2.900e+00

5.090e-02

2.876e-02

6.555e-02

3.100e+00

4.771e-02

2.994e-02

6.561e-02

3.300e+00

4.525e-02

3.321e-02

6.182e-02

3.500e+00

4.657e-02

3.570e-02

6.049e-02

3.700e+00

4.904e-02

3.801e-02

6.178e-02

3.900e+00

5.221e-02

4.029e-02

6.450e-02

4.100e+00

5.524e-02

4.253e-02

6.659e-02

4.300e+00

5.634e-02

4.463e-02

6.867e-02

4.500e+00

5.751e-02

4.645e-02

6.970e-02

4.700e+00

5.634e-02

4.786e-02

6.938e-02

4.900e+00

5.648e-02

4.881e-02

6.960e-02

5.100e+00

5.664e-02

4.912e-02

6.983e-02

5.300e+00

5.679e-02

4.795e-02

7.005e-02

5.500e+00

5.693e-02

4.679e-02

7.026e-02

5.700e+00

5.707e-02

4.688e-02

7.049e-02

5.900e+00

5.722e-02

4.700e-02

7.074e-02

6.100e+00

5.741e-02

4.712e-02

7.105e-02

6.300e+00

5.766e-02

4.723e-02

7.147e-02

6.500e+00

5.801e-02

4.733e-02

7.205e-02

6.600e+00

5.824e-02

4.737e-02

7.242e-02

[Pullup]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

2.922e-04

2.177e-04

4.123e-04

-3.10e+00

2.881e-04

2.175e-04

4.021e-04

-2.90e+00

2.853e-04

2.173e-04

3.946e-04

-2.70e+00

2.836e-04

2.172e-04

3.893e-04

-2.50e+00

2.825e-04

2.171e-04

3.857e-04

-2.30e+00

2.819e-04

2.170e-04

3.834e-04

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.

IBIS Model

Appendix B-6

DSP56362 Advance Information

MOTOROLA

-2.10e+00

2.815e-04

2.169e-04

3.820e-04

-1.90e+00

2.813e-04

2.167e-04

3.812e-04

-1.70e+00

2.812e-04

2.520e-04

3.808e-04

-1.50e+00

2.811e-04

3.078e-02

3.806e-04

-1.30e+00

2.810e-04

2.684e-02

3.804e-04

-1.10e+00

2.809e-04

2.277e-02

3.802e-04

-9.00e-01

2.808e-04

1.864e-02

3.801e-04

-7.00e-01

2.997e-04

1.447e-02

3.799e-04

-5.00e-01

1.750e-02

1.031e-02

3.797e-04

-3.00e-01

1.048e-02

6.181e-03

3.776e-04

-1.00e-01

3.487e-03

2.084e-03

4.568e-03

1.000e-01

-3.40e-03

-2.03e-03

-4.22e-03

3.000e-01

-9.69e-03

-5.71e-03

-1.24e-02

5.000e-01

-1.52e-02

-8.99e-03

-1.95e-02

7.000e-01

-2.02e-02

-1.19e-02

-2.61e-02

9.000e-01

-2.46e-02

-1.43e-02

-3.21e-02

1.100e+00

-2.84e-02

-1.62e-02

-3.73e-02

1.300e+00

-3.14e-02

-1.77e-02

-4.18e-02

1.500e+00

-3.37e-02

-1.88e-02

-4.55e-02

1.700e+00

-3.55e-02

-1.95e-02

-4.85e-02

1.900e+00

-3.68e-02

-2.00e-02

-5.09e-02

2.100e+00

-3.78e-02

-2.04e-02

-5.27e-02

2.300e+00

-3.85e-02

-2.07e-02

-5.41e-02

2.500e+00

-3.91e-02

-2.10e-02

-5.51e-02

2.700e+00

-3.96e-02

-2.12e-02

-5.60e-02

2.900e+00

-4.01e-02

-2.15e-02

-5.67e-02

3.100e+00

-4.04e-02

-2.17e-02

-5.74e-02

3.300e+00

-4.08e-02

-2.18e-02

-5.79e-02

3.500e+00

-4.11e-02

-2.20e-02

-5.84e-02

3.700e+00

-4.14e-02

-2.78e-02

-5.89e-02

3.900e+00

-4.17e-02

-1.20e+00

-5.94e-02

4.100e+00

-4.32e-02

-2.15e+01

-5.98e-02

4.300e+00

-4.08e-01

-4.52e+01

-6.10e-02

4.500e+00

-2.73e+01

-6.89e+01

-6.84e-02

4.700e+00

-6.13e+01

-9.25e+01

-7.73e+00

4.900e+00

-9.54e+01

-1.17e+02

-4.18e+01

5.100e+00

-1.38e+02

-1.52e+02

-7.59e+01

5.300e+00

-1.89e+02

-1.88e+02

-1.11e+02

5.500e+00

-2.40e+02

-2.23e+02

-1.61e+02

5.700e+00

-2.91e+02

-2.59e+02

-2.12e+02

5.900e+00

-3.42e+02

-2.94e+02

-2.63e+02

6.100e+00

-3.93e+02

-3.30e+02

-3.14e+02

6.300e+00

-4.44e+02

-3.65e+02

6.500e+00

-4.95e+02

-4.01e+02

-4.16e+02

6.600e+00

-5.21e+02

-4.18e+02

-4.41e+02

[GND_clamp]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

-5.21e+02

-3.65e+02

-5.18e+02

-3.10e+00

-4.69e+02

-3.30e+02

-4.67e+02

-2.90e+00

-4.18e+02

-2.94e+02

-4.16e+02

-2.70e+00

-3.67e+02

-2.59e+02

-3.65e+02

-2.50e+00

-3.16e+02

-2.23e+02

-3.14e+02

r
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r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

IBIS Model

MOTOROLA

DSP56362 Advance Information

Appendix B-7

-2.30e+00

-2.65e+02

-1.88e+02

-2.63e+02

-2.10e+00

-2.14e+02

-1.52e+02

-2.12e+02

-1.90e+00

-1.63e+02

-1.17e+02

-1.61e+02

-1.70e+00

-1.13e+02

-9.25e+01

-1.10e+02

-1.50e+00

-7.83e+01

-6.88e+01

-7.58e+01

-1.30e+00

-4.43e+01

-4.52e+01

-4.17e+01

-1.10e+00

-1.02e+01

-2.15e+01

-7.67e+00

-9.00e-01

-9.69e-03

-1.18e+00

-7.81e-03

-7.00e-01

-2.83e-04

-5.70e-03

-8.42e-04

-5.00e-01

-1.35e-06

-4.53e-05

-1.00e-05

-3.00e-01

-1.31e-09

-3.74e-07

-8.58e-09

-1.00e-01

-2.92e-11

-3.00e-09

-3.64e-11

0.000e+00

-2.44e-11

-5.14e-10

-2.79e-11

[Ramp]

R_load = 50.00

|voltage

I(typ)

I(min)

I(max)

dV/dt_r

1.030/0.465

0.605/0.676

1.320/0.366

dV/dt_f

1.290/0.671

0.829/0.122

1.520/0.431

[Model]

ip5b_o

Model_type

3-state

Polarity

Non-Inverting

C_comp

5.00pF

[Voltage Range]

3.3v

3.6v

[Pulldown]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

-5.21e+02

-3.65e+02

-5.18e+02

-3.10e+00

-4.69e+02

-3.30e+02

-4.67e+02

-2.90e+00

-4.18e+02

-2.94e+02

-4.16e+02

-2.70e+00

-3.67e+02

-2.59e+02

-3.65e+02

-2.50e+00

-3.16e+02

-2.23e+02

-3.14e+02

-2.30e+00

-2.65e+02

-1.88e+02

-2.63e+02

-2.10e+00

-2.14e+02

-1.52e+02

-2.12e+02

-1.90e+00

-1.63e+02

-1.17e+02

-1.61e+02

-1.70e+00

-1.13e+02

-9.25e+01

-1.10e+02

-1.50e+00

-7.83e+01

-6.88e+01

-7.58e+01

-1.30e+00

-4.43e+01

-4.52e+01

-4.17e+01

-1.10e+00

-1.02e+01

-2.15e+01

-7.69e+00

-9.00e-01

-5.10e-02

-1.18e+00

-5.63e-02

-7.00e-01

-3.65e-02

-2.25e-02

-4.28e-02

-5.00e-01

-2.65e-02

-1.38e-02

-3.12e-02

-3.00e-01

-1.62e-02

-8.35e-03

-1.91e-02

-1.00e-01

-5.49e-03

-2.80e-03

-6.52e-03

1.000e-01

5.377e-03

2.744e-03

6.427e-03

3.000e-01

1.516e-02

7.871e-03

1.823e-02

r
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Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

IBIS Model

Appendix B-8

DSP56362 Advance Information

MOTOROLA

5.000e-01

2.370e-02

1.252e-02

2.869e-02

7.000e-01

3.098e-02

1.667e-02

3.776e-02

9.000e-01

3.700e-02

2.026e-02

4.544e-02

1.100e+00

4.175e-02

2.324e-02

5.171e-02

1.300e+00

4.531e-02

2.553e-02

5.660e-02

1.500e+00

4.779e-02

2.709e-02

6.023e-02

1.700e+00

4.935e-02

2.803e-02

6.271e-02

1.900e+00

5.013e-02

2.851e-02

6.419e-02

2.100e+00

5.046e-02

2.876e-02

6.494e-02

2.300e+00

5.063e-02

2.892e-02

6.525e-02

2.500e+00

5.075e-02

2.904e-02

6.540e-02

2.700e+00

5.085e-02

2.912e-02

6.549e-02

2.900e+00

5.090e-02

2.876e-02

6.555e-02

3.100e+00

4.771e-02

2.994e-02

6.561e-02

3.300e+00

4.525e-02

3.321e-02

6.182e-02

3.500e+00

4.657e-02

3.570e-02

6.049e-02

3.700e+00

4.904e-02

3.801e-02

6.178e-02

3.900e+00

5.221e-02

4.029e-02

6.450e-02

4.100e+00

5.524e-02

4.253e-02

6.659e-02

4.300e+00

5.634e-02

4.463e-02

6.867e-02

4.500e+00

5.751e-02

4.645e-02

6.970e-02

4.700e+00

5.634e-02

4.786e-02

6.938e-02

4.900e+00

5.648e-02

4.881e-02

6.960e-02

5.100e+00

5.664e-02

4.912e-02

6.983e-02

5.300e+00

5.679e-02

4.795e-02

7.005e-02

5.500e+00

5.693e-02

4.679e-02

7.026e-02

5.700e+00

5.707e-02

4.688e-02

7.049e-02

5.900e+00

5.722e-02

4.700e-02

7.074e-02

6.100e+00

5.741e-02

4.712e-02

7.105e-02

6.300e+00

5.766e-02

4.723e-02

7.147e-02

6.500e+00

5.801e-02

4.733e-02

7.205e-02

6.600e+00

5.824e-02

4.737e-02

7.242e-02

[Pullup]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

2.922e-04

2.177e-04

4.123e-04

-3.10e+00

2.881e-04

2.175e-04

4.021e-04

-2.90e+00

2.853e-04

2.173e-04

3.946e-04

-2.70e+00

2.836e-04

2.172e-04

3.893e-04

-2.50e+00

2.825e-04

2.171e-04

3.857e-04

-2.30e+00

2.819e-04

2.170e-04

3.834e-04

-2.10e+00

2.815e-04

2.169e-04

3.820e-04

-1.90e+00

2.813e-04

2.167e-04

3.812e-04

-1.70e+00

2.812e-04

2.520e-04

3.808e-04

-1.50e+00

2.811e-04

3.078e-02

3.806e-04

-1.30e+00

2.810e-04

2.684e-02

3.804e-04

-1.10e+00

2.809e-04

2.277e-02

3.802e-04

-9.00e-01

2.808e-04

1.864e-02

3.801e-04

-7.00e-01

2.997e-04

1.447e-02

3.799e-04

-5.00e-01

1.750e-02

1.031e-02

3.797e-04

-3.00e-01

1.048e-02

6.181e-03

3.776e-04

-1.00e-01

3.487e-03

2.084e-03

4.568e-03

1.000e-01

-3.40e-03

-2.03e-03

-4.22e-03

r
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r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

IBIS Model

MOTOROLA

DSP56362 Advance Information

Appendix B-9

3.000e-01

-9.69e-03

-5.71e-03

-1.24e-02

5.000e-01

-1.52e-02

-8.99e-03

-1.95e-02

7.000e-01

-2.02e-02

-1.19e-02

-2.61e-02

9.000e-01

-2.46e-02

-1.43e-02

-3.21e-02

1.100e+00

-2.84e-02

-1.62e-02

-3.73e-02

1.300e+00

-3.14e-02

-1.77e-02

-4.18e-02

1.500e+00

-3.37e-02

-1.88e-02

-4.55e-02

1.700e+00

-3.55e-02

-1.95e-02

-4.85e-02

1.900e+00

-3.68e-02

-2.00e-02

-5.09e-02

2.100e+00

-3.78e-02

-2.04e-02

-5.27e-02

2.300e+00

-3.85e-02

-2.07e-02

-5.41e-02

2.500e+00

-3.91e-02

-2.10e-02

-5.51e-02

2.700e+00

-3.96e-02

-2.12e-02

-5.60e-02

2.900e+00

-4.01e-02

-2.15e-02

-5.67e-02

3.100e+00

-4.04e-02

-2.17e-02

-5.74e-02

3.300e+00

-4.08e-02

-2.18e-02

-5.79e-02

3.500e+00

-4.11e-02

-2.20e-02

-5.84e-02

3.700e+00

-4.14e-02

-2.78e-02

-5.89e-02

3.900e+00

-4.17e-02

-1.20e+00

-5.94e-02

4.100e+00

-4.32e-02

-2.15e+01

-5.98e-02

4.300e+00

-4.08e-01

-4.52e+01

-6.10e-02

4.500e+00

-2.73e+01

-6.89e+01

-6.84e-02

4.700e+00

-6.13e+01

-9.25e+01

-7.73e+00

4.900e+00

-9.54e+01

-1.17e+02

-4.18e+01

5.100e+00

-1.38e+02

-1.52e+02

-7.59e+01

5.300e+00

-1.89e+02

-1.88e+02

-1.11e+02

5.500e+00

-2.40e+02

-2.23e+02

-1.61e+02

5.700e+00

-2.91e+02

-2.59e+02

-2.12e+02

5.900e+00

-3.42e+02

-2.94e+02

-2.63e+02

6.100e+00

-3.93e+02

-3.30e+02

-3.14e+02

6.300e+00

-4.44e+02

-3.65e+02

6.500e+00

-4.95e+02

-4.01e+02

-4.16e+02

6.600e+00

-5.21e+02

-4.18e+02

-4.41e+02

[GND_clamp]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

-5.21e+02

-3.65e+02

-5.18e+02

-3.10e+00

-4.69e+02

-3.30e+02

-4.67e+02

-2.90e+00

-4.18e+02

-2.94e+02

-4.16e+02

-2.70e+00

-3.67e+02

-2.59e+02

-3.65e+02

-2.50e+00

-3.16e+02

-2.23e+02

-3.14e+02

-2.30e+00

-2.65e+02

-1.88e+02

-2.63e+02

-2.10e+00

-2.14e+02

-1.52e+02

-2.12e+02

-1.90e+00

-1.63e+02

-1.17e+02

-1.61e+02

-1.70e+00

-1.13e+02

-9.25e+01

-1.10e+02

-1.50e+00

-7.83e+01

-6.88e+01

-7.58e+01

-1.30e+00

-4.43e+01

-4.52e+01

-4.17e+01

-1.10e+00

-1.02e+01

-2.15e+01

-7.67e+00

-9.00e-01

-9.69e-03

-1.18e+00

-7.81e-03

-7.00e-01

-2.83e-04

-5.70e-03

-8.42e-04

-5.00e-01

-1.35e-06

-4.53e-05

-1.00e-05

-3.00e-01

-1.31e-09

-3.74e-07

-8.58e-09

-1.00e-01

-2.92e-11

-3.00e-09

-3.64e-11

r
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Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

IBIS Model

Appendix B-10

DSP56362 Advance Information

MOTOROLA

0.000e+00

-2.44e-11

-5.14e-10

-2.79e-11

[Ramp]

R_load = 50.00

|voltage

I(typ)

I(min)

I(max)

dV/dt_r

1.030/0.465

0.605/0.676

1.320/0.366

dV/dt_f

1.290/0.671

0.829/0.122

1.520/0.431

[Model]

icba_io

Model_type

I/O

Polarity

Non-Inverting

Vinl= 0.8000v

Vinh= 2.000v

C_comp

5.00pF

[Voltage Range]

3.3v

3.6v

[Pulldown]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

-5.20e+02

-3.65e+02

-5.18e+02

-3.10e+00

-4.69e+02

-3.30e+02

-4.67e+02

-2.90e+00

-4.18e+02

-2.94e+02

-4.16e+02

-2.70e+00

-3.67e+02

-2.59e+02

-3.65e+02

-2.50e+00

-3.16e+02

-2.23e+02

-3.14e+02

-2.30e+00

-2.65e+02

-1.88e+02

-2.63e+02

-2.10e+00

-2.14e+02

-1.52e+02

-2.12e+02

-1.90e+00

-1.63e+02

-1.17e+02

-1.60e+02

-1.70e+00

-1.13e+02

-9.25e+01

-1.10e+02

-1.50e+00

-7.83e+01

-6.88e+01

-7.58e+01

-1.30e+00

-4.43e+01

-4.52e+01

-4.17e+01

-1.10e+00

-1.02e+01

-2.15e+01

-7.68e+00

-9.00e-01

-2.70e-02

-1.19e+00

-2.90e-02

-7.00e-01

-1.32e-02

-1.25e-02

-1.63e-02

-5.00e-01

-9.33e-03

-4.69e-03

-1.10e-02

-3.00e-01

-5.75e-03

-2.81e-03

-6.76e-03

-1.00e-01

-1.97e-03

-9.48e-04

-2.32e-03

1.000e-01

1.945e-03

9.285e-04

2.307e-03

3.000e-01

5.507e-03

2.640e-03

6.599e-03

5.000e-01

8.649e-03

4.168e-03

1.048e-02

7.000e-01

1.136e-02

5.504e-03

1.393e-02

9.000e-01

1.364e-02

6.636e-03

1.693e-02

1.100e+00

1.547e-02

7.551e-03

1.950e-02

1.300e+00

1.688e-02

8.240e-03

2.162e-02

1.500e+00

1.299e-01

6.458e-02

2.331e-02

1.700e+00

1.366e-01

6.746e-02

1.755e-01

1.900e+00

1.404e-01

6.916e-02

1.847e-01

2.100e+00

1.423e-01

7.006e-02

1.907e-01

2.300e+00

1.433e-01

7.059e-02

1.940e-01

r
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Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

IBIS Model

MOTOROLA

DSP56362 Advance Information

Appendix B-11

2.500e+00

1.440e-01

7.098e-02

1.958e-01

2.700e+00

1.445e-01

7.128e-02

1.970e-01

2.900e+00

1.450e-01

7.154e-02

1.979e-01

3.100e+00

1.454e-01

7.176e-02

1.986e-01

3.300e+00

1.458e-01

7.196e-02

1.993e-01

3.500e+00

1.461e-01

7.223e-02

1.999e-01

3.700e+00

1.464e-01

8.810e-02

2.004e-01

3.900e+00

1.469e-01

2.589e+00

2.009e-01

4.100e+00

1.490e-01

1.451e+01

2.015e-01

4.300e+00

1.501e+00

2.658e+01

2.030e-01

4.500e+00

1.813e+01

3.866e+01

2.385e-01

4.700e+00

3.540e+01

5.076e+01

9.563e+00

4.900e+00

5.269e+01

6.461e+01

2.682e+01

5.100e+00

7.541e+01

8.261e+01

4.409e+01

5.300e+00

1.012e+02

1.006e+02

6.258e+01

5.500e+00

1.270e+02

1.186e+02

8.836e+01

5.700e+00

1.527e+02

1.366e+02

1.141e+02

5.900e+00

1.785e+02

1.546e+02

1.399e+02

6.100e+00

2.043e+02

1.726e+02

1.657e+02

6.300e+00

2.301e+02

1.906e+02

1.915e+02

6.500e+00

2.559e+02

2.086e+02

2.173e+02

6.600e+00

2.688e+02

2.176e+02

2.302e+02

[Pullup]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

2.686e+02

1.905e+02

2.686e+02

-3.10e+00

2.428e+02

1.725e+02

2.428e+02

-2.90e+00

2.170e+02

1.545e+02

2.170e+02

-2.70e+00

1.912e+02

1.365e+02

1.912e+02

-2.50e+00

1.655e+02

1.185e+02

1.655e+02

-2.30e+00

1.397e+02

1.005e+02

1.397e+02

-2.10e+00

1.139e+02

8.253e+01

1.139e+02

-1.90e+00

8.814e+01

6.454e+01

8.814e+01

-1.70e+00

6.237e+01

5.068e+01

6.237e+01

-1.50e+00

4.389e+01

3.859e+01

4.389e+01

-1.30e+00

2.662e+01

2.651e+01

2.662e+01

-1.10e+00

9.360e+00

1.444e+01

9.362e+00

-9.00e-01

4.275e-02

2.518e+00

4.663e-02

-7.00e-01

8.208e-03

2.012e-02

1.070e-02

-5.00e-01

5.635e-03

3.518e-03

7.068e-03

-3.00e-01

3.370e-03

2.053e-03

4.233e-03

-1.00e-01

1.118e-03

6.789e-04

1.410e-03

1.000e-01

-1.09e-03

-6.56e-04

-1.38e-03

3.000e-01

-3.12e-03

-1.86e-03

-3.99e-03

5.000e-01

-4.96e-03

-2.93e-03

-6.39e-03

7.000e-01

-6.60e-03

-3.87e-03

-8.59e-03

9.000e-01

-8.04e-03

-4.66e-03

-1.06e-02

1.100e+00

-9.26e-03

-5.30e-03

-1.23e-02

1.300e+00

-1.03e-02

-6.55e-02

-1.38e-02

1.500e+00

-1.25e-01

-6.93e-02

-1.70e-01

1.700e+00

-1.31e-01

-7.19e-02

-1.82e-01

1.900e+00

-1.36e-01

-7.38e-02

-1.91e-01

2.100e+00

-1.40e-01

-7.53e-02

-1.97e-01

r
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I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

IBIS Model

Appendix B-12

DSP56362 Advance Information

MOTOROLA

2.300e+00

-1.42e-01

-7.65e-02

-2.03e-01

2.500e+00

-1.44e-01

-7.76e-02

-2.07e-01

2.700e+00

-1.46e-01

-7.85e-02

-2.10e-01

2.900e+00

-1.48e-01

-7.93e-02

-2.13e-01

3.100e+00

-1.49e-01

-8.00e-02

-2.15e-01

3.300e+00

-1.50e-01

-8.06e-02

-2.17e-01

3.500e+00

-1.52e-01

-8.13e-02

-2.19e-01

3.700e+00

-1.53e-01

-8.84e-02

-2.21e-01

3.900e+00

-1.54e-01

-1.26e+00

-2.22e-01

4.100e+00

-1.57e-01

-2.16e+01

-2.24e-01

4.300e+00

-5.25e-01

-4.53e+01

-2.27e-01

4.500e+00

-2.74e+01

-6.89e+01

-2.38e-01

4.700e+00

-6.14e+01

-9.26e+01

-7.90e+00

4.900e+00

-9.55e+01

-1.17e+02

-4.20e+01

5.100e+00

-1.38e+02

-1.52e+02

-7.60e+01

5.300e+00

-1.89e+02

-1.88e+02

-1.11e+02

5.500e+00

-2.40e+02

-2.23e+02

-1.61e+02

5.700e+00

-2.91e+02

-2.59e+02

-2.12e+02

5.900e+00

-3.42e+02

-2.94e+02

-2.63e+02

6.100e+00

-3.93e+02

-3.30e+02

-3.14e+02

6.300e+00

-4.44e+02

-3.65e+02

6.500e+00

-4.95e+02

-4.01e+02

-4.16e+02

6.600e+00

-5.21e+02

-4.19e+02

-4.42e+02

[GND_clamp]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

-5.20e+02

-3.65e+02

-5.18e+02

-3.10e+00

-4.69e+02

-3.30e+02

-4.67e+02

-2.90e+00

-4.18e+02

-2.94e+02

-4.16e+02

-2.70e+00

-3.67e+02

-2.59e+02

-3.65e+02

-2.50e+00

-3.16e+02

-2.23e+02

-3.14e+02

-2.30e+00

-2.65e+02

-1.88e+02

-2.63e+02

-2.10e+00

-2.14e+02

-1.52e+02

-2.12e+02

-1.90e+00

-1.63e+02

-1.17e+02

-1.60e+02

-1.70e+00

-1.13e+02

-9.25e+01

-1.10e+02

-1.50e+00

-7.83e+01

-6.88e+01

-7.58e+01

-1.30e+00

-4.43e+01

-4.52e+01

-4.17e+01

-1.10e+00

-1.02e+01

-2.15e+01

-7.67e+00

-9.00e-01

-1.22e-02

-1.18e+00

-1.17e-02

-7.00e-01

-5.18e-04

-6.62e-03

-1.56e-03

-5.00e-01

-2.43e-06

-6.64e-05

-1.80e-05

-3.00e-01

-2.33e-09

-6.35e-07

-1.54e-08

-1.00e-01

-2.10e-11

-6.31e-09

-2.99e-11

0.000e+00

-1.70e-11

-1.95e-09

-1.91e-11

[POWER_clamp]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

2.686e+02

1.905e+02

2.686e+02

-3.10e+00

2.428e+02

1.725e+02

2.428e+02

-2.90e+00

2.170e+02

1.545e+02

2.170e+02

-2.70e+00

1.912e+02

1.365e+02

1.912e+02

-2.50e+00

1.655e+02

1.185e+02

1.655e+02

r
e

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l
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t
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r
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I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

IBIS Model

MOTOROLA

DSP56362 Advance Information

Appendix B-13

-2.30e+00

1.397e+02

1.005e+02

1.397e+02

-2.10e+00

1.139e+02

8.253e+01

1.139e+02

-1.90e+00

8.814e+01

6.454e+01

8.814e+01

-1.70e+00

6.236e+01

5.068e+01

6.237e+01

-1.50e+00

4.389e+01

3.859e+01

4.389e+01

-1.30e+00

2.662e+01

2.651e+01

2.662e+01

-1.10e+00

9.358e+00

1.444e+01

9.359e+00

-9.00e-01

3.399e-02

2.517e+00

3.554e-02

-7.00e-01

3.426e-04

1.577e-02

9.211e-04

-5.00e-01

2.840e-06

7.857e-05

1.655e-05

-3.00e-01

3.401e-09

6.836e-07

1.946e-08

-1.00e-01

6.162e-11

7.379e-09

7.622e-11

0.000e+00

5.758e-11

2.438e-09

6.240e-11

[Ramp]

R_load = 50.00

|voltage

I(typ)

I(min)

I(max)

dV/dt_r

1.680/0.164

1.360/0.329

1.900/0.124

dV/dt_f

1.690/0.219

1.310/0.442

1.880/0.155

[Model]

icba_o

Model_type

3-state

Polarity

Non-Inverting

C_comp

5.00pF

[Voltage Range]

3.3v

3.6v

[Pulldown]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

-5.20e+02

-3.65e+02

-5.18e+02

-3.10e+00

-4.69e+02

-3.30e+02

-4.67e+02

-2.90e+00

-4.18e+02

-2.94e+02

-4.16e+02

-2.70e+00

-3.67e+02

-2.59e+02

-3.65e+02

-2.50e+00

-3.16e+02

-2.23e+02

-3.14e+02

-2.30e+00

-2.65e+02

-1.88e+02

-2.63e+02

-2.10e+00

-2.14e+02

-1.52e+02

-2.12e+02

-1.90e+00

-1.63e+02

-1.17e+02

-1.60e+02

-1.70e+00

-1.13e+02

-9.25e+01

-1.10e+02

-1.50e+00

-7.83e+01

-6.88e+01

-7.58e+01

-1.30e+00

-4.43e+01

-4.52e+01

-4.17e+01

-1.10e+00

-1.02e+01

-2.15e+01

-7.68e+00

-9.00e-01

-2.70e-02

-1.19e+00

-2.90e-02

-7.00e-01

-1.32e-02

-1.25e-02

-1.63e-02

-5.00e-01

-9.33e-03

-4.69e-03

-1.10e-02

-3.00e-01

-5.75e-03

-2.81e-03

-6.76e-03

-1.00e-01

-1.97e-03

-9.48e-04

-2.32e-03

1.000e-01

1.945e-03

9.285e-04

2.307e-03

3.000e-01

5.507e-03

2.640e-03

6.599e-03

r
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I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

IBIS Model

Appendix B-14

DSP56362 Advance Information

MOTOROLA

5.000e-01

8.649e-03

4.168e-03

1.048e-02

7.000e-01

1.136e-02

5.504e-03

1.393e-02

9.000e-01

1.364e-02

6.636e-03

1.693e-02

1.100e+00

1.547e-02

7.551e-03

1.950e-02

1.300e+00

1.688e-02

8.240e-03

2.162e-02

1.500e+00

1.299e-01

6.458e-02

2.331e-02

1.700e+00

1.366e-01

6.746e-02

1.755e-01

1.900e+00

1.404e-01

6.916e-02

1.847e-01

2.100e+00

1.423e-01

7.006e-02

1.907e-01

2.300e+00

1.433e-01

7.059e-02

1.940e-01

2.500e+00

1.440e-01

7.098e-02

1.958e-01

2.700e+00

1.445e-01

7.128e-02

1.970e-01

2.900e+00

1.450e-01

7.154e-02

1.979e-01

3.100e+00

1.454e-01

7.176e-02

1.986e-01

3.300e+00

1.458e-01

7.196e-02

1.993e-01

3.500e+00

1.461e-01

7.223e-02

1.999e-01

3.700e+00

1.464e-01

8.810e-02

2.004e-01

3.900e+00

1.469e-01

2.589e+00

2.009e-01

4.100e+00

1.490e-01

1.451e+01

2.015e-01

4.300e+00

1.501e+00

2.658e+01

2.030e-01

4.500e+00

1.813e+01

3.866e+01

2.385e-01

4.700e+00

3.540e+01

5.076e+01

9.563e+00

4.900e+00

5.269e+01

6.461e+01

2.682e+01

5.100e+00

7.541e+01

8.261e+01

4.409e+01

5.300e+00

1.012e+02

1.006e+02

6.258e+01

5.500e+00

1.270e+02

1.186e+02

8.836e+01

5.700e+00

1.527e+02

1.366e+02

1.141e+02

5.900e+00

1.785e+02

1.546e+02

1.399e+02

6.100e+00

2.043e+02

1.726e+02

1.657e+02

6.300e+00

2.301e+02

1.906e+02

1.915e+02

6.500e+00

2.559e+02

2.086e+02

2.173e+02

6.600e+00

2.688e+02

2.176e+02

2.302e+02

[Pullup]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

2.686e+02

1.905e+02

2.686e+02

-3.10e+00

2.428e+02

1.725e+02

2.428e+02

-2.90e+00

2.170e+02

1.545e+02

2.170e+02

-2.70e+00

1.912e+02

1.365e+02

1.912e+02

-2.50e+00

1.655e+02

1.185e+02

1.655e+02

-2.30e+00

1.397e+02

1.005e+02

1.397e+02

-2.10e+00

1.139e+02

8.253e+01

1.139e+02

-1.90e+00

8.814e+01

6.454e+01

8.814e+01

-1.70e+00

6.237e+01

5.068e+01

6.237e+01

-1.50e+00

4.389e+01

3.859e+01

4.389e+01

-1.30e+00

2.662e+01

2.651e+01

2.662e+01

-1.10e+00

9.360e+00

1.444e+01

9.362e+00

-9.00e-01

4.275e-02

2.518e+00

4.663e-02

-7.00e-01

8.208e-03

2.012e-02

1.070e-02

-5.00e-01

5.635e-03

3.518e-03

7.068e-03

-3.00e-01

3.370e-03

2.053e-03

4.233e-03

-1.00e-01

1.118e-03

6.789e-04

1.410e-03

1.000e-01

-1.09e-03

-6.56e-04

-1.38e-03

r
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l
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t
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r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

IBIS Model

MOTOROLA

DSP56362 Advance Information

Appendix B-15

3.000e-01

-3.12e-03

-1.86e-03

-3.99e-03

5.000e-01

-4.96e-03

-2.93e-03

-6.39e-03

7.000e-01

-6.60e-03

-3.87e-03

-8.59e-03

9.000e-01

-8.04e-03

-4.66e-03

-1.06e-02

1.100e+00

-9.26e-03

-5.30e-03

-1.23e-02

1.300e+00

-1.03e-02

-6.55e-02

-1.38e-02

1.500e+00

-1.25e-01

-6.93e-02

-1.70e-01

1.700e+00

-1.31e-01

-7.19e-02

-1.82e-01

1.900e+00

-1.36e-01

-7.38e-02

-1.91e-01

2.100e+00

-1.40e-01

-7.53e-02

-1.97e-01

2.300e+00

-1.42e-01

-7.65e-02

-2.03e-01

2.500e+00

-1.44e-01

-7.76e-02

-2.07e-01

2.700e+00

-1.46e-01

-7.85e-02

-2.10e-01

2.900e+00

-1.48e-01

-7.93e-02

-2.13e-01

3.100e+00

-1.49e-01

-8.00e-02

-2.15e-01

3.300e+00

-1.50e-01

-8.06e-02

-2.17e-01

3.500e+00

-1.52e-01

-8.13e-02

-2.19e-01

3.700e+00

-1.53e-01

-8.84e-02

-2.21e-01

3.900e+00

-1.54e-01

-1.26e+00

-2.22e-01

4.100e+00

-1.57e-01

-2.16e+01

-2.24e-01

4.300e+00

-5.25e-01

-4.53e+01

-2.27e-01

4.500e+00

-2.74e+01

-6.89e+01

-2.38e-01

4.700e+00

-6.14e+01

-9.26e+01

-7.90e+00

4.900e+00

-9.55e+01

-1.17e+02

-4.20e+01

5.100e+00

-1.38e+02

-1.52e+02

-7.60e+01

5.300e+00

-1.89e+02

-1.88e+02

-1.11e+02

5.500e+00

-2.40e+02

-2.23e+02

-1.61e+02

5.700e+00

-2.91e+02

-2.59e+02

-2.12e+02

5.900e+00

-3.42e+02

-2.94e+02

-2.63e+02

6.100e+00

-3.93e+02

-3.30e+02

-3.14e+02

6.300e+00

-4.44e+02

-3.65e+02

6.500e+00

-4.95e+02

-4.01e+02

-4.16e+02

6.600e+00

-5.21e+02

-4.19e+02

-4.42e+02

[GND_clamp]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

-5.20e+02

-3.65e+02

-5.18e+02

-3.10e+00

-4.69e+02

-3.30e+02

-4.67e+02

-2.90e+00

-4.18e+02

-2.94e+02

-4.16e+02

-2.70e+00

-3.67e+02

-2.59e+02

-3.65e+02

-2.50e+00

-3.16e+02

-2.23e+02

-3.14e+02

-2.30e+00

-2.65e+02

-1.88e+02

-2.63e+02

-2.10e+00

-2.14e+02

-1.52e+02

-2.12e+02

-1.90e+00

-1.63e+02

-1.17e+02

-1.60e+02

-1.70e+00

-1.13e+02

-9.25e+01

-1.10e+02

-1.50e+00

-7.83e+01

-6.88e+01

-7.58e+01

-1.30e+00

-4.43e+01

-4.52e+01

-4.17e+01

-1.10e+00

-1.02e+01

-2.15e+01

-7.67e+00

-9.00e-01

-1.22e-02

-1.18e+00

-1.17e-02

-7.00e-01

-5.18e-04

-6.62e-03

-1.56e-03

-5.00e-01

-2.43e-06

-6.64e-05

-1.80e-05

-3.00e-01

-2.33e-09

-6.35e-07

-1.54e-08

-1.00e-01

-2.10e-11

-6.31e-09

-2.99e-11

r
e

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l
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,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

IBIS Model

Appendix B-16

DSP56362 Advance Information

MOTOROLA

0.000e+00

-1.70e-11

-1.95e-09

-1.91e-11

[POWER_clamp]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

2.686e+02

1.905e+02

2.686e+02

-3.10e+00

2.428e+02

1.725e+02

2.428e+02

-2.90e+00

2.170e+02

1.545e+02

2.170e+02

-2.70e+00

1.912e+02

1.365e+02

1.912e+02

-2.50e+00

1.655e+02

1.185e+02

1.655e+02

-2.30e+00

1.397e+02

1.005e+02

1.397e+02

-2.10e+00

1.139e+02

8.253e+01

1.139e+02

-1.90e+00

8.814e+01

6.454e+01

8.814e+01

-1.70e+00

6.236e+01

5.068e+01

6.237e+01

-1.50e+00

4.389e+01

3.859e+01

4.389e+01

-1.30e+00

2.662e+01

2.651e+01

2.662e+01

-1.10e+00

9.358e+00

1.444e+01

9.359e+00

-9.00e-01

3.399e-02

2.517e+00

3.554e-02

-7.00e-01

3.426e-04

1.577e-02

9.211e-04

-5.00e-01

2.840e-06

7.857e-05

1.655e-05

-3.00e-01

3.401e-09

6.836e-07

1.946e-08

-1.00e-01

6.162e-11

7.379e-09

7.622e-11

0.000e+00

5.758e-11

2.438e-09

6.240e-11

[Ramp]

R_load = 50.00

|voltage

I(typ)

I(min)

I(max)

dV/dt_r

1.680/0.164

1.360/0.329

1.900/0.124

dV/dt_f

1.690/0.219

1.310/0.442

1.880/0.155

[Model]

icbc_o

Model_type

3-state

Polarity

Non-Inverting

C_comp

5.00pF

[Voltage Range]

3.3v

3.6v

[Pulldown]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

-5.20e+02

-3.65e+02

-5.18e+02

-3.10e+00

-4.69e+02

-3.30e+02

-4.67e+02

-2.90e+00

-4.18e+02

-2.94e+02

-4.16e+02

-2.70e+00

-3.67e+02

-2.59e+02

-3.65e+02

-2.50e+00

-3.16e+02

-2.23e+02

-3.14e+02

-2.30e+00

-2.65e+02

-1.88e+02

-2.63e+02

-2.10e+00

-2.14e+02

-1.52e+02

-2.11e+02

-1.90e+00

-1.63e+02

-1.17e+02

-1.60e+02

-1.70e+00

-1.13e+02

-9.25e+01

-1.10e+02

r
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Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

IBIS Model

MOTOROLA

DSP56362 Advance Information

Appendix B-17

-1.50e+00

-7.83e+01

-6.88e+01

-7.58e+01

-1.30e+00

-4.42e+01

-4.51e+01

-4.17e+01

-1.10e+00

-1.02e+01

-2.15e+01

-7.67e+00

-9.00e-01

-2.51e-02

-1.18e+00

-2.65e-02

-7.00e-01

-1.30e-02

-1.16e-02

-1.58e-02

-5.00e-01

-9.33e-03

-4.67e-03

-1.10e-02

-3.00e-01

-5.75e-03

-2.81e-03

-6.76e-03

-1.00e-01

-1.97e-03

-9.48e-04

-2.32e-03

1.000e-01

1.945e-03

9.285e-04

2.307e-03

3.000e-01

5.507e-03

2.640e-03

6.599e-03

5.000e-01

8.649e-03

4.168e-03

1.048e-02

7.000e-01

1.136e-02

5.504e-03

1.393e-02

9.000e-01

1.364e-02

6.636e-03

1.693e-02

1.100e+00

1.547e-02

7.551e-03

1.950e-02

1.300e+00

1.688e-02

8.240e-03

2.162e-02

1.500e+00

9.632e-02

4.783e-02

2.331e-02

1.700e+00

1.012e-01

4.994e-02

1.302e-01

1.900e+00

1.039e-01

5.118e-02

1.369e-01

2.100e+00

1.053e-01

5.184e-02

1.412e-01

2.300e+00

1.060e-01

5.223e-02

1.436e-01

2.500e+00

1.065e-01

5.251e-02

1.449e-01

2.700e+00

1.069e-01

5.274e-02

1.458e-01

2.900e+00

1.073e-01

5.293e-02

1.464e-01

3.100e+00

1.076e-01

5.309e-02

1.470e-01

3.300e+00

1.078e-01

5.324e-02

1.475e-01

3.500e+00

1.081e-01

5.344e-02

1.479e-01

3.700e+00

1.083e-01

6.705e-02

1.483e-01

3.900e+00

1.086e-01

2.529e+00

1.487e-01

4.100e+00

1.103e-01

1.438e+01

1.491e-01

4.300e+00

1.437e+00

2.638e+01

1.503e-01

4.500e+00

1.800e+01

3.839e+01

1.810e-01

4.700e+00

3.519e+01

5.041e+01

9.452e+00

4.900e+00

5.241e+01

6.419e+01

2.664e+01

5.100e+00

7.505e+01

8.210e+01

4.384e+01

5.300e+00

1.007e+02

1.000e+02

6.224e+01

5.500e+00

1.264e+02

1.179e+02

8.794e+01

5.700e+00

1.522e+02

1.359e+02

1.136e+02

5.900e+00

1.779e+02

1.538e+02

1.394e+02

6.100e+00

2.036e+02

1.717e+02

1.651e+02

6.300e+00

2.293e+02

1.896e+02

1.908e+02

6.500e+00

2.550e+02

2.075e+02

2.165e+02

6.600e+00

2.678e+02

2.165e+02

2.293e+02

[Pullup]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

2.677e+02

1.896e+02

2.677e+02

-3.10e+00

2.420e+02

1.716e+02

2.420e+02

-2.90e+00

2.163e+02

1.537e+02

2.163e+02

-2.70e+00

1.906e+02

1.358e+02

1.906e+02

-2.50e+00

1.649e+02

1.179e+02

1.649e+02

-2.30e+00

1.392e+02

9.996e+01

1.392e+02

-2.10e+00

1.135e+02

8.205e+01

1.135e+02

-1.90e+00

8.778e+01

6.413e+01

8.778e+01

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Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

IBIS Model

Appendix B-18

DSP56362 Advance Information

MOTOROLA

-1.70e+00

6.208e+01

5.035e+01

6.208e+01

-1.50e+00

4.368e+01

3.834e+01

4.368e+01

-1.30e+00

2.649e+01

2.633e+01

2.649e+01

-1.10e+00

9.302e+00

1.433e+01

9.303e+00

-9.00e-01

3.838e-02

2.477e+00

4.183e-02

-7.00e-01

8.115e-03

1.789e-02

1.045e-02

-5.00e-01

5.634e-03

3.503e-03

7.064e-03

-3.00e-01

3.370e-03

2.053e-03

4.233e-03

-1.00e-01

1.118e-03

6.789e-04

1.410e-03

1.000e-01

-1.09e-03

-6.56e-04

-1.38e-03

3.000e-01

-3.12e-03

-1.86e-03

-3.99e-03

5.000e-01

-4.96e-03

-2.93e-03

-6.39e-03

7.000e-01

-6.60e-03

-3.87e-03

-8.59e-03

9.000e-01

-8.04e-03

-4.66e-03

-1.06e-02

1.100e+00

-9.26e-03

-5.30e-03

-1.23e-02

1.300e+00

-1.03e-02

-4.75e-02

-1.41e-02

1.500e+00

-9.03e-02

-5.02e-02

-1.23e-01

1.700e+00

-9.49e-02

-5.21e-02

-1.31e-01

1.900e+00

-9.84e-02

-5.34e-02

-1.38e-01

2.100e+00

-1.01e-01

-5.45e-02

-1.43e-01

2.300e+00

-1.03e-01

-5.54e-02

-1.47e-01

2.500e+00

-1.05e-01

-5.62e-02

-1.50e-01

2.700e+00

-1.06e-01

-5.68e-02

-1.52e-01

2.900e+00

-1.07e-01

-5.74e-02

-1.54e-01

3.100e+00

-1.08e-01

-5.79e-02

-1.56e-01

3.300e+00

-1.09e-01

-5.84e-02

-1.57e-01

3.500e+00

-1.10e-01

-5.89e-02

-1.59e-01

3.700e+00

-1.11e-01

-6.49e-02

-1.60e-01

3.900e+00

-1.11e-01

-1.23e+00

-1.61e-01

4.100e+00

-1.14e-01

-2.16e+01

-1.62e-01

4.300e+00

-4.76e-01

-4.52e+01

-1.64e-01

4.500e+00

-2.73e+01

-6.89e+01

-1.73e-01

4.700e+00

-6.14e+01

-9.25e+01

-7.82e+00

4.900e+00

-9.54e+01

-1.17e+02

-4.19e+01

5.100e+00

-1.38e+02

-1.52e+02

-7.59e+01

5.300e+00

-1.89e+02

-1.88e+02

-1.11e+02

5.500e+00

-2.40e+02

-2.23e+02

-1.61e+02

5.700e+00

-2.91e+02

-2.59e+02

-2.12e+02

5.900e+00

-3.42e+02

-2.94e+02

-2.63e+02

6.100e+00

-3.93e+02

-3.30e+02

-3.14e+02

6.300e+00

-4.44e+02

-3.65e+02

6.500e+00

-4.95e+02

-4.01e+02

-4.16e+02

6.600e+00

-5.20e+02

-4.18e+02

-4.41e+02

[GND_clamp]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

-5.20e+02

-3.65e+02

-5.18e+02

-3.10e+00

-4.69e+02

-3.30e+02

-4.67e+02

-2.90e+00

-4.18e+02

-2.94e+02

-4.16e+02

-2.70e+00

-3.67e+02

-2.59e+02

-3.65e+02

-2.50e+00

-3.16e+02

-2.23e+02

-3.14e+02

-2.30e+00

-2.65e+02

-1.88e+02

-2.63e+02

-2.10e+00

-2.14e+02

-1.52e+02

-2.11e+02

r
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Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

IBIS Model

MOTOROLA

DSP56362 Advance Information

Appendix B-19

-1.90e+00

-1.63e+02

-1.17e+02

-1.60e+02

-1.70e+00

-1.13e+02

-9.25e+01

-1.10e+02

-1.50e+00

-7.83e+01

-6.88e+01

-7.58e+01

-1.30e+00

-4.42e+01

-4.51e+01

-4.17e+01

-1.10e+00

-1.02e+01

-2.15e+01

-7.66e+00

-9.00e-01

-1.03e-02

-1.17e+00

-9.27e-03

-7.00e-01

-3.74e-04

-5.73e-03

-1.14e-03

-5.00e-01

-1.72e-06

-5.06e-05

-1.28e-05

-3.00e-01

-1.67e-09

-4.65e-07

-1.10e-08

-1.00e-01

-2.03e-11

-4.80e-09

-2.71e-11

0.000e+00

-1.69e-11

-1.61e-09

-1.89e-11

[POWER_clamp]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

2.677e+02

1.896e+02

2.677e+02

-3.10e+00

2.420e+02

1.716e+02

2.420e+02

-2.90e+00

2.163e+02

1.537e+02

2.163e+02

-2.70e+00

1.906e+02

1.358e+02

1.906e+02

-2.50e+00

1.649e+02

1.179e+02

1.649e+02

-2.30e+00

1.392e+02

9.996e+01

1.392e+02

-2.10e+00

1.135e+02

8.205e+01

1.135e+02

-1.90e+00

8.778e+01

6.413e+01

8.778e+01

-1.70e+00

6.208e+01

5.035e+01

6.208e+01

-1.50e+00

4.368e+01

3.834e+01

4.368e+01

-1.30e+00

2.649e+01

2.633e+01

2.649e+01

-1.10e+00

9.300e+00

1.433e+01

9.301e+00

-9.00e-01

2.962e-02

2.475e+00

3.075e-02

-7.00e-01

2.501e-04

1.354e-02

6.708e-04

-5.00e-01

2.066e-06

6.280e-05

1.204e-05

-3.00e-01

2.487e-09

5.128e-07

1.417e-08

-1.00e-01

5.672e-11

5.639e-09

6.832e-11

0.000e+00

5.334e-11

1.992e-09

5.783e-11

[Ramp]

R_load = 50.00

|voltage

I(typ)

I(min)

I(max)

dV/dt_r

1.570/0.200

1.210/0.411

1.810/0.149

dV/dt_f

1.590/0.304

1.170/0.673

1.800/0.205

[Model]

ipbw_i

Model_type

Input

Polarity

Non-Inverting

Vinl= 0.8000v

Vinh= 2.000v

C_comp

5.00pF

[Voltage Range]

3.3v

3.6v

r
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I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

IBIS Model

Appendix B-20

DSP56362 Advance Information

MOTOROLA

[GND_clamp]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

-5.20e+02

-3.65e+02

-5.17e+02

-3.10e+00

-4.69e+02

-3.29e+02

-4.66e+02

-2.90e+00

-4.18e+02

-2.94e+02

-4.15e+02

-2.70e+00

-3.67e+02

-2.58e+02

-3.64e+02

-2.50e+00

-3.16e+02

-2.23e+02

-3.13e+02

-2.30e+00

-2.65e+02

-1.88e+02

-2.62e+02

-2.10e+00

-2.14e+02

-1.52e+02

-2.11e+02

-1.90e+00

-1.63e+02

-1.17e+02

-1.60e+02

-1.70e+00

-1.13e+02

-9.24e+01

-1.10e+02

-1.50e+00

-7.82e+01

-6.87e+01

-7.57e+01

-1.30e+00

-4.42e+01

-4.51e+01

-4.16e+01

-1.10e+00

-1.02e+01

-2.15e+01

-7.64e+00

-9.00e-01

-7.17e-03

-1.16e+00

-4.87e-03

-7.00e-01

-1.14e-04

-4.39e-03

-3.03e-04

-5.00e-01

-4.86e-07

-2.55e-05

-2.73e-06

-3.00e-01

-5.19e-10

-1.91e-07

-2.57e-09

-1.00e-01

-1.91e-11

-2.47e-09

-2.19e-11

0.000e+00

-1.68e-11

-1.17e-09

-1.84e-11

[POWER_clamp]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

2.667e+02

1.885e+02

2.667e+02

-3.10e+00

2.411e+02

1.707e+02

2.411e+02

-2.90e+00

2.155e+02

1.528e+02

2.155e+02

-2.70e+00

1.898e+02

1.350e+02

1.898e+02

-2.50e+00

1.642e+02

1.172e+02

1.642e+02

-2.30e+00

1.386e+02

9.935e+01

1.386e+02

-2.10e+00

1.130e+02

8.152e+01

1.130e+02

-1.90e+00

8.739e+01

6.369e+01

8.739e+01

-1.70e+00

6.178e+01

4.999e+01

6.178e+01

-1.50e+00

4.346e+01

3.806e+01

4.346e+01

-1.30e+00

2.634e+01

2.613e+01

2.634e+01

-1.10e+00

9.237e+00

1.421e+01

9.237e+00

-9.00e-01

2.454e-02

2.430e+00

2.488e-02

-7.00e-01

8.741e-05

1.104e-02

2.050e-04

-5.00e-01

6.316e-07

4.079e-05

2.961e-06

-3.00e-01

8.479e-10

2.484e-07

3.721e-09

-1.00e-01

4.420e-11

3.001e-09

4.943e-11

0.000e+00

4.215e-11

1.346e-09

4.543e-11

[Model]

ipbw_io

Model_type

I/O

Polarity

Non-Inverting

Vinl= 0.8000v

Vinh= 2.000v

C_comp

5.00pF

[Voltage Range]

3.3v

3.6v

r
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Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

IBIS Model

MOTOROLA

DSP56362 Advance Information

Appendix B-21

[Pulldown]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

-5.20e+02

-3.65e+02

-5.17e+02

-3.10e+00

-4.69e+02

-3.29e+02

-4.66e+02

-2.90e+00

-4.18e+02

-2.94e+02

-4.15e+02

-2.70e+00

-3.67e+02

-2.58e+02

-3.64e+02

-2.50e+00

-3.16e+02

-2.23e+02

-3.13e+02

-2.30e+00

-2.65e+02

-1.88e+02

-2.62e+02

-2.10e+00

-2.14e+02

-1.52e+02

-2.11e+02

-1.90e+00

-1.63e+02

-1.17e+02

-1.60e+02

-1.70e+00

-1.13e+02

-9.24e+01

-1.10e+02

-1.50e+00

-7.82e+01

-6.87e+01

-7.57e+01

-1.30e+00

-4.42e+01

-4.51e+01

-4.17e+01

-1.10e+00

-1.02e+01

-2.15e+01

-7.66e+00

-9.00e-01

-3.69e-02

-1.17e+00

-3.79e-02

-7.00e-01

-2.52e-02

-1.67e-02

-2.81e-02

-5.00e-01

-1.83e-02

-9.77e-03

-2.04e-02

-3.00e-01

-1.11e-02

-5.89e-03

-1.24e-02

-1.00e-01

-3.77e-03

-1.98e-03

-4.20e-03

1.000e-01

3.729e-03

1.940e-03

4.177e-03

3.000e-01

1.076e-02

5.578e-03

1.216e-02

5.000e-01

1.723e-02

8.907e-03

1.965e-02

7.000e-01

2.311e-02

1.191e-02

2.663e-02

9.000e-01

2.836e-02

1.455e-02

3.305e-02

1.100e+00

3.292e-02

1.680e-02

3.887e-02

1.300e+00

3.675e-02

1.862e-02

4.404e-02

1.500e+00

3.979e-02

1.997e-02

4.850e-02

1.700e+00

4.205e-02

2.085e-02

5.223e-02

1.900e+00

4.347e-02

2.136e-02

5.518e-02

2.100e+00

4.413e-02

2.162e-02

5.728e-02

2.300e+00

4.445e-02

2.176e-02

5.843e-02

2.500e+00

4.465e-02

2.186e-02

5.899e-02

2.700e+00

4.479e-02

2.194e-02

5.931e-02

2.900e+00

4.492e-02

2.200e-02

5.953e-02

3.100e+00

4.502e-02

2.206e-02

5.971e-02

3.300e+00

4.511e-02

2.211e-02

5.986e-02

3.500e+00

4.519e-02

2.219e-02

5.999e-02

3.700e+00

4.526e-02

3.324e-02

6.010e-02

3.900e+00

4.536e-02

2.452e+00

6.021e-02

4.100e+00

4.614e-02

1.423e+01

6.032e-02

4.300e+00

1.344e+00

2.615e+01

6.065e-02

4.500e+00

1.783e+01

3.808e+01

8.548e-02

4.700e+00

3.495e+01

5.001e+01

9.298e+00

4.900e+00

5.208e+01

6.371e+01

2.640e+01

5.100e+00

7.463e+01

8.154e+01

4.352e+01

5.300e+00

1.002e+02

9.937e+01

6.184e+01

5.500e+00

1.259e+02

1.172e+02

8.745e+01

5.700e+00

1.515e+02

1.350e+02

1.131e+02

5.900e+00

1.771e+02

1.529e+02

1.387e+02

6.100e+00

2.027e+02

1.707e+02

1.643e+02

6.300e+00

2.283e+02

1.885e+02

1.899e+02

6.500e+00

2.539e+02

2.064e+02

2.155e+02

6.600e+00

2.667e+02

2.153e+02

2.283e+02

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For More Information On This Product,

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IBIS Model

Appendix B-22

DSP56362 Advance Information

MOTOROLA

[Pullup]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

2.667e+02

1.885e+02

2.667e+02

-3.10e+00

2.411e+02

1.707e+02

2.411e+02

-2.90e+00

2.155e+02

1.528e+02

2.155e+02

-2.70e+00

1.898e+02

1.350e+02

1.898e+02

-2.50e+00

1.642e+02

1.172e+02

1.642e+02

-2.30e+00

1.386e+02

9.935e+01

1.386e+02

-2.10e+00

1.130e+02

8.152e+01

1.130e+02

-1.90e+00

8.739e+01

6.369e+01

8.739e+01

-1.70e+00

6.178e+01

4.999e+01

6.178e+01

-1.50e+00

4.346e+01

3.806e+01

4.346e+01

-1.30e+00

2.635e+01

2.613e+01

2.635e+01

-1.10e+00

9.243e+00

1.421e+01

9.245e+00

-9.00e-01

5.536e-02

2.435e+00

6.260e-02

-7.00e-01

2.847e-02

2.689e-02

3.437e-02

-5.00e-01

2.025e-02

1.265e-02

2.451e-02

-3.00e-01

1.208e-02

7.503e-03

1.467e-02

-1.00e-01

3.994e-03

2.474e-03

4.868e-03

1.000e-01

-3.88e-03

-2.38e-03

-4.76e-03

3.000e-01

-1.11e-02

-6.76e-03

-1.37e-02

5.000e-01

-1.76e-02

-1.06e-02

-2.20e-02

7.000e-01

-2.35e-02

-1.40e-02

-2.95e-02

9.000e-01

-2.86e-02

-1.69e-02

-3.63e-02

1.100e+00

-3.30e-02

-1.93e-02

-4.23e-02

1.300e+00

-3.65e-02

-2.10e-02

-4.75e-02

1.500e+00

-3.92e-02

-2.22e-02

-5.17e-02

1.700e+00

-4.12e-02

-2.29e-02

-5.51e-02

1.900e+00

-4.26e-02

-2.35e-02

-5.77e-02

2.100e+00

-4.36e-02

-2.38e-02

-5.97e-02

2.300e+00

-4.43e-02

-2.42e-02

-6.11e-02

2.500e+00

-4.49e-02

-2.44e-02

-6.22e-02

2.700e+00

-4.54e-02

-2.47e-02

-6.31e-02

2.900e+00

-4.58e-02

-2.49e-02

-6.38e-02

3.100e+00

-4.61e-02

-2.50e-02

-6.44e-02

3.300e+00

-4.65e-02

-2.52e-02

-6.49e-02

3.500e+00

-4.68e-02

-2.54e-02

-6.54e-02

3.700e+00

-4.70e-02

-2.99e-02

-6.58e-02

3.900e+00

-4.73e-02

-1.19e+00

-6.62e-02

4.100e+00

-4.81e-02

-2.15e+01

-6.66e-02

4.300e+00

-4.00e-01

-4.51e+01

-6.72e-02

4.500e+00

-2.72e+01

-6.87e+01

-7.21e-02

4.700e+00

-6.12e+01

-9.24e+01

-7.70e+00

4.900e+00

-9.52e+01

-1.17e+02

-4.17e+01

5.100e+00

-1.37e+02

-1.52e+02

-7.57e+01

5.300e+00

-1.88e+02

-1.10e+02

5.500e+00

-2.39e+02

-2.23e+02

-1.60e+02

5.700e+00

-2.90e+02

-2.58e+02

-2.11e+02

5.900e+00

-3.41e+02

-2.94e+02

-2.62e+02

6.100e+00

-3.92e+02

-3.29e+02

-3.13e+02

6.300e+00

-4.43e+02

-3.65e+02

-3.64e+02

6.500e+00

-4.94e+02

-4.00e+02

-4.15e+02

6.600e+00

-5.20e+02

-4.18e+02

-4.41e+02

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Freescale Semiconductor, Inc.

For More Information On This Product,

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IBIS Model

MOTOROLA

DSP56362 Advance Information

Appendix B-23

[GND_clamp]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

-5.20e+02

-3.65e+02

-5.17e+02

-3.10e+00

-4.69e+02

-3.29e+02

-4.66e+02

-2.90e+00

-4.18e+02

-2.94e+02

-4.15e+02

-2.70e+00

-3.67e+02

-2.58e+02

-3.64e+02

-2.50e+00

-3.16e+02

-2.23e+02

-3.13e+02

-2.30e+00

-2.65e+02

-1.88e+02

-2.62e+02

-2.10e+00

-2.14e+02

-1.52e+02

-2.11e+02

-1.90e+00

-1.63e+02

-1.17e+02

-1.60e+02

-1.70e+00

-1.13e+02

-9.24e+01

-1.10e+02

-1.50e+00

-7.82e+01

-6.87e+01

-7.57e+01

-1.30e+00

-4.42e+01

-4.51e+01

-4.16e+01

-1.10e+00

-1.02e+01

-2.15e+01

-7.64e+00

-9.00e-01

-7.17e-03

-1.16e+00

-4.87e-03

-7.00e-01

-1.14e-04

-4.39e-03

-3.03e-04

-5.00e-01

-4.86e-07

-2.55e-05

-2.73e-06

-3.00e-01

-5.19e-10

-1.91e-07

-2.57e-09

-1.00e-01

-1.91e-11

-2.47e-09

-2.19e-11

0.000e+00

-1.68e-11

-1.17e-09

-1.84e-11

[POWER_clamp]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

2.667e+02

1.885e+02

2.667e+02

-3.10e+00

2.411e+02

1.707e+02

2.411e+02

-2.90e+00

2.155e+02

1.528e+02

2.155e+02

-2.70e+00

1.898e+02

1.350e+02

1.898e+02

-2.50e+00

1.642e+02

1.172e+02

1.642e+02

-2.30e+00

1.386e+02

9.935e+01

1.386e+02

-2.10e+00

1.130e+02

8.152e+01

1.130e+02

-1.90e+00

8.739e+01

6.369e+01

8.739e+01

-1.70e+00

6.178e+01

4.999e+01

6.178e+01

-1.50e+00

4.346e+01

3.806e+01

4.346e+01

-1.30e+00

2.634e+01

2.613e+01

2.634e+01

-1.10e+00

9.237e+00

1.421e+01

9.237e+00

-9.00e-01

2.454e-02

2.430e+00

2.488e-02

-7.00e-01

8.741e-05

1.104e-02

2.050e-04

-5.00e-01

6.316e-07

4.079e-05

2.961e-06

-3.00e-01

8.479e-10

2.484e-07

3.721e-09

-1.00e-01

4.420e-11

3.001e-09

4.943e-11

0.000e+00

4.215e-11

1.346e-09

4.543e-11

[Ramp]

R_load = 50.00

|voltage

I(typ)

I(min)

I(max)

dV/dt_r

1.140/0.494

0.699/0.978

1.400/0.354

dV/dt_f

1.150/0.505

0.642/0.956

1.350/0.350

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For More Information On This Product,

Go to: www.freescale.com

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IBIS Model

Appendix B-24

DSP56362 Advance Information

MOTOROLA

[Model]

iexlh_i

Model_type

Input

Polarity

Non-Inverting

Vinl= 0.8000v

Vinh= 2.000v

C_comp

5.00pF

[Voltage Range]

3.3v

3.6v

[GND_clamp]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

-5.21e+02

-3.66e+02

-5.18e+02

-3.10e+00

-4.70e+02

-3.30e+02

-4.67e+02

-2.90e+00

-4.19e+02

-2.95e+02

-4.16e+02

-2.70e+00

-3.68e+02

-2.59e+02

-3.65e+02

-2.50e+00

-3.17e+02

-2.24e+02

-3.14e+02

-2.30e+00

-2.66e+02

-1.89e+02

-2.63e+02

-2.10e+00

-2.15e+02

-1.53e+02

-2.12e+02

-1.90e+00

-1.64e+02

-1.18e+02

-1.61e+02

-1.70e+00

-1.14e+02

-9.34e+01

-1.11e+02

-1.50e+00

-7.93e+01

-6.98e+01

-7.68e+01

-1.30e+00

-4.53e+01

-4.62e+01

-4.28e+01

-1.10e+00

-1.13e+01

-2.26e+01

-8.78e+00

-9.00e-01

-7.94e-03

-1.87e+00

-3.77e-03

-7.00e-01

-1.62e-06

-5.11e-03

-7.69e-07

-5.00e-01

-3.45e-10

-1.40e-05

-1.72e-10

-3.00e-01

-1.29e-11

-3.90e-08

-1.38e-11

-1.00e-01

-1.10e-11

-8.67e-10

-1.19e-11

0.000e+00

-1.01e-11

-7.13e-10

-1.10e-11

[POWER_clamp]

|voltage

I(typ)

I(min)

I(max)

-3.30e+00

2.653e+02

1.870e+02

2.653e+02

-3.10e+00

2.398e+02

1.693e+02

2.398e+02

-2.90e+00

2.143e+02

1.516e+02

2.143e+02

-2.70e+00

1.888e+02

1.339e+02

1.888e+02

-2.50e+00

1.633e+02

1.162e+02

1.633e+02

-2.30e+00

1.378e+02

9.847e+01

1.378e+02

-2.10e+00

1.123e+02

8.076e+01

1.123e+02

-1.90e+00

8.682e+01

6.305e+01

8.682e+01

-1.70e+00

6.133e+01

4.947e+01

6.133e+01

-1.50e+00

4.313e+01

3.766e+01

4.313e+01

-1.30e+00

2.614e+01

2.585e+01

2.614e+01

-1.10e+00

9.145e+00

1.404e+01

9.145e+00

-9.00e-01

1.797e-02

2.364e+00

1.797e-02

-7.00e-01

3.667e-06

7.589e-03

3.667e-06

-5.00e-01

7.730e-10

2.072e-05

7.748e-10

-3.00e-01

2.293e-11

5.767e-08

2.476e-11

-1.00e-01

2.096e-11

1.163e-09

2.278e-11

0.000e+00

2.004e-11

9.618e-10

2.186e-11

[End]

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Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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MOTOROLA

DSP56362 Advance Information

INDEX

ac electrical characteristics

2-4

Address Trace mode

iv, 2-44, 2-47

ALU

iii

applications

arbitration bus timings

2-47

Arithmetic Logic Unit

iii

benchmark test algorithm

A-1, B-1

bootstrap ROM

Boundary Scan (JTAG Port) timing diagram

bus

address

1-2

data

1-2

multiplexed

1-2

non-multiplexed

1-2

bus acquisition timings

2-48

bus release timings

2-49, 2-50

case outline drawing

3-8

clock

external

2-5

operation

2-6

clocks

internal

2-5

Data Arithmetic Logic Unit

iii

data memory expansion

DAX

iv, 1-2, 1-19

dc electrical characteristics

2-3

Debug support

description, general

design considerations

electrical

4-3

PLL

4-5, 4-6

power consumption

4-4

thermal

4-1

Digital Audio Transmitter

iv, 1-19

Direct Memory Access

iii

DMA

iii

DRAM

out of page

read access

2-41

wait states selection guide

2-33

write access

2-42

out of page and refresh timings

11 wait states

2-37

15 wait states

2-39

4 wait states

2-33

8 wait states

2-36

Page mode

read accesses

2-32

wait states selection guide

2-22

write accesses

2-31

Page mode timings

1 wait state

2-23

2 wait states

2-24

3 wait states

2-27

4 wait states

2-29

refresh access

2-43

DRAM controller

DSP programming

4-8

DSP56300

core features

iii

DSP56362

features

iii

specifications

2-1

electrical design considerations

4-3

Enhanced Serial Audio Interface

ESAI

iv, 1-2

ESSI

receiver timing

2-75, 2-76

timings

2-71

transmitter timing

2-74

EXTAL jitter

4-6

external bus control

1-7, 1-8

external bus synchronous timings (SRAM

access)

2-44

external clock operation

2-5

external interrupt timing (negative edge-

triggered)

2-15

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Freescale Semiconductor, Inc.

For More Information On This Product,

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Index

DSP56362 Advance Information

MOTOROLA

external level-sensitive fast interrupt timing

2-15

external memory access (DMA Source) timing

External Memory Expansion Port

2-18

functional groups

1-2

functional signal groups

1-1

general description

General Purpose Input/Output

GPIO

iv, 1-2, 1-25

GPIO timing

2-80

Ground

1-4

PLL

1-4

HDI08

iv, 1-2, 1-11, 1-12, 1-14, 1-15

DSP programming

4-8

DSP synchronization

4-8

Host synchronization

4-6

HDI08 timing

2-52

Host Interface

iv, 1-2, 1-11, 1-12, 1-14, 1-15

Host Interface timing

2-52

host port

configuration

1-11

Host Port considerations

4-6

Host programming

4-6

Host Request

Double

1-2

Single

1-2

instruction cache

internal clocks

2-5

interrupt and mode control

1-9

interrupt control

1-9

interrupt timing

2-9

external level-sensitive fast

2-15

external negative edge-triggered

2-15

synchronous from Wait state

2-16

Jitter

4-6

JTAG

1-25

JTAG Port

reset timing diagram

2-84

timing

2-82, 2-83

maximum ratings

2-1, 2-2

mechanical drawings

3-8

Memory Expansion Port

Mfax system

3-8

mode control

1-9

Mode select timing

2-9

multiplexed bus

1-2

multiplexed bus timings

read

2-57

write

2-58

non-multiplexed bus

1-2

non-multiplexed bus timings

read

2-55

write

2-56

off-chip memory

OnCE

module timing

2-85

OnCE module

iv, 1-25

Debug request

2-85

on-chip DRAM controller

On-Chip Emulation module

on-chip memory

operating mode select timing

2-16

ordering drawings

3-8

ordering information

5-1

package

144-pin TQFP

3-1

TQFP description

3-2, 3-3

PCU

iii

Phase Lock Loop

iii, 2-8

PLL

iii, 2-8

Characteristics

2-8

performance issues

4-5

PLL design considerations

4-5, 4-6

PLL performance issues

4-6

Port A

1-2

Port B

1-2, 1-12, 1-13, 1-14, 1-15

Port C

1-2, 1-19

Port D

1-2, 1-19

power consumption benchmark test

A-1, B-1

power consumption design considerations

4-4

power management

Program Control Unit

iii

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Freescale Semiconductor, Inc.

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Index

MOTOROLA

DSP56362 Advance Information

program memory expansion

program RAM

recovery from Stop state using IRQA

2-16

2-17

RESET

1-10

Reset timing

2-9, 2-14

synchronous

2-14

ROM, bootstrap

Serial Host Interface

iv, 1-16

SHI

iv, 1-2, 1-16

signal groupings

1-1

signals

1-1

functional grouping

1-2

SRAM

2-45

Access

2-44

read access

2-21

read and write accesses

2-18

support

write access

2-21

Stop mode

Stop state

recovery from

2-16, 2-17

Stop timing

2-9

supply voltage

2-2

Switch mode

Synchronization

4-6

synchronous bus timings

SRAM

2 wait states

2-46

SRAM 1 wait state (BCR controlled)

2-45

synchronous interrupt from Wait state timing

synchronous Reset timing

2-14

TAP

target applications

Test Access Port

Test Access Port timing diagram

2-84

Test Clock (TCLK) input timing diagram

2-83

thermal characteristics

2-2

thermal design considerations

4-1

Timer

iv, 1-2, 1-25

event input restrictions

2-78

interrupt generation

2-79

timing

2-78

Timing

Digital Audio Transmitter (DAX)

2-77

Enhanced Serial Audio Interface (ESAI)

General Purpose I/O (GPIO) Timing

2-71

OnCETM (On Chip Emulator) Timing

2-71

Serial Host Interface (SHI) SPI Protocol

Timing

2-60

Serial Host Interface (SHI) Timing

2-60

timing

interrupt

2-9

mode select

2-9

Reset

2-9

Stop

2-9

TQFP

3-1

pin list by number

3-3

pin-out drawing (top)

3-2

TQFP package drawing

3-8

Wait mode

X data RAM

Y data RAM

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HOW TO REACH US:

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P.O. Box 5405
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HOME PAGE:
http://motorola.com/semiconductors

DSP56362/D
Rev. 3
02/2004

Information in this document is provided solely to enable system and software implementers to use Motorola products.
There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or
integrated circuits based on the information in this document.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume
any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including "Typicals", must be validated for each customer application by customer's technical
experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could
create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising
out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even
if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.

MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service
names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

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Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DSP56362P

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DSP56362P