DSP56855 Data Sheet

DSP56855/D

Rev. 2.0, 3/2003

DSP56855

Preliminary Technical Data

DSP56855 16-bit Digital Signal Processor

· 120 MIPS at 120MHz

· 24K x 16-bit Program SRAM

· 24K x 16-bit Data SRAM

· 1K x 16-bit Boot ROM

· Access up to 2M words of program memory or 8M

words of data memory

· Chip Select Logic for glue-less interface to ROM

and SRAM

· Six (6) independent channels of DMA

· Enhanced Synchronous Serial Interface (ESSI)

· Two (2) Serial Communication Interfaces (SCI)

· General Purpose 16-bit Quad Timer with 1 external

· JTAG/Enhanced On-Chip Emulation (OnCETM) for

unobtrusive, real-time debugging

· Computer Operating Properly (COP)/Watchdog

Timer

· Time-of-Day (TOD)

· 100 LQFP package

· Up to 18 GPIO

Figure 1. DSP56855 Block Diagram

JTAG/

Enhanced

OnCE

Program Controller

and

Hardware Looping Unit

Data ALU

16 x 16 + 36

36-Bit MAC

Three 16-bit Input Registers

Four 36-bit Accumulators

Address

Generation Unit

Bit

Manipulation

Unit

16-Bit

DSP56800E Core

XTAL

EXTAL

Interrupt

Controller

Quad

Timer

GPIOG

CLKO

External Address

Bus Switch

External Bus

Interface Unit

RESET

IRQA

IRQB

SSIO

DDA

SSA

External Data

Bus Switch

Bus Control

WR Enable

RD Enable

CS0-CS3[3:0] or

A0-20 [20:0]

MODEA-C or

D0-D15 [15:0]

Program Memory

24,576 x 16 SRAM

Boot ROM

1024 x 16 ROM

Data Memory

24,576 x 16 SRAM

PDB

XAB1

XAB2

XDB2

CDBR

2 SCI

GPIOE

IPBus Bridge (IPBB)

(GPIOH0-H2)

DDIO

Decoding
Peripherals

System

Bus

Control

Memory

PAB

CDBW

CDBR

CDBW

GPIOA0-GPIOA3[3:0]

ESSI0

GPIOC

RSTO

DMA

6 channel

POR

Integration

Module

System

COP/

Watch-

dog

Time

Day

Clock

Generator

OSC PLL

IPBus CLK

COP/TOD CLK

Core CLK

I
P

RDB

Reques

t
s

DSP56855 Preliminary Technical Data

MOTOROLA

Part 1 Overview

1.1 DSP56855 Features

1.1.1

Digital Signal Processing Core

Efficient 16-bit DSP engine with dual Harvard architecture

120 Million Instructions Per Second (MIPS) at 120MHz core frequency

Single-cycle 16

× 16-bit parallel Multiplier-Accumulator (MAC)

Four (4) 36-bit accumulators including extension bits

16-bit bidirectional shifter

Parallel instruction set with unique DSP addressing modes

Hardware DO and REP loops

Three (3) internal address buses and one (1) external address bus

Four (4) internal data buses and one (1) external data bus

Instruction set supports both DSP and controller functions

Four (4) hardware interrupt levels

Five (5) software interrupt levels

Controller-style addressing modes and instructions for compact code

Efficient C Compiler and local variable support

Software subroutine and interrupt stack with depth limited only by memory

JTAG/Enhanced OnCE debug programming interface

1.1.2

Memory

Harvard architecture permits up to three (3) simultaneous accesses to program and data memory

On-Chip Memory

-- 24K

× 16-bit Program SRAM

-- 24K

× 16-bit Data SRAM

-- 1K

× 16-bit Boot ROM

Off-Chip Memory Expansion (EMI)

-- Access up to 2M words of program memory or 8M words of data memory

-- Chip Select Logic for glue-less interface to ROM and SRAM

1.1.3

Peripheral Circuits for DSP56855

General Purpose 16-bit Quad Timer with 1 external pin*

Two (2) Serial Communication Interfaces (SCI)*

Enhanced Synchronous Serial Interface (ESSI) module*

Computer Operating Properly (COP)/Watchdog Timer

JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging

DSP56855 Description

MOTOROLA

DSP56855 Preliminary Technical Data

Six (6) independent channels of DMA

Time-of-Day (TOD)

Up to 18 GPIO

* Each peripheral I/O can be used alternately as a General Purpose I/O if not needed

1.1.4

Energy Information

Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs

Wait and Stop modes available

1.2 DSP56855 Description

The DSP56855 is a member of the DSP56800E core-based family of Digital Signal Processors (DSPs). It
combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with
a flexible set of peripherals, creating an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the DSP56855 is well-suited for many applications.
The DSP56855 includes many peripherals that are especially useful for low-end Internet appliance
applications and low-end client applications such as telephony; portable devices; Internet audio; and point-
of-sale systems, such as noise suppression; ID tag readers; sonic/subsonic detectors; security access
devices; remote metering; sonic alarms.

The DSP56800E core is based on a Harvard-style architecture consisting of three execution units operating
in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C Compilers, enabling rapid
development of optimized control applications.

The DSP56855 supports program execution from either internal or external memories. Two data operands
can be accessed from the on-chip Data RAM per instruction cycle. The DSP56855 also provides two
external dedicated interrupt lines, and up to 18 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.

The DSP56855 DSP controller includes 24K words of Program RAM, 24K words of Data RAM and 1K of
Boot ROM. It also supports program execution from external memory.

This DSP controller also provides a full set of standard programmable peripherals that include one
Enhanced Synchronous Serial Interface (ESSI), two Serial Communications Interfaces (SCI), and one Quad
Timer. The ESSI, SCIs, four chip selects and and Quad Timer external output can be used as General
Purpose Input/Outputs when its primary function is not required.

1.3 "Best in Class" Development Environment

The SDK (Software Development Kit) provides fully debugged peripheral drivers, libraries and interfaces
that allow a programmer to create his own unique C application code independent of component
architecture. The CodeWarrior Integrated Development Environment is a sophisticated tool for code
navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development
system cards will support concurrent engineering. Together, the SDK, CodeWarrior, and EVMs create a
complete, scalable tools solution for easy, fast and efficient development.

DSP56855 Preliminary Technical Data

MOTOROLA

1.4 Product Documentation

The four documents listed in

Table 1

are required for a complete description of and proper design with the

DSP56855. Documentation is available from local Motorola distributors, Motorola semiconductor sales
offices, Motorola Literature Distribution Centers, or online at www.motorola.com/semiconductors/.

Table 1. DSP56855 Chip Documentation

1.5 Data Sheet Conventions

This data sheet uses the following conventions:

Topic

Description

Order Number

DSP56800E
Reference Manual

Detailed description of the DSP56800E architecture,
and 16-bit DSP core processor and the instruction set

DSP56800ERM/D

DSP56855
User's Manual

Detailed description of memory, peripherals, and
interfaces of the DSP56855

DSP5685xUM/D

DSP56855
Technical Data Sheet

Electrical and timing specifications, pin descriptions,
and package descriptions (this document)

DSP56855/D

DSP56855
Product Brief

Summary description and block diagram of the
DSP56855 core, memory, peripherals and interfaces

DSP56855PB/D

OVERBAR

This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.

"asserted"

A high true (active high) signal is high or a low true (active low) signal is low.

"deasserted"

A high true (active high) signal is low or a low true (active low) signal is high.

Examples:

Signal/Symbol

Logic State

Signal State

Voltage

Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

True

Asserted

False

Deasserted

True

Asserted

False

Deasserted

Introduction

MOTOROLA

DSP56855 Preliminary Technical Data

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the DSP56855 are organized into functional groups, as shown in

Table 2

and as illustrated in

Figure 2

. In

Table 3

each table row describes the package pin and the signal or signals

present.

DD CORE,

SS CORE,

DDIO

DD IO,

SSIO

SS IO,

DDA

DD ANA,

SSA

SS ANA

2. MODA, MODB and MODC can be used as GPIO after the bootstrap process has completed.

Table 2. DSP56855 Functional Group Pin Allocations

Functional Group

Number of Pins

Power (V

DD,

DDIO, or

DDA

)

(4, 10, 1)

Ground (V

SS,

SSIO,

or V

SSA

)

(4, 10, 1)

PLL and Clock

External Bus Signals

External Chip Select*

Interrupt and Program Control

Enhanced Synchronous Serial Interface (ESSI0) Port*

Serial Communications Interface (SCI0) Ports*

Serial Communications Interface (SCI1) Ports*

Quad Timer Module Port*

JTAG/Enhanced On-Chip Emulation (EOnCE)

*Alternately, GPIO pins

DSP56855 Preliminary Technical Data

MOTOROLA

Figure 2. DSP56855 Signals Identified by Functional Group

1. Specifically for PLL, OSC, and POR.
2. Alternate pin functions are shown in parentheses.

DSP56855

Logic

Power

I/O

Power

SCI 0

JTAG /
Enhanced
OnCE

Timer

Module

ESSI 0

Chip

Select

External

Bus

Analog

Power

PLL/Clock

SCI 2

Interrupt/

Program

Control

DDIO

SSIO

DDA

SSA

A0 - A20

D0 - D15

CS0 - CS3 (GPIOA0 - A3)

TIO0 (GPIOG0)

IRQA

IRQB

MODA, MODB, MODC

(GPIOH0 - H2)

RESET

RSTO

XTAL

RXDO (GPIOE0)

TXDO (GPIOE1)

RXD1 (GPIOE2)

TXD1 (GPIOE3)

STD0 (GPIOC0)

SRD0 (GPIOC1)

SCK0 (GPIOC2)

SC00 (GPIOC3)

SC01 (GPIOC4)

SC02 (GPIOC5)

EXTAL

CLKO

TCK

TDI

TDO

TMS

TRST

Introduction

MOTOROLA

DSP56855 Preliminary Technical Data

Part 3 Signals and Package Information

All digital inputs have a weak internal pull-up circuit associated with them. These pull-up circuits
are enabled by default. Exceptions:

1. When a pin has GPIO functionality, the pull-up may be disabled under software control.

2. MODE A, MODE B and MODE C pins have no pull-up.

3. TCK has a weak pull-down circuit always active.

4. Bidirectional I/O pullups automatically disable when the output is enabled.

This table is presented consistently with the Signals Identified by Functional Group figure.

1. BOLD entries in the Type column represents the state of the pin just out of reset.

2. Ouput(Z) means an output in a High-Z condition.

Table 3. DSP56855 Signal and Package Information for the 100-pin LQFP

Pin
No.

Signal Name

Type

Description

Power (V

)--These pins provide power to the internal structures of

the chip, and should all be attached to V

DD.

Ground (V

)--These pins provide grounding for the internal

structures of the chip and should all be attached to V

SS.

DDIO

Power (V

DDIO

)--These pins provide power for all I/O and ESD

structures of the chip, and should all be attached to V

DDIO

(3.3V).

DDIO

DSP56855 Preliminary Technical Data

MOTOROLA

SSIO

Ground (V

SSIO

)--These pins provide grounding for all I/O and ESD

structures of the chip and should all be attached to V

SS.

SSIO

DDA

Analog Power (V

DDA

)--These pins supply an analog power source.

SSA

Analog Ground (V

SSA

)--This pin supplies an analog ground.

Table 3. DSP56855 Signal and Package Information for the 100-pin LQFP

Pin
No.

Signal Name

Type

Description

DSP56855 Preliminary Technical Data

MOTOROLA

Input/Output(Z)

Data Bus (D0-D15)--These pins provide the bidirectional data for
external program or data memory accesses.

D10

D11

D12

D13

D14

Output

Read Enable (RD)-- is asserted during external memory read cycles.

This signal is pulled high during reset.

Output

Write Enable (WR) -- is asserted during external memory write
cycles.

This signal is pulled high during reset.

CS0

GPIOA0

Output

Input/Output

External Chip Select (CS0)--This pin is used as a dedicated GPIO.

Port A GPIO (0) --This pin is a General Purpose I/O (GPIO) pin when
not configured for host port usage.

CS1

GPIOA1

Output

Input/Output

External Chip Select (CS1)--This pin is used as a dedicated GPIO.

Port A GPIO (1) --This pin is a General Purpose I/O (GPIO) pin when
not configured for host port usage.

CS2

GPIOA2

Output

Input/Output

External Chip Select (CS2)--This pin is used as a dedicated GPIO.

Port A GPIO (2) --This pin is a General Purpose I/O (GPIO) pin when
not configured for host port usage.

Table 3. DSP56855 Signal and Package Information for the 100-pin LQFP

Pin
No.

Signal Name

Type

Description

Introduction

MOTOROLA

DSP56855 Preliminary Technical Data

CS3

GPIOA3

Output

Input/Output

External Chip Select (CS3)--This pin is used as a dedicated GPIO.

Port A GPIO (3)--This pin is a General Purpose I/O (GPIO) pin when
not configured for host port usage.

TIO0

GPIOG0

Input/Output

Input/Output

Timer Input/Output (TIO0)--This pin can be independently
configured to be either timer input source or output flag.

Port G GPIO (0)--This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.

IRQA

Input

External Interrupt Request A and B--The IRQA and IRQB inputs
are asynchronized external interrupt requests that indicate that an
external device is requesting service. A Schmitt trigger input is used
for noise immunity. They can be programmed to be level-sensitive or
negative-edge- triggered. If level-sensitive triggering is selected, an
external pull-up resistor is required for Wired-OR operation.

IRQB

MODA

GPIOH0

Input

Input/Output

Mode Select (MODA)--During the bootstrap process MODA selects
one of the eight bootstrap modes.

Port H GPIO (0)--This pin is a General Purpose I/O (GPIO) pin after
the bootstrap process has completed.

MODB

GPIOH1

Input

Input/Output

Mode Select (MODB)--During the bootstrap process MODB selects
one of the eight bootstrap modes.

Port H GPIO (1)--This pin is a General Purpose I/O (GPIO) pin after
the bootstrap process has completed.

MODC

GPIOH2

Input

Input/Output

Mode Select (MODC)--During the bootstrap process MODC selects
one of the eight bootstrap modes.

Port H GPIO (2)--This pin is a General Purpose I/O (GPIO) pin after
the bootstrap process has completed.

RESET

Input

Reset (RESET)--This input is a direct hardware reset on the
processor. When RESET is asserted low, the DSP is initialized and
placed in the Reset state. A Schmitt trigger input is used for noise
immunity. When the RESET pin is deasserted, the initial chip
operating mode is latched from the MODA, MODB, and MODC pins.

To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware DSP reset is required and it is
necessary not to reset the JTAG/Enhanced OnCE module. In this
case, assert RESET, but do not assert TRST.

RSTO

Output

Reset Output (RSTO)--This output is asserted on any reset
condition (external reset, low voltage, software or COP).

Table 3. DSP56855 Signal and Package Information for the 100-pin LQFP

Pin
No.

Signal Name

Type

Description

DSP56855 Preliminary Technical Data

MOTOROLA

RXD0

GPIOE0

Input

Input/Output

Serial Receive Data 0 (RXD0)--This input receives byte-oriented
serial data and transfers it to the SCI 0 receive shift register.

Port E GPIO (0)--This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.

TXD0

GPIOE1

Output(Z)

Input/Output

Serial Transmit Data 0 (TXD0)--This signal transmits data from the
SCI 0 transmit data register.

Port E GPIO (1)--This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.

RXD1

GPIOE2

Input

Input/Output

Serial Receive Data 1 (RXD1)--This input receives byte-oriented
serial data and transfers it to the SCI 1 receive shift register.

Port E GPIO (2)--This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.

TXD1

GPIOE3

Output(Z)

Input/Output

Serial Transmit Data 1 (TXD1)--This signal transmits data from the
SCI 1 transmit data register.

Port E GPIO (3)--This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.

STD0

GPIOC0

Output

Input/Output

ESSI Transmit Data (STD0)--This output pin transmits serial data
from the ESSI Transmitter Shift Register.

Port C GPIO (0)--This pin is a General Purpose I/O (GPIO) pin when
the ESSI is not in use.

SRD0

GPIOC1

Input

Input/Output

ESSI Receive Data (SRD0)--This input pin receives serial data and
transfers the data to the ESSI Receive Shift Register.

Port C GPIO (1)--This pin is a General Purpose I/O (GPIO) pin when
the ESSI is not in use.

SCK0

GPIOC2

Input/Output

Input/Output

ESSI Serial Clock (SCK0)--This bidirectional pin provides the serial
bit rate clock for the transmit section of the ESSI. The clock signal can
be continuous or gated and can be used by both the transmitter and
receiver in synchronous mode.

Port C GPIO (2)--This pin is a General Purpose I/O (GPIO) pin when
the ESSI is not in use.

SC00

GPIOC3

Input/Output

Input/Output

ESSI Serial Control Pin 0 (SC00)--The function of this pin is
determined by the selection of either synchronous or asynchronous
mode. For asynchronous mode, this pin will be used for the receive
clock I/O. For synchronous mode, this pin is used either for
transmitter1 output or for serial I/O flag 0.

Port C GPIO (3)--This pin is a General Purpose I/O (GPIO) pin when
the ESSI is not in use.

Table 3. DSP56855 Signal and Package Information for the 100-pin LQFP

Pin
No.

Signal Name

Type

Description

Introduction

MOTOROLA

DSP56855 Preliminary Technical Data

SC01

GPIOC4

Input/Output

Input/Output

ESSI Serial Control Pin 1 (SC01)--The function of this pin is
determined by the selection of either synchronous or asynchronous
mode. For asynchronous mode, this pin is the receiver frame sync I/
O. For synchronous mode, this pin is used either for transmitter2
output or for serial I/O flag 1.

Port C GPIO (4)--This pin is a General Purpose I/O (GPIO) pin when
the ESSI is not in use.

SC02

GPIOC5

Input/Output

Input or Output

ESSI Serial Control Pin 2 (SC02)--This pin is used for frame sync I/
O. SC02 is the frame sync for both the transmitter and receiver in
synchronous mode and for the transmitter only in asynchronous
mode. When configured as an output, this pin is the internally
generated frame sync signal. When configured as an input, this pin
receives an external frame sync signal for the transmitter (and the
receiver in synchronous operation).

Port C GPIO (5)--This pin is a General Purpose I/O (GPIO) pin when
the ESSI is not in use.

XTAL

Input/Output

Crystal Oscillator Output (XTAL)--This output connects the internal
crystal oscillator output to an external crystal. If an external clock
source other than a crystal oscillator is used, XTAL must be used as
the input.

EXTAL

Input

External Crystal Oscillator Input (EXTAL)--This input should be
connected to an external crystal. If an external clock source other
than a crystal oscillator is used, EXTAL must be tied off. See

Section

4.4.2

CLKO

Output

Clock Output (CLKO)--This pin outputs a buffered clock signal.
When enabled, this signal is the system clock divided by four.

TCK

Input

Test Clock Input (TCK)--This input pin provides a gated clock to
synchronize the test logic and to shift serial data to the JTAG/
Enhanced OnCE port. The pin is connected internally to a pull-down
resistor.

TDI

Input

Test Data Input (TDI)--This input pin provides a serial input data
stream to the JTAG/Enhanced OnCE port. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.

TDO

Output (Z)

Test Data Output (TDO)--This tri-statable output pin provides a
serial output data stream from the JTAG/Enhanced OnCE port. It is
driven in the Shift-IR and Shift-DR controller states, and changes on
the falling edge of TCK.

TMS

Input

Test Mode Select Input (TMS)--This input pin is used to sequence
the JTAG TAP controller's state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.

Table 3. DSP56855 Signal and Package Information for the 100-pin LQFP

Pin
No.

Signal Name

Type

Description

DSP56855 Preliminary Technical Data

MOTOROLA

Part 4 Specifications

4.1 General Characteristics

The DSP56855 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs.
The term "5-volt tolerant" refers to the capability of an I/O pin, built on a 3.3V compatible process
technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture
of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V-
compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V

10% during normal operation without causing damage). This 5V tolerant capability therefore offers the
power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged.

Absolute maximum ratings given in

Table 4

are stress ratings only, and functional operation at the

maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.

The DSP56855 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.

TRST

Input

Test Reset (TRST)--As an input, a low signal on this pin provides a
reset signal to the JTAG TAP controller. To ensure complete
hardware reset, TRST should be asserted whenever RESET is
asserted. The only exception occurs in a debugging environment,
since the Enhanced OnCE/JTAG module is under the control of the
debugger. In this case it is not necessary to assert TRST when
asserting RESET . Outside of a debugging environment RESET
should be permanently asserted by grounding the signal, thus
disabling the Enhanced OnCE/JTAG module on the DSP.

Input/Output

Debug Event (DE)--This is an open-drain, bidirectional, active low
signal. As an input, it is a means of entering debug mode of operation
from an external command controller. As an output, it is a means of
acknowledging that the chip has entered debug mode.

This pin is connected internally to a weak pull-up resistor.

CAUTION

This device contains protective circuitry to guard
against damage due to high static voltage or
electrical fields. However, normal precautions are
advised to avoid application of any voltages higher
than maximum rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate voltage level.

Table 3. DSP56855 Signal and Package Information for the 100-pin LQFP

Pin
No.

Signal Name

Type

Description

General Characteristics

MOTOROLA

DSP56855 Preliminary Technical Data

Table 4. Absolute Maximum Ratings

Characteristic

Symbol

Min

Max

Unit

Supply voltage, core

must not exceed V

DDIO

0.3

+ 2.0

Supply voltage, IO
Supply voltage, analog

DDIO

and V

DDA

must not differ by more that 0.5V

SSIO

0.3

SSA

0.3

SSIO

+ 4.0

DDA

+ 4.0

Digital input voltages
Analog input voltages (XTAL, EXTAL)

INA

SSIO

0.3

SSA

0.3

SSIO

+ 5.5

DDA

+ 0.3

Current drain per pin excluding V

, GND

8 mA

Junction temperature

-40

120

°C

Storage temperature range

STG

-55

150

°C

Table 5. Recommended Operating Conditions

Characteristic

Symbol

Min

Max

Unit

Supply voltage for Logic Power

1.62

1.98

Supply voltage for I/O Power

DDIO

3.0

3.6

Supply voltage for Analog Power

DDA

3.0

3.6

Ambient operating temperature

-40

°C

PLL clock frequency

Assumes clock source is direct clock to EXTAL or crystal oscillator running 2-4MHz. PLL must be enabled, locked, and

selected. The actual frequency depends on the source clock frequency and programming of the CGM module.

pll

240

MHz

Operating Frequency

Master clock is derived from on of the following four sources:

clk

= f

xtal

when the source clock is the direct clock to EXTAL

clk

= f

pll

when PLL is selected

clk

= f

osc

when the source clock is the crystal oscillator and PLL is not selected

clk

= f

extal

when the source clock is the direct clock to EXTAL and PLL is not selected

120

MHz

Frequency of peripheral bus

ipb

MHz

Frequency of external clock

clk

240

MHz

Frequency of oscillator

osc

MHz

Frequency of clock via XTAL

xtal

240

MHz

Frequency of clock via EXTAL

extal

MHz

DSP56855 Preliminary Technical Data

MOTOROLA

Table 6. Thermal Characteristics

See

Section 6.1

for more detail.

Characteristic

100-pin LQFP

Symbol

Value

Unit

Thermal resistance junction-to-ambient
(estimated)

41.2

°C/W

I/O pin power dissipation

I/O

User Determined

Power dissipation

= (I

) + P

I/O

Maximum allowed P

DMAX

) /

Table 7. DC Electrical Characteristics

Operating Conditions: V

= V

SSIO

= V

SSA

= 0 V, V

= 1.62-1.98V, V

DDIO

= V

DDA

3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

Characteristic

Symbol

Min

Typ

Max

Unit

Input high voltage (XTAL/EXTAL)

IHC

DDA

0.8

DDA

+ 0.3

Input low voltage (XTAL/EXTAL)

ILC

-0.3

0.5

Input high voltage

2.0

5.5

Input low voltage

-0.3

0.8

Input current low (pullups disabled)

-1

Input current high (pullups disabled)

-1

Output tri-state current low

OZL

-10

Output tri-state current high

OZH

-10

Output High Voltage

0.7

Output Low Voltage

0.4

Output High Current

Output Low Current

Input capacitance

Output capacitance

OUT

General Characteristics

MOTOROLA

DSP56855 Preliminary Technical Data

supply current @ nominal voltage and 25

Run

Deep Stop

Light Stop

--
--
--

100

2.6

--
--
--

DDIO

supply current @ nominal voltage and 25

Run

DDIO

DDA

supply current @ nominal voltage and 25

Deep Stop

DDA

Low Voltage Interrupt

2.5

2.85

Low Voltage Interrupt Recovery Hysteresis

EIH

Power on Reset

POR

1.5

2.0

Run (operating) I

measured using external square wave clock source (f

osc

= 4MHz) into XTAL. All inputs 0.2V from

rail; no DC loads; outputs unloaded. All ports configured as inputs; measured with all modules enabled. PLL set to 240MHz
out. Running Core, performing 50% NOP and 50% FIR. Clock at 120 MHz.

Deep Stop Mode - Operation frequency = 4 MHz, PLL set to 4 MHz, crystal oscillator and time of day module operat-

ing.

Light Stop Mode - Operation frequency = 120 MHz, PLL set to 240 MHz, crystal oscillator and time of day module

operating.

includes current for core logic, internal memories, and all internal peripheral logic circuitry.

Running core and performing external memory access. Clock at 120 MHz.

When V

drops below V

max value, an interrupt is generated.

Power-on reset occurs whenever the digital supply drops below 1.8V. While power is ramping up, this signal remains

active for as long as the internal 2.5V is below 1.8V no matter how long the ramp up rate is. The internally regulated voltage
is typically 100 mV less than V

during ramp up until 2.5V is reached, at which time it self-regulates.

Table 7. DC Electrical Characteristics (Continued)

Operating Conditions: V

= V

SSIO

= V

SSA

= 0 V, V

= 1.62-1.98V, V

DDIO

= V

DDA

3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

Characteristic

Symbol

Min

Typ

Max

Unit

DSP56855 Preliminary Technical Data

MOTOROLA

4.2 Supply Voltage Sequencing and Separation Cautions

Figure 1

shows two situations to avoid in sequencing the V

and V

DDIO,

DDA

supplies.

Notes: 1. V

rising before V

DDIO

, V

DDA

2. V

DDIO

, V

DDA

rising much faster than V

Figure 3. Supply Voltage Sequencing and Separation Cautions

should not be allowed to rise early (1). This is usually avoided by running the regulator for the V

supply (1.8V) from the voltage generated by the 3.3V V

DDIO

supply, see

Figure 2

. This keeps V

from

rising faster than V

DDIO

should not rise so late that a large voltage difference is allowed between the two supplies (2). Typically

this situation is avoided by using external discrete diodes in series between supplies, as shown in

Figure 2

The series diodes forward bias when the difference between V

DDIO

and V

reaches approximately 2.1,

causing V

to rise as V

DDIO

ramps up. When the V

regulator begins proper operation, the difference

between supplies will typically be 0.8V and conduction through the diode chain reduces to essentially
leakage current. During supply sequencing, the following general relationship should be adhered to:
V

DDIO

> V

> (V

DDIO

- 2.1V)

In practice, V

DDA

is typically connected directly to V

DDIO

with some filtering.

Figure 4. Example Circuit to Control Supply Sequencing

3.3V

1.8V

Time

Supplies Stable

DDIO,

DDA

DC Power

Supp

ly V

l
t
a
ge

3.3V

Regulator

1.8V

Regulator

Supply

DDIO,

DDA

AC Electrical Characteristics

MOTOROLA

DSP56855 Preliminary Technical Data

4.3 AC Electrical Characteristics

Timing waveforms in

Section 4.2

are tested with a V

maximum of 0.8 V and a V

minimum of 2.0 V for

all pins except XTAL, which is tested using the input levels in

Section 4.2

. In

Figure 5

the levels of V

and V

for an input signal are shown.

Figure 5. Input Signal Measurement References

Figure 6

shows the definitions of the following signal states:

Active state, when a bus or signal is driven, and enters a low impedance state.

Tri-stated, when a bus or signal is placed in a high impedance state.

Data Valid state, when a signal level has reached V

or V

OH.

Data Invalid state, when a signal level is in transition between V

and V

OH.

4.4 External Clock Operation

The DSP56855 system clock can be derived from a crystal or an external system clock signal. To generate
a reference frequency using the internal oscillator, a reference crystal must be connected between the
EXTAL and XTAL pins.

4.4.1

Crystal Oscillator

The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency
range specified for the external crystal in

Table 9

. In

Figure 7

a typical crystal oscillator circuit is shown.

Follow the crystal supplier's recommendations when selecting a crystal, because crystal parameters
determine the component values required to provide maximum stability and reliable start-up. The crystal
and associated components should be mounted as close as possible to the EXTAL and XTAL pins to
minimize output distortion and start-up stabilization time.

Figure 6. Signal States

Fall Time

Input Signal

Note: The midpoint is V

+ (V

)/2.

Midpoint1

Low

High

90%

50%

10%

Rise Time

Data Invalid State

Data1

Data2 Valid

Data

Tri-stated

Data3 Valid

Data2

Data3

Data1 Valid

Data Active

DSP56855 Preliminary Technical Data

MOTOROLA

Figure 7. Crystal Oscillator

4.4.2

High Speed External Clock Source (> 4MHz)

The recommended method of connecting an external clock is given in

Figure 8

. The external clock source

is connected to XTAL and the EXTAL pin is held at ground, V

DDA

, or V

DDA

/2. The TOD_SEL bit in

CGM must be set to 0.

Figure 8. Connecting a High Speed External Clock Signal using XTAL

4.4.3

Low Speed External Clock Source (2-4MHz)

The recommended method of connecting an external clock is given in

Figure 9

. The external clock source

is connected to XTAL and the EXTAL pin is held at V

DDA

/2. The TOD_SEL bit in CGM must be set to 0.

Figure 9. Connecting a Low Speed External Clock Signal using XTAL

Sample External Crystal Parameters:
R

= 10M

TOD_SEL bit in CGM must be set to 0

Crystal Frequency = 24 MHz (optimized for 4MHz)

EXTAL XTAL

DSP56855

XTAL

EXTAL

External

GND,

DDA

Clock

(up to 240MHz)

or V

DDA

DSP56855

XTAL

EXTAL

External

Clock

(2-4MHz)

DDA

External Clock Operation

MOTOROLA

DSP56855 Preliminary Technical Data

Figure 10. External Clock Timing

Table 8. External Clock Operation Timing Requirements

Operating Conditions: V

= V

SSIO

= V

SSA

= 0 V, V

= 1.62-1.98V, V

DDIO

= V

DDA

3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

Characteristic

Symbol

Min

Typ

Max

Unit

Frequency of operation (external clock driver)

See

Figure 8

for details on using the recommended connection of an external clock driver.

osc

240

MHz

Clock Pulse Width

6.25

External clock input rise time

2, 4

External clock input rise time is measured from 10% to 90%.

rise

TBD

External clock input fall time

External clock input fall time is measured from 90% to 10%.

Parameters listed are guaranteed by design.

fall

TBD

Table 9. PLL Timing

Operating Conditions: V

= V

SSIO

= V

SSA

= 0 V, V

= 1.62-1.98V, V

DDIO

= V

DDA

3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

Characteristic

Symbol

Min

Typ

Max

Unit

External reference crystal frequency for the PLL

An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.

The PLL is optimized for 4MHz input crystal.

osc

MHz

PLL output frequency

clk

240

MHz

PLL stabilization time

This is the minimum time required after the PLL setup is changed to ensure reliable operation.

plls

External

Clock

Note: The midpoint is V

+ (V

)/2.

90%

50%

10%

90%

50%

10%

fall

rise

DSP56855 Preliminary Technical Data

MOTOROLA

4.5 External Memory Interface Timing

The External Memory Interface is designed to access static memory and peripheral devices.

Figure 11

shows sample timing and parameters that are detailed in

Table 10

The timing of each parameter consists of both a fixed delay portion and a clock related portion; as well as
user controlled wait states. The equation:

t = D + P * (M + W)

should be used to determine the actual time of each parameter. The terms in the above equation are
defined as:

parameter delay time

fixed portion of the delay, due to on-chip path delays.

the period of the system clock, which determines the execution rate of the part (i.e. when the
device is operating at 120 MHz, P = 8.33 ns).

M Fixed portion of a clock period inherent in the design. This number is adjusted to account for

possible clock duty cycle derating.

W the sum of the applicable wait state controls. See the "Wait State Controls" column of

Table 10

for the applicable controls for each parameter. See the EMI chapter of the 83x

Peripheral Manual for details of what each wait state field controls.

Some of the parameters contain two sets of numbers. These parameters have two different paths and clock
edges that must be considered. Check both sets of numbers and use the smaller result. The appropriate entry
may change if the operating frequency of the part changes.

The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters
contain two sets of numbers to account for this difference. The "Wait States Configuration" column of

Table 10

should be used to make the appropriate selection.

Figure 11. External Memory Interface Timing

DRD

RDD

DOH

DOS

DWR

RDWR

WAC

WRRD

AWR

WRWR

ARDD

RDA

RDRD

ARDA

Data Out

Data In

A0-Axx,CS

D0-D15

Note: During read-modify-write instructions and internal instructions, the address lines do not change state.

External Memory Interface Timing

MOTOROLA

DSP56855 Preliminary Technical Data

Table 10. External Memory Interface Timing

Operating Conditions: V

= V

SSIO

= V

SSA

= 0 V, V

= 1.62-1.98 V, V

DDIO

= V

DDA

3.03.6V, T

= 40

° to +120°C, C

50pF, P = 8.333ns

Characteristic

Symbol

Wait States

Configuration

Wait States

Controls

Unit

Address Valid to WR Asserted

AWR

WWS=0 -0.79

0.50

WWSS

WWS>0

-1.98

0.69

WR Width Asserted to WR
Deasserted

WWS=0 -0.86

0.19

WWS

WWS>0

-0.01

0.00

Data Out Valid to WR Asserted

DWR

WWS=0

-1.52

0.00

WWSS

WWS=0 -

5.69

0.25

WWS>0

-2.10

0.19

WWS>0

-4.66

0.50

Valid Data Out Hold Time after WR
Deasserted

DOH

-1.47

0.25

WWSH

Valid Data Out Set Up Time to WR
Deasserted

DOS

-2.36

0.19

WWS,WWSS

-4.67

0.50

Valid Address after WR
Deasserted

WAC

-1.60

0.25

WWSH

RD Deasserted to Address Invalid

RDA

- 0.44

0.00

RWSH

Address Valid to RD Deasserted

ARDD

-2.07

1.00

RWSS,RWS

Valid Input Data Hold after RD
Deasserted

DRD

0.00

N/A

N/A since device captures data before it deasserts RD

RD Assertion Width

-1.34

1.00

RWS

Address Valid to Input Data Valid

-10.27

1.00

RWSS,RWS

-13.5

1.19

Address Valid to RD Asserted

ARDA

- 0.94

0.00

RWSS

RD Asserted to Input Data Valid

RDD

-9.53

1.00

RWSS,RWS

-12.64

1.19

WR Deasserted to RD Asserted

WRRD

-0.75

0.25

WWSH,RWSS

RD Deasserted to RD Asserted

RDRD

-0.16

If RWSS = RWSH = 0, RD does not deassert during back-to-back reads and D=0.00 should be used.

0.00

RWSS,RWSH

WR Deasserted to WR Asserted

WRWR

WWS=0

-0.44

0.75

WWSS, WWSH

WWS>0

-0.11

1.00

RD Deasserted to WR Asserted

RDWR

0.14

0.50

MDAR, BMDAR,

RWSH, WWSS

-0.57

0.69

DSP56855 Preliminary Technical Data

MOTOROLA

4.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Table 11. Reset, Stop, Wait, Mode Select, and Interrupt Timing

1, 2

Operating Conditions: V

= V

SSIO

= V

SSA

= 0 V, V

= 1.62-1.98V, V

DDIO

= V

DDA

3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

In the formulas, T = clock cycle. For f

= 120MHz operation and f

ipb

= 60MHz, T = 8.33ns.

Parameters listed are guaranteed by design.

Characteristic

Symbol

Min

Max

Unit

See

Figure

RESET Assertion to Address, Data and Control
Signals High Impedance

RAZ

Figure 12

Minimum RESET Assertion Duration

At reset, the PLL is disabled and bypassed. The part is then put into Run mode and t

clk

assumes the period of the source

clock, t

xtal

, t

extal

or t

osc

Figure 12

RESET Deassertion to First External Address Output

RDA

120T

Figure 12

Edge-sensitive Interrupt Request Width

IRW

1T + 3

Figure 13

IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine

IDM

18T

Figure 14

IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine

18T

Figure 14

IRQA Low to First Valid Interrupt Vector Address Out

recovery from Wait State

The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Wait state.

This is not the minimum required so that the IRQA interrupt is accepted.

IRI

13T

Figure 15

IRQA Width Assertion to Recover from Stop State

Fast

Normal

7, 8

This interrupt instruction fetch is visible on the pins only in Mode 3.

Fast stop mode:

Fast stop recovery applies when fast stop mode recovery is requested (OMR bit 6 is set to 1). The PLL and the master

clock are unaffected by stop mode entry. Recovery takes one less cycle and t

clk

will continue with the same value it had before

stop mode was entered.

Normal stop mode:

As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master

clock, recovery will take an extra cycle (to restart the clock), and t

clk

will resume at the input clock source rate.

ET = External Clock period; for an external crystal frequency of 4MHz, ET=250ns.

8ET

--
--

ns
ns

Figure 16

Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)

Fast

Normal

6,7

--
--

13T

25ET

ns
ns

Figure 16

RSTO pulse width

normal operation
internal reset mode

RSTO

128ET

8ET

--
--

Figure 17

Reset, Stop, Wait, Mode Select, and Interrupt Timing

MOTOROLA

DSP56855 Preliminary Technical Data

Figure 12. Asynchronous Reset Timing

Figure 13. External Interrupt Timing (Negative-Edge-Sensitive)

Figure 14. External Level-Sensitive Interrupt Timing

Figure 15. Interrupt from Wait State Timing

First Fetch

A0A20,

D0D15

CS,

RD, WR

RESET

First Fetch

RDA

RAZ

IRQA

IRQB

IRW

A0A20,

CS,

IRQA,

IRQB

First Interrupt Instruction Execution

a) First Interrupt Instruction Execution

Purpose

I/O Pin

IRQA,

IRQB

b) General Purpose I/O

IDM

General

Instruction Fetch

IRQA,

IRQB

First Interrupt Vector

A0A20,

CS,

RD, WR

IRI

DSP56855 Preliminary Technical Data

MOTOROLA

Figure 16. Recovery from Stop State Using Asynchronous Interrupt Timing

Figure 17. Reset Output Timing

4.7 Host Interface Port

Table 12. Host Interface Port Timing

Operating Conditions: V

= V

SSIO

= V

SSA

= 0 V, V

= 1.62-1.98V, V

DDIO

= V

DDA

3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

The formulas: T = clock cycle. f ipb = 60MHz, T = 16.7ns.

Characteristic

Symbol

Min

Max

Unit

See Figure

Access time

TACKDV

Figure 18

Disable time

TACKDZ

Figure 18

Time to disassert

TACKREQH

3.5

Figure 18

Figure 21

Lead time

TREQACKL

Figure 18

Figure 21

Access time

TRADV

Figure 19
Figure 20

Disable time

TRADX

Figure 19
Figure 20

Disable time

TRADZ

Figure 19
Figure 20

Setup time

TDACKS

Figure 21

Hold time

TACKDH

Figure 21

Setup time

TADSS

Figure 22
Figure 23

Hold time

TDSAH

Figure 22
Figure 23

Pulse width

TWDS

Figure 22
Figure 23

Time to re-assert
1. After second write in 16-bit mode
2. After first write in 16-bit mode or after write in 8-bit mode

TACKREQL

4T + 5

5T + 9

ns
ns

Figure 18

Figure 21

Not IRQA Interrupt Vector

IRQA

A0A20,

CS,

RD, WR

First Instruction Fetch

RESET

RSTO

Quad Timer Timing

MOTOROLA

DSP56855 Preliminary Technical Data

4.8 Quad Timer Timing

Figure 24. Timer Timing

4.9 Enhanced Synchronous Serial Interface (ESSI) Timing

Table 13. Quad Timer Timing

1, 2

Operating Conditions: V

= V

SSIO

= V

SSA

= 0 V, V

= 1.62-1.98V, V

DDIO

= V

DDA

3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

In the formulas listed, T = clock cycle. For f

= 120MHz operation and fipb = 60MHz, T = 8.33ns.

Parameters listed are guaranteed by design.

Characteristic

Symbol

Min

Max

Unit

Timer input period

2T + 3

Timer input high/low period

INHL

1T + 3

Timer output period

OUT

2T - 3

Timer output high/low period

OUTHL

1T - 3

Table 14. ESSI Master Mode

Switching Characteristics

Operating Conditions: V

= V

SSIO

= V

SSA

= 0 V, V

= 1.62-1.98V, V

DDIO

= V

DDA

3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

Parameter

Symbol

Min

Typ

Max

Units

SCK frequency

MHz

SCK period

SCKW

66.7

SCK high time

SCKH

33.4

SCK low time

SCKL

33.4

Output clock rise/fall time

Delay from SCK high to SC2 (bl) high - Master

TFSBHM

-1.0

1.0

Delay from SCK high to SC2 (wl) high - Master

TFSWHM

-1.0

1.0

Timer Inputs

Timer Outputs

INHL

OUTHL

OUT

DSP56855 Preliminary Technical Data

MOTOROLA

Delay from SC0 high to SC1 (bl) high - Master

RFSBHM

-1.0

1.0

Delay from SC0 high to SC1 (wl) high - Master

RFSWHM

-1.0

1.0

Delay from SCK high to SC2 (bl) low - Master

TFSBLM

-1.0

1.0

Delay from SCK high to SC2 (wl) low - Master

TFSWLM

-1.0

1.0

Delay from SC0 high to SC1 (bl) low - Master

RFSBLM

-1.0

1.0

Delay from SC0 high to SC1 (wl) low - Master

RFSWLM

-1.0

1.0

SCK high to STD enable from high impedance - Master

TXEM

-0.1

SCK high to STD valid - Master

TXVM

-0.1

SCK high to STD not valid - Master

TXNVM

-0.1

SCK high to STD high impedance - Master

TXHIM

-4

SRD Setup time before SC0 low - Master

SRD Hold time after SC0 low - Master

Synchronous Operation (in addition to standard internal clock parameters)

SRD Setup time before SCK low - Master

TSM

SRD Hold time after SCK low - Master

THM

1. Master mode is internally generated clocks and frame syncs
2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for an 120MHz part.
3. All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)

and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync
have been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in
the tables and in the figures.

4. 50 percent duty cycle
5. bl = bit length; wl = word length

Table 14. ESSI Master Mode

Switching Characteristics (Continued)

Operating Conditions: V

= V

SSIO

= V

SSA

= 0 V, V

= 1.62-1.98V, V

DDIO

= V

DDA

3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

Parameter

Symbol

Min

Typ

Max

Units

Enhanced Synchronous Serial Interface (ESSI) Timing

MOTOROLA

DSP56855 Preliminary Technical Data

Figure 25. Master Mode Timing Diagram

Table 15: ESSI Slave Mode

Switching Characteristics

Operating Conditions: V

= V

SSIO

= V

SSA

= 0 V, V

= 1.62-1.98V, V

DDIO

= V

DDA

3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

Parameter

Symbol

Min

Typ

Max

Units

SCK frequency

MHz

SCK period

SCKW

66.7

SCK high time

SCKH

33.4

SCK low time

SCKL

33.4

Output clock rise/fall time

Delay from SCK high to SC2 (bl) high - Slave

TFSBHS

-1

Delay from SCK high to SC2 (wl) high - Slave

TFSWHS

-1

Delay from SC0 high to SC1 (bl) high - Slave

RFSBHS

-1

THM

TSM

RFSWLM

RFSWHM

RFBLM

RFSBHM

TXHIM

TXNVM

TXVM

TXEM

TFSWLM

TFSWHM

TFSBLM

TFSBHM

SCKL

SCKW

SCKH

First Bit

Last Bit

SCK output

SC2 (bl) output

SC2 (wl) output

STD

SC0 output

SC1 (bl) output

SC1 (wl) output

SRD

DSP56855 Preliminary Technical Data

MOTOROLA

Delay from SC0 high to SC1 (wl) high - Slave

RFSWHS

-1

Delay from SCK high to SC2 (bl) low - Slave

TFSBLS

-29

Delay from SCK high to SC2 (wl) low - Slave

TFSWLS

-29

Delay from SC0 high to SC1 (bl) low - Slave

RFSBLS

-29

Delay from SC0 high to SC1 (wl) low - Slave

RFSWLS

-29

SCK high to STD enable from high impedance - Slave

TXES

SCK high to STD valid - Slave

TXVS

SC2 high to STD enable from high impedance (first bit) - Slave

FTXES

SC2 high to STD valid (first bit) - Slave

FTXVS

SCK high to STD not valid - Slave

TXNVS

SCK high to STD high impedance - Slave

TXHIS

SRD Setup time before SC0 low - Slave

SRD Hold time after SC0 low - Slave

Synchronous Operation (in addition to standard external clock parameters)

SRD Setup time before SCK low - Slave

TSS

SRD Hold time after SCK low - Slave

THS

1. Slave mode is externally generated clocks and frame syncs
2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for a 120MHz part.
3. All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)

4. 50 percent duty cycle
5. bl = bit length; wl = word length

Table 15: ESSI Slave Mode

Switching Characteristics (Continued)

Operating Conditions: V

= V

SSIO

= V

SSA

= 0 V, V

= 1.62-1.98V, V

DDIO

= V

DDA

3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

Parameter

Symbol

Min

Typ

Max

Units

Serial Communication Interface (SCI) Timing

MOTOROLA

DSP56855 Preliminary Technical Data

Figure 26. Slave Mode Clock Timing

4.10 Serial Communication Interface (SCI) Timing

Table 16. SCI Timing

Operating Conditions: V

= V

SSIO

= V

SSA

= 0 V, V

= 1.62-1.98V, V

DDIO

= V

DDA

3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

Characteristic

Symbol

Min

Max

Unit

Baud Rate

MAX

is the frequency of operation of the system clock in MHz.

MAX

)/(32)

Mbps

RXD

Pulse Width

The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.

RXD

0.965/BR

1.04/BR

TXD

Pulse Width

The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.

Parameters listed are guaranteed by design.

TXD

0.965/BR

1.04/BR

THS

TSS

RFSWLS

RFSWHS

RFBLS

RFSBHS

TXHIS

TXNVS

FTXVS

TXVS

FTXES

TXES

TFSWLS

TFSWHS

TFSBLS

TFSBHS

SCKL

SCKW

SCKH

First Bit

Last Bit

SCK input

SC2 (bl) input

SC2 (wl) input

STD

SC0 input

SC1 (bl) input

SC1 (wl) input

SRD

DSP56855 Preliminary Technical Data

MOTOROLA

Figure 27. RXD Pulse Width

Figure 28. TXD Pulse Width

4.11 JTAG Timing

Table 17. JTAG Timing

1, 3

Operating Conditions: V

= V

SSIO

= V

SSA

= 0 V, V

= 1.62-1.98V, V

DDIO

= V

DDA

3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 120MHz

operation, T = 8.33ns.

Characteristic

Symbol

Min

Max

Unit

TCK frequency of operation

TCK frequency of operation must be less than 1/4 the processor rate.

Parameters listed are guaranteed by design.

MHz

TCK cycle time

33.3

TCK clock pulse width

16.6

TMS, TDI data setup time

TMS, TDI data hold time

TCK low to TDO data valid

TCK low to TDO tri-state

TRST assertion time

TRST

DE assertion time

RXD

SCI receive

data pin

(Input)

RXD

TXD

SCI receive

data pin

(Input)

TXD

DSP56855 Preliminary Technical Data

MOTOROLA

4.12 GPIO Timing

Figure 33. GPIO Timing

Table 18. GPIO Timing

1, 2

Operating Conditions: V

= V

SSIO

= V

SSA

= 0 V, V

= 1.62-1.98V, V

DDIO

= V

DDA

3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

In the formulas listed, T = clock cycle. For f

= 120MHz operation and fipb = 60MHz, T = 8.33ns

Parameters listed are guaranteed by design.

Characteristic

Symbol

Min

Max

Unit

GPIO input period

2T + 3

GPIO input high/low period

INHL

1T + 3

GPIO output period

OUT

2T - 3

GPIO output high/low period

OUTHL

1T - 3

GPIO Inputs

GPIO Outputs

INHL

OUTHL

OUT

Package and Pin-Out Information DSP56855

MOTOROLA

DSP56855 Preliminary Technical Data

Part 5 Packaging

5.1 Package and Pin-Out Information DSP56855

This section contains package and pin-out information for the 100-pin LQFP configuration of the
DSP56855.

Figure 34. Top View, DSP56855 100-pin LQFP Package

PIN 1

PIN 26

PIN 51

PIN 76

DDIO

SSIO

A0
A1
A2
A3

MODA
MODB

MODC

DDIO

SSIO

IRQA
IRQB

DDA

SSA

XTAL

EXTAL

A4
A5
A6
A7

RST

RESET

DDI

SSI

A10

TRST

TDO

TDI

DDI

SSI

A14

A15

TXD1
RXD1
V

SSIO

DDIO

D5
D4
D3
D2
D1
V

CS3
CS2
CS1
CS0
V

SSIO

D0
V

DDIO

A20
A19
A18
A17
A16
TXDO
RXD0

I
O

DDI

SC0

SCK0

SRD0

I
O

DDI

I
O

DDI

Motorola

DSP56855

ORIENTATION

MARK

A12

A13

DDI

SSI

DSP56855 Preliminary Technical Data

MOTOROLA

Table 19. DSP56855 Pin Identification By Pin Number

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

DDIO

CLKO

RXD0

DDIO

SSIO

RSTO

TXD0

TIO0

RESET

A16

SSIO

DDIO

A17

SSIO

A18

A19

A20

A10

DDIO

D10

A11

SSIO

MODA

CS0

DDIO

MODB

CS1

SSIO

MODC

TRST

CS2

STD0

DDIO

TDO

CS3

SRD0

SSIO

TDI

SCK0

IRQA

TMS

SC00

IRQB

TCK

SC01

DDA

DDIO

SC02

SSA

SSIO

D11

XTAL

A12

D12

EXTAL

A13

DDIO

A14

DDIO

SSIO

A15

SSIO

D13

DDIO

RXD1

D14

SSIO

TXD1

100

D15

Package and Pin-Out Information DSP56855

MOTOROLA

DSP56855 Preliminary Technical Data

Figure 35. 100-pin LQPF Mechanical Information

NOTES:
1.

DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

CONTROLLING DIMENSION: MILLIMETER.

DATUM PLANE -AB- IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING
LINE.

DATUMS -T-, -U-, AND -Z- TO BE DETERMINED
AT DATUM PLANE -AB-.

DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE -AC-.

DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT
DATUM PLANE -AB-.

DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.350 (0.014). DAMBAR CAN NOT BE LOCATED
ON THE LOWER RADIUS OR THE FOOT.
MINIMUM SPACE BETWEEN PROTRUSION
AND AN ADJACENT LEAD IS 0.070 (0.003).

MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.003).

EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.

SEATING

(24X PER SIDE)

GAUGE PLANE

DETAIL AD

SECTION AE-AE

96X

DIM MIN

MAX

MIN

MAX

INCHES

MILLIMETERS

13.950 14.050

0.549

0.553

13.950 14.050

0.549

0.553

1.400

1.600

0.055

0.063

0.170

0.270

0.007

0.011

1.350

1.450

0.053

0.057

0.170

0.230

0.007

0.009

0.500 BSC

0.020 BSC

0.050

0.150

0.002

0.006

0.090

0.200

0.004

0.008

0.500

0.700

0.020

0.028

12 REF

0.090

0.160

0.004

0.006

0.150

0.250

0.006

0.010

15.950 16.050

0.628

0.632

15.950 16.050

0.628

0.632

0.200 REF

0.008 REF

1.000 REF

0.039 REF

CASE 842F-01

-T-

T-U

0.15 (0.006)

T-

.
0

06)

T-

(

.
006

)

-U-

T-U

0.15 (0.006)

-Z-

-AC-

PLANE

-AB-

T-U

0.20 (0.008)

0.100 (0.004) AC

0.25 (0.010)

DSP56855 Preliminary Technical Data

MOTOROLA

Part 6 Design Considerations

6.1 Thermal Design Considerations

An estimation of the chip junction temperature, T

, in

°C can be obtained from the equation:

Equation 1:

= T

+ (P

x R

)

Where:

= ambient temperature °C

= package junction-to-ambient thermal resistance °C/W

= power dissipation in package

Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and
a case-to-ambient thermal resistance:

Equation 2:

= R

+ R

Where:

= package junction-to-ambient thermal resistance °C/W

= package junction-to-case thermal resistance °C/W

= package case-to-ambient thermal resistance °C/W

is device-related and cannot be influenced by the user. The user controls the thermal environment to

change the case-to-ambient thermal resistance, R

. For example, the user can change the air flow around

the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the
heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device
thermal performance may need the additional modeling capability of a system level thermal simulation tool.

The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the
package is mounted. Again, if the estimations obtained from R

do not satisfactorily answer whether the

thermal performance is adequate, a system level model may be appropriate.

A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:

Measure the thermal resistance from the junction to the outside surface of the package (case) closest
to the chip mounting area when that surface has a proper heat sink. This is done to minimize
temperature variation across the surface.

Measure the thermal resistance from the junction to where the leads are attached to the case. This
definition is approximately equal to a junction to board thermal resistance.

Use the value obtained by the equation (T

)/P

where T

is the temperature of the package

case determined by a thermocouple.

As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the
first definition. From a practical standpoint, that value is also suitable for determining the junction
temperature from a case thermocouple reading in forced convection environments. In natural convection,
using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading

Electrical Design Considerations

MOTOROLA

DSP56855 Preliminary Technical Data

on the case of the package will estimate a junction temperature slightly hotter than actual. Hence, the new
thermal metric, Thermal Characterization Parameter, or

, has been defined to be (T

)/P

. This value

gives a better estimate of the junction temperature in natural convection when using the surface temperature
of the package. Remember that surface temperature readings of packages are subject to significant errors
caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor.
The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the
package with thermally conductive epoxy.

6.2 Electrical Design Considerations

Use the following list of considerations to assure correct DSP operation:

Provide a low-impedance path from the board power supply to each V

pin on the DSP, and from

the board ground to each V

(GND) pin.

The minimum bypass requirement is to place six 0.010.1

µF capacitors positioned as close as

possible to the package supply pins. The recommended bypass configuration is to place one bypass
capacitor on each of the ten V

pairs, including V

DDA

SSA.

Ensure that capacitor leads and associated printed circuit traces that connect to the chip V

and

(GND) pins are less than 0.5 inch per capacitor lead.

Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for V

and GND.

Bypass the V

and GND layers of the PCB with approximately 100

µF, preferably with a high-

grade capacitor such as a tantalum capacitor.

Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal.

Consider all device loads as well as parasitic capacitance due to PCB traces when calculating
capacitance. This is especially critical in systems with higher capacitive loads that could create
higher transient currents in the V

and GND circuits.

All inputs must be terminated (i.e., not allowed to float) using CMOS levels.

Take special care to minimize noise levels on the V

DDA

and V

SSA

pins.

When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pull-
up device.

CAUTION

This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.

DSP56855 Preliminary Technical Data

MOTOROLA

Designs that utilize the TRST pin for JTAG port or Enhance OnCE module functionality (such as
development or debugging systems) should allow a means to assert TRST whenever RESET is
asserted, as well as a means to assert TRST independently of RESET. Designs that do not require
debugging functionality, such as consumer products, should tie these pins together.

The internal POR (Power on Reset) will reset the part at power on with reset asserted or pulled high
but requires that TRST be asserted at power on.

Part 7 Ordering Information

Table 20

lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales

office or authorized distributor to determine availability and to order parts.

Table 20. DSP56855 Ordering Information

Part

Supply

Voltage

Package Type

Pin

Count

Frequency

(MHz)

Order Number

DSP56855

1.8V, 3.3V

Low-Profile Quad Flat Pack (LQFP)

100

120

DSP56855BU120

DSP56855/D

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