This document contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing specifications for the MPC860 family.

This document contains the following topics:

Topic

Page

Section 1, "Overview"

Section 2, "Features"

Section 3, "Maximum Tolerated Ratings"

Section 4, "Thermal Characteristics"

Section 5, "Power Dissipation"

Section 6, "DC Characteristics"

Section 7, "Thermal Calculation and Measurement"

Section 8, "Layout Practices"

Section 9, "Bus Signal Timing"

Section 10, "IEEE 1149.1 Electrical Specifications"

Section 11, "CPM Electrical Characteristics"

Section 12, "UTOPIA AC Electrical Specifications"

Section 13, "FEC Electrical Characteristics"

Section 14, "Mechanical Data and Ordering Information"

Section 15, "Document Revision History"

Advanced Information

MPC860EC/D
Rev. 6.2, 8/2003

MPC860 Family
Hardware Specifications

MPC860 Family Hardware Specifications

MOTOROLA

Overview

The MPC860 Quad Integrated Communications Controller (PowerQUICCTM) is a versatile one-chip
integrated microprocessor and peripheral combination designed for a variety of controller applications. It
particularly excels in both communications and networking systems. The PowerQUICC unit is referred to
as the MPC860 in this manual.

The MPC860 is a derivative of Motorola's MC68360 Quad Integrated Communications Controller
(QUICC

), referred to here as the QUICC, that implements the PowerPC architecture. The CPU on the

MPC860 is a 32-bit PowerPC

core that incorporates memory management units (MMUs) and instruction

and data caches and that implements the PowerPC instruction set. The communications processor module
(CPM) from the MC68360 QUICC has been enhanced by the addition of the inter-integrated controller (I

channel. The memory controller has been enhanced, enabling the MPC860 to support any type of memory,
including high-performance memories and new types of DRAMs. A PCMCIA socket controller supports up
to two sockets. A real-time clock has also been integrated.

Table 1 shows the functionality supported by the members of the MPC860 family.

Features

The following list summarizes the key MPC860 features:

Embedded single-issue, 32-bit PowerPC

core (implementing the PowerPC architecture) with

thirty-two 32-bit general-purpose registers (GPRs)

-- The core performs branch prediction with conditional prefetch, without conditional execution

-- 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1)

16-Kbyte instruction caches are four-way, set-associative with 256 sets; 4-Kbyte instruction

caches are two-way, set-associative with 128 sets.

8-Kbyte data caches are two-way, set-associative with 256 sets; 4-Kbyte data caches are

two-way, set-associative with 128 sets.

Table 1. MPC860 Family Functionality

Part

Cache (Kbytes)

Ethernet

ATM

SCC Ref.

Supporting documentation for these devices refers to the following:

1. MPC860 PowerQUICC Family User's Manual (MPC860UM/D, Rev. 2).

2. MPC855T User's Manual (MPC855TUM/D, Rev. 1).

Instruction

Cache

Data Cache

10T

10/100

MPC860DE

Up to 2

MPC860DT

Up to 2

yes

MPC860DP

Up to 2

yes

MPC860EN

Up to 4

MPC860SR

Up to 4

yes

MPC860T

Up to 4

yes

MPC860P

Up to 4

yes

MPC855T

yes

MOTOROLA

MPC860 Family Hardware Specifications

Features

Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)

cache blocks.

Caches are physically addressed, implement a least recently used (LRU) replacement

algorithm, and are lockable on a cache block basis.

-- Instruction and data caches are two-way, set-associative, physically addressed, LRU

replacement, and lockable on-line granularity.

-- MMUs with 32-entry TLB, fully associative instruction, and data TLBs

-- MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address

spaces and 16 protection groups

-- Advanced on-chip-emulation debug mode

Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)

32 address lines

Operates at up to 80 MHz

Memory controller (eight banks)

-- Contains complete dynamic RAM (DRAM) controller

-- Each bank can be a chip select or RAS to support a DRAM bank

-- Up to 15 wait states programmable per memory bank

-- Glueless interface to DRAM, SIMMS, SRAM, EPROM, Flash EPROM, and other memory

devices.

-- DRAM controller programmable to support most size and speed memory interfaces

-- Four CAS lines, four WE lines, one OE line

-- Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)

-- Variable block sizes (32 Kbyte to 256 Mbyte)

-- Selectable write protection

-- On-chip bus arbitration logic

General-purpose timers

-- Four 16-bit timers or two 32-bit timers

-- Gate mode can enable/disable counting

-- Interrupt can be masked on reference match and event capture

System integration unit (SIU)

-- Bus monitor

-- Software watchdog

-- Periodic interrupt timer (PIT)

-- Low-power stop mode

-- Clock synthesizer

-- Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture

-- Reset controller

-- IEEE 1149.1 test access port (JTAG)

Interrupts

-- Seven external interrupt request (IRQ) lines

-- 12 port pins with interrupt capability

MPC860 Family Hardware Specifications

MOTOROLA

Features

-- 23 internal interrupt sources

-- Programmable priority between SCCs

-- Programmable highest priority request

10/100 Mbps Ethernet support, fully compliant with the IEEE 802.3u Standard (not available when
using ATM over UTOPIA interface)

ATM support compliant with ATM forum UNI 4.0 specification

-- Cell processing up to 5070 Mbps at 50-MHz system clock

-- Cell multiplexing/demultiplexing

-- Support of AAL5 and AAL0 protocols on a per-VC basis. AAL0 support enables OAM and

software implementation of other protocols).

-- ATM pace control (APC) scheduler, providing direct support for constant bit rate (CBR) and

unspecified bit rate (UBR) and providing control mechanisms enabling software support of
available bit rate (ABR)

-- Physical interface support for UTOPIA (10/100-Mbps is not supported with this interface) and

byte-aligned serial (for example, T1/E1/ADSL)

-- UTOPIA-mode ATM supports level-1 master with cell-level handshake, multi-PHY (up to 4

physical layer devices), connection to 25-, 51-, or 155-Mbps framers, and UTOPIA/system
clock ratios of 1/2 or 1/3.

-- Serial-mode ATM connection supports transmission convergence (TC) function for

T1/E1/ADSL lines; cell delineation; cell payload scrambling/descrambling; automatic
idle/unassigned cell insertion/stripping; header error control (HEC) generation, checking, and
statistics.

Communications processor module (CPM)

-- RISC communications processor (CP)

-- Communication-specific commands (for example,

GRACEFUL

STOP

TRANSMIT

ENTER

HUNT

MODE

, and

RESTART

TRANSMIT

)

-- Supports continuous mode transmission and reception on all serial channels

-- Up to 8Kbytes of dual-port RAM

-- 16 serial DMA (SDMA) channels

-- Three parallel I/O registers with open-drain capability

Four baud-rate generators (BRGs)

-- Independent (can be connected to any SCC or SMC)

-- Allow changes during operation

-- Autobaud support option

Four serial communications controllers (SCCs)

-- Ethernet/IEEE 802.3 optional on SCC14, supporting full 10-Mbps operation (available only

on specially programmed devices).

-- HDLC/SDLC

(all channels supported at 2 Mbps)

-- HDLC bus (implements an HDLC-based local area network (LAN))

-- Asynchronous HDLC to support PPP (point-to-point protocol)

-- AppleTalk

-- Universal asynchronous receiver transmitter (UART)

-- Synchronous UART

MOTOROLA

MPC860 Family Hardware Specifications

Features

-- Serial infrared (IrDA)

-- Binary synchronous communication (BISYNC)

-- Totally transparent (bit streams)

-- Totally transparent (frame based with optional cyclic redundancy check (CRC))

Two SMCs (serial management channels)

-- UART

-- Transparent

-- General circuit interface (GCI) controller

-- Can be connected to the time-division multiplexed (TDM) channels

One SPI (serial peripheral interface)

-- Supports master and slave modes

-- Supports multimaster operation on the same bus

One I

C (inter-integrated circuit) port

-- Supports master and slave modes

-- Multiple-master environment support

Time-slot assigner (TSA)

-- Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation

-- Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined

-- 1- or 8-bit resolution

-- Allows independent transmit and receive routing, frame synchronization, clocking

-- Allows dynamic changes

-- Can be internally connected to six serial channels (four SCCs and two SMCs)

Parallel interface port (PIP)

-- Centronics interface support

-- Supports fast connection between compatible ports on the MPC860 or the MC68360

PCMCIA interface

-- Master (socket) interface, release 2.1 compliant

-- Supports two independent PCMCIA sockets

-- Eight memory or I/O windows supported

Low power support

-- Full on--all units fully powered

-- Doze--core functional units disabled, except time base decrementer, PLL, memory controller,

RTC, and CPM in low-power standby

-- Sleep--all units disabled, except RTC and PIT, PLL active for fast wake up

-- Deep sleep--all units disabled including PLL, except RTC and PIT

-- Power down mode-- all units powered down, except PLL, RTC, PIT, time base, and

decrementer

Debug interface

-- Eight comparators: four operate on instruction address, two operate on data address, and two

operate on data

-- Supports conditions:

< >

MPC860 Family Hardware Specifications

MOTOROLA

Maximum Tolerated Ratings

-- Each watchpoint can generate a break-point internally

3.3 V operation with 5-V TTL compatibility except EXTAL and EXTCLK

357-pin ball grid array (BGA) package

Maximum Tolerated Ratings

This section provides the maximum tolerated voltage and temperature ranges for the MPC860. Table 2
provides the maximum ratings.

This device contains circuitry protecting against damage due to high-static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced, if unused
inputs are tied to an appropriate logic voltage level (for example, either GND or V

Table 2. Maximum Tolerated Ratings

(GND = 0 V)

Rating

Symbol

Value

Unit

Supply Voltage

The power supply of the device must start its ramp from 0.0 V.

DDH

0.3 to 4.0

DDL

0.3 to 4.0

KAPWR

0.3 to 4.0

VDDSYN

0.3 to 4.0

Input Voltage

Functional operating conditions are provided with the DC electrical specifications in Table 5. Absolute maximum
ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may
affect device reliability or cause permanent damage to the device.

Caution

: All inputs that tolerate 5 V cannot be more than 2.5 V greater than the supply voltage. This restriction applies

to power-up and normal operation (that is, if the MPC860 is unpowered, voltage greater than 2.5 V must not be
applied to its inputs).

GND 0.3 to VDDH

Temperature

(Standard)

Minimum temperatures are guaranteed as ambient temperature, T

. Maximum temperatures are guaranteed as

junction temperature, T

A(min)

°C

j(max)

°C

Temperature

(Extended)

A(min)

°C

j(max)

°C

Storage Temperature Range

stg

55 to 150

°C

MOTOROLA

MPC860 Family Hardware Specifications

Thermal Characteristics

Table 3 shows the thermal characteristics for the MPC860.

Table 3. MPC860 Thermal Resistance Data

Rating

Environment

Symbol

Rev A

Rev

B, C, D

Unit

Junction to Ambient

Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.

Natural Convection

Single layer board (1s)

Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

°C/W

Four layer board (2s2p)

JMA

Per JEDEC JESD51-6 with the board horizontal.

Air Flow (200 ft/min)

Single layer board (1s)

JMA

Four layer board (2s2p)

JMA

Junction to Board

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.

Junction to Case

Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate
method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. For exposed
pad packages where the pad would be expected to be soldered, junction to case thermal resistance is a simulated
value from the junction to the exposed pad without contact resistance.

Junction to Package
Top

Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.

Natural Convection

Air Flow (200 ft/min)

MPC860 Family Hardware Specifications

MOTOROLA

Power Dissipation

Table 4 provides power dissipation information. The modes are 1:1, where CPU and bus speeds are equal,
and 2:1 mode, where CPU frequency is twice bus speed.

NOTE

Values in Table 4" represent V

DDL

-based power dissipation and do not

include I/O power dissipation over V

DDH

. I/O power dissipation varies

widely by application due to buffer current, depending on external
circuitry.

Table 4. Power Dissipation (P

)

Die Revision

Frequency (MHz)

Typical

Typical power dissipation is measured at 3.3 V.

Maximum

Maximum power dissipation is measured at 3.5 V.

Unit

A.3 and Previous

450

550

700

850

870

1050

B.1 and C.1

375

TBD

575

TBD

750

TBD

D.3 and D.4
(1:1 Mode)

656

735

TBD

D.3 and D.4
(2:1 Mode)

722

762

851

909

MOTOROLA

MPC860 Family Hardware Specifications

DC Characteristics

Table 5 provides the DC electrical characteristics for the MPC860.

Table 5. DC Electrical Specifications

Characteristic

Symbol

Min

Max

Unit

Operating Voltage at 40 MHz or Less

DDH

, V

DDL

, VDDSYN

3.0

3.6

KAPWR

(power-down mode)

2.0

3.6

KAPWR

(all other operating modes)

DDH

0.4

DDH

Operating Voltage Greater than 40 MHz

DDH

, V

DDL

, KAPWR,

VDDSYN

3.135

3.465

KAPWR

(power-down mode)

2.0

3.6

KAPWR

(all other operating modes)

DDH

0.4

DDH

Input High Voltage (All Inputs Except EXTAL and
EXTCLK)

2.0

5.5

Input Low Voltage

GND

0.8

EXTAL, EXTCLK Input High Voltage

IHC

0.7

DDH

)

DDH

+ 0.3

Input Leakage Current, V

= 5.5 V (Except TMS,

TRST, DSCK, and DSDI Pins)

100

µA

Input Leakage Current, V

= 3.6 V (Except TMS,

TRST, DSCK, and DSDI Pins)

µA

Input Leakage Current, V

= 0 V (Except TMS,

TRST, DSCK, and DSDI Pins)

µA

Input Capacitance

Input capacitance is periodically sampled.

Output High Voltage, I

= 2.0 mA, V

DDH

= 3.0 V

(Except XTAL, XFC, and Open Drain Pins)

2.4

Output Low Voltage

IOL = 2.0 mA, CLKOUT
IOL = 3.2 mA

IOL = 5.3 mA

IOL = 7.0 mA, TXD1/PA14, TXD2/PA12
IOL = 8.9 mA, TS, TA, TEA, BI, BB,

HRESET, SRESET

0.5

MPC860 Family Hardware Specifications

MOTOROLA

Thermal Calculation and Measurement

For the following discussions, P

= (V

× I

) + PI/O, where PI/O is the power dissipation of the I/O

drivers.

7.1

Estimation with Junction-to-Ambient Thermal
Resistance

An estimation of the chip junction temperature, T

, in °C can be obtained from the equation:

= T

+ (R

× P

)

where:

= ambient temperature (ºC)

= package junction-to-ambient thermal resistance (ºC/W)

= power dissipation in package

The junction-to-ambient thermal resistance is an industry standard value which provides a quick and easy
estimation of thermal performance. However, the answer is only an estimate; test cases have demonstrated
that errors of a factor of two (in the quantity T

) are possible.

7.2

Estimation with Junction-to-Case Thermal Resistance

Historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal
resistance and a case-to-ambient thermal resistance:

= R

+ R

where:

= junction-to-ambient thermal resistance (ºC/W)

= junction-to-case thermal resistance (ºC/W)

= case-to-ambient thermal resistance (ºC/W)

A(0:31), TSIZ0/REG, TSIZ1, D(0:31), DP(0:3)/IRQ(3:6), RD/WR, BURST, RSV/IRQ2, IP_B(0:1)/IWP(0:1)/
VFLS(0:1), IP_B2/IOIS16_B/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/VF1, IP_B6/DSDI/AT0,
IP_B7/PTR/AT3, RXD1 /PA15, RXD2/PA13, L1TXDB/PA11, L1RXDB/PA10, L1TXDA/PA9, L1RXDA/PA8,
TIN1/L1RCLKA/BRGO1/CLK1/PA7, BRGCLK1/TOUT1/CLK2/PA6, TIN2/L1TCLKA/BRGO2/CLK3/PA5,
TOUT2/CLK4/PA4, TIN3/BRGO3/CLK5/PA3, BRGCLK2/L1RCLKB/TOUT3/CLK6/PA2, TIN4/BRGO4/CLK7/
PA1, L1TCLKB/TOUT4/CLK8/PA0, REJCT1/SPISEL/PB31, SPICLK/PB30, SPIMOSI/PB29, BRGO4/SPIMISO/
PB28, BRGO1/I2CSDA/PB27, BRGO2/I2CSCL/PB26, SMTXD1/PB25, SMRXD1/PB24, SMSYN1/SDACK1/
PB23, SMSYN2/SDACK2/PB22, SMTXD2/L1CLKOB/PB21, SMRXD2/L1CLKOA/PB20, L1ST1/RTS1/PB19,
L1ST2/RTS2/PB18, L1ST3/L1RQB/PB17, L1ST4/L1RQA/PB16, BRGO3/PB15, RSTRT1/PB14, L1ST1/RTS1/
DREQ0/PC15, L1ST2/RTS2/DREQ1/PC14, L1ST3/L1RQB/PC13, L1ST4/L1RQA/PC12, CTS1/PC11,
TGATE1/CD1/PC10, CTS2/PC9, TGATE2/CD2/PC8, SDACK2/L1TSYNCB/PC7, L1RSYNCB/PC6, SDACK1/
L1TSYNCA/PC5, L1RSYNCA/PC4, PD15, PD14, PD13, PD12, PD11, PD10, PD9, PD8, PD5, PD6, PD7, PD4, PD3,
MII_MDC, MII_TX_ER, MII_EN, MII_MDIO, MII_TXD[0:3].

BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:5), CS(6)/CE(1)_B, CS(7)/CE(2)_B, WE0/BS_B0/IORD,
WE1/BS_B1/IOWR, WE2/BS_B2/PCOE, WE3/BS_B3/PCWE, BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/
GPL_B1, GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A, CE1_A,
CE2_A, ALE_B/DSCK/AT1, OP(0:1), OP2/MODCK1/STS, OP3/MODCK2/DSDO, BADDR(28:30).

MOTOROLA

MPC860 Family Hardware Specifications

Thermal Calculation and Measurement

is device related and cannot be influenced by the user. The user adjusts the thermal environment to

affect the case-to-ambient thermal resistance, R

. For instance, the user can change the air flow around

the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the
thermal dissipation on the printed circuit board surrounding the device. This thermal model is most useful
for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink
to the ambient environment. For most packages, a better model is required.

7.3

Estimation with Junction-to-Board Thermal Resistance

A simple package thermal model which has demonstrated reasonable accuracy (about 20%) is a two resistor
model consisting of a junction-to-board and a junction-to-case thermal resistance. The junction-to-case
covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the
top of the package. The junction-to-board thermal resistance describes the thermal performance when most
of the heat is conducted to the printed circuit board. It has been observed that the thermal performance of
most plastic packages and especially PBGA packages is strongly dependent on the board temperature; see
Figure 1.

Figure 1. Effect of Board Temperature Rise on Thermal Behavior

If the board temperature is known, an estimate of the junction temperature in the environment can be made
using the following equation:

= T

+ (R

× P

)

where:

= junction-to-board thermal resistance (ºC/W)

= board temperature (ºC)

= power dissipation in package

If the board temperature is known and the heat loss from the package case to the air can be ignored,
acceptable predictions of junction temperature can be made. For this method to work, the board and board
mounting must be similar to the test board used to determine the junction-to-board thermal resistance,
namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground
plane.

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0

1 0 0

2 0

4 0

6 0

8 0

Board Temperture Rise Above Ambient Divided by Package

Junction Temperature Rise Above

Ambient Divided by Package Power

Board Temperature Rise Above Ambient Divided by Package Power

unction

emper

ature Rise Abo

Ambient Divided b

kage P

MPC860 Family Hardware Specifications

MOTOROLA

Layout Practices

7.4

Estimation Using Simulation

When the board temperature is not known, a thermal simulation of the application is needed. The simple
two resistor model can be used with the thermal simulation of the application [2], or a more accurate and
complex model of the package can be used in the thermal simulation.

7.5

Experimental Determination

To determine the junction temperature of the device in the application after prototypes are available, the
thermal characterization parameter (

) can be used to determine the junction temperature with a

measurement of the temperature at the top center of the package case using the following equation:

= T

+ (

× P

)

where:

= thermal characterization parameter

= thermocouple temperature on top of package

= power dissipation in package

The thermal characterization parameter is measured per JEDEC JESD51-2 specification using a 40 gauge
type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned
so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is
placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.

7.6

References

Semiconductor Equipment and Materials International

(415) 964-5111

805 East Middlefield Rd.
Mountain View, CA 94043

MIL-SPEC and EIA/JESD (JEDEC) specifications

800-854-7179 or

(Available from Global Engineering Documents)

303-397-7956

JEDEC Specifications

http://www.jedec.org

1. 1. C.E. Triplett and B. Joiner, "An Experimental Characterization of a 272 PBGA Within an

Automotive Engine Controller Module," Proceedings of SemiTherm, San Diego, 1998, pp. 4754.

2. 2. B. Joiner and V. Adams, "Measurement and Simulation of Junction to Board Thermal

Resistance and Its Application in Thermal Modeling," Proceedings of SemiTherm, San Diego,
1999, pp. 212220.

Layout Practices

Each V

pin on the MPC860 should be provided with a low-impedance path to the board's supply. Each

GND pin should likewise be provided with a low-impedance path to ground. The power supply pins drive
distinct groups of logic on chip. The V

power supply should be bypassed to ground using at least four 0.1

µF-bypass capacitors located as close as possible to the four sides of the package. The capacitor leads and
associated printed circuit traces connecting to chip V

and GND should be kept to less than half an inch

per capacitor lead. A four-layer board is recommended, employing two inner layers as V

and GND planes.

MOTOROLA

MPC860 Family Hardware Specifications

Bus Signal Timing

All output pins on the MPC860 have fast rise and fall times. Printed circuit (PC) trace interconnection length
should be minimized in order to minimize undershoot and reflections caused by these fast output switching
times. This recommendation particularly applies to the address and data busses. Maximum PC trace lengths
of 6 inches are recommended. Capacitance calculations should consider all device loads as well as parasitic
capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical
in systems with higher capacitive loads because these loads create higher transient currents in the V

and

GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be
taken to minimize the noise levels on the PLL supply pins.

Bus Signal Timing

Table 6 provides the bus operation timing for the MPC860 at 33, 40, 50, and 66 MHz.

The maximum bus speed supported by the MPC860 is 66 MHz. Higher-speed parts must be operated in
half-speed bus mode (for example, an MPC860 used at 80 MHz must be configured for a 40 MHz bus).

The timing for the MPC860 bus shown assumes a 50-pF load for maximum delays and a 0-pF load for
minimum delays.

Table 6. Bus Operation Timings

Num

Characteristic

33 MHz

40 MHz

50 MHz

66 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

CLKOUT period

30.30

25.00

30.30

20.00

30.30

15.15

30.30

B1a

EXTCLK to CLKOUT phase skew
(EXTCLK > 15 MHz and MF <= 2)

0.90

B1b

EXTCLK to CLKOUT phase skew
(EXTCLK > 10 MHz and MF < 10)

2.30

B1c

CLKOUT phase jitter (EXTCLK >
15 MHz and MF <= 2)

0.60

B1d

CLKOUT phase jitter

2.00

B1e

CLKOUT frequency jitter (MF < 10)

0.50

B1f

CLKOUT frequency jitter (10 < MF
< 500)

2.00

B1g

CLKOUT frequency jitter (MF > 500)

3.00

B1h

Frequency jitter on EXTCLK

0.50

CLKOUT pulse width low

12.12

10.00

8.00

6.06

CLKOUT width high

12.12

10.00

8.00

6.06

CLKOUT rise time

4.00

CLKOUT fall time

4.00

CLKOUT to A(0:31), BADDR(28:30),
RD/WR, BURST, D(0:31), DP(0:3)
invalid

7.58

6.25

5.00

3.80

MPC860 Family Hardware Specifications

MOTOROLA

Bus Signal Timing

B7a

CLKOUT to TSIZ(0:1), REG, RSV,
AT(0:3), BDIP, PTR invalid

7.58

6.25

5.00

3.80

B7b

CLKOUT to BR, BG, FRZ,
VFLS(0:1), VF(0:2) IWP(0:2),
LWP(0:1), STS invalid

7.58

6.25

5.00

3.80

CLKOUT to A(0:31), BADDR(28:30)
RD/WR, BURST, D(0:31), DP(0:3)
valid

7.58

14.33

6.25

13.00

5.00

11.75

3.80

10.04

B8a

CLKOUT to TSIZ(0:1), REG, RSV,
AT(0:3) BDIP, PTR valid

7.58

14.33

6.25

13.00

5.00

11.75

3.80

10.04

B8b

CLKOUT to BR, BG, VFLS(0:1),
VF(0:2), IWP(0:2), FRZ, LWP(0:1),
STS valid

7.58

14.33

6.25

13.00

5.00

11.75

3.80

10.04

CLKOUT to A(0:31), BADDR(28:30),
RD/WR, BURST, D(0:31), DP(0:3),
TSIZ(0:1), REG, RSV, AT(0:3), PTR
High-Z

7.58

14.33

6.25

13.00

5.00

11.75

3.80

10.04

B11

CLKOUT to TS, BB assertion

7.58

13.58

6.25

12.25

5.00

11.00

3.80

11.29

B11a

CLKOUT to TA, BI assertion (when
driven by the memory controller or
PCMCIA interface)

2.50

9.25

2.50

9.25

2.50

9.25

2.50

9.75

B12

CLKOUT to TS, BB negation

7.58

14.33

6.25

13.00

5.00

11.75

3.80

8.54

B12a

CLKOUT to TA, BI negation (when
driven by the memory controller or
PCMCIA interface)

2.50

11.00

2.50

11.00

2.50

11.00

2.50

9.00

B13

CLKOUT to TS, BB High-Z

7.58

21.58

6.25

20.25

5.00

19.00

3.80

14.04

B13a

CLKOUT to TA, BI High-Z (when
driven by the memory controller or
PCMCIA interface)

2.50

15.00

2.50

15.00

2.50

15.00

2.50

15.00

B14

CLKOUT to TEA assertion

2.50

10.00

2.50

10.00

2.50

10.00

2.50

9.00

B15

CLKOUT to TEA High-Z

2.50

15.00

2.50

15.00

2.50

15.00

2.50

15.00

B16

TA, BI valid to CLKOUT (setup time)

9.75

6.00

B16a

TEA, KR, RETRY, CR valid to
CLKOUT (setup time)

10.00

4.50

B16b

BB, BG, BR, valid to CLKOUT (setup
time)

8.50

4.00

B17

CLKOUT to TA, TEA, BI, BB, BG, BR
valid (hold time)

1.00

2.00

B17a

CLKOUT to KR, RETRY, CR valid
(hold time)

2.00

Table 6. Bus Operation Timings (continued)

Num

Characteristic

33 MHz

40 MHz

50 MHz

66 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

MOTOROLA

MPC860 Family Hardware Specifications

Bus Signal Timing

B18

D(0:31), DP(0:3) valid to CLKOUT
rising edge (setup time)

6.00

B19

CLKOUT rising edge to D(0:31),
DP(0:3) valid (hold time)

1.00

2.00

B20

D(0:31), DP(0:3) valid to CLKOUT
falling edge (setup time)

4.00

B21

CLKOUT falling edge to D(0:31),
DP(0:3) valid (hold time)

2.00

B22

CLKOUT rising edge to CS asserted
GPCM ACS = 00

7.58

14.33

6.25

13.00

5.00

11.75

3.80

10.04

B22a

CLKOUT falling edge to CS asserted
GPCM ACS = 10, TRLX = 0

8.00

B22b

CLKOUT falling edge to CS asserted
GPCM ACS = 11, TRLX = 0,
EBDF = 0

7.58

14.33

6.25

13.00

5.00

11.75

3.80

10.54

B22c

CLKOUT falling edge to CS asserted
GPCM ACS = 11, TRLX = 0,
EBDF = 1

10.86

17.99

8.88

16.00

7.00

14.13

5.18

12.31

B23

CLKOUT rising edge to CS negated
GPCM read access, GPCM write
access ACS = 00, TRLX = 0, and
CSNT = 0

2.00

8.00

2.00

8.00

2.00

8.00

2.00

8.00

B24

A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 10, TRLX = 0

5.58

4.25

3.00

1.79

B24a

A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 11, TRLX = 0

13.15

10.50

8.00

5.58

B25

CLKOUT rising edge to OE, WE(0:3)
asserted

9.00

B26

CLKOUT rising edge to OE negated

2.00

9.00

2.00

9.00

2.00

9.00

2.00

9.00

B27

A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 10, TRLX = 1

35.88

29.25

23.00

16.94

B27a

A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 11, TRLX = 1

43.45

35.50

28.00

20.73

B28

CLKOUT rising edge to WE(0:3)
negated GPCM write access
CSNT = 0

9.00

B28a

CLKOUT falling edge to WE(0:3)
negated GPCM write access
TRLX = 0, 1, CSNT = 1, EBDF = 0

7.58

14.33

6.25

13.00

5.00

11.75

3.80

10.54

Table 6. Bus Operation Timings (continued)

Num

Characteristic

33 MHz

40 MHz

50 MHz

66 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

MPC860 Family Hardware Specifications

MOTOROLA

Bus Signal Timing

B28b

CLKOUT falling edge to CS negated
GPCM write access TRLX = 0, 1,
CSNT = 1, ACS = 10, or ACS = 11,
EBDF = 0

14.33

13.00

11.75

10.54

B28c

CLKOUT falling edge to WE(0:3)
negated GPCM write access
TRLX = 0, 1, CSNT = 1 write access
TRLX = 0, CSNT = 1, EBDF = 1

10.86

17.99

8.88

16.00

7.00

14.13

5.18

12.31

B28d

CLKOUT falling edge to CS negated
GPCM write access TRLX = 0, 1,
CSNT = 1, ACS = 10, or ACS = 11,
EBDF = 1

17.99

16.00

14.13

12.31

B29

WE(0:3) negated to D(0:31), DP(0:3)
High-Z GPCM write access
CSNT = 0, EBDF = 0

5.58

4.25

3.00

1.79

B29a

WE(0:3) negated to D(0:31), DP(0:3)
High-Z GPCM write access,
TRLX = 0, CSNT = 1, EBDF = 0

13.15

10.5

8.00

5.58

B29b

CS negated to D(0:31), DP(0:3),
High-Z GPCM write access,
ACS = 00, TRLX = 0, 1, and CSNT =
0

5.58

4.25

3.00

1.79

B29c CS negated to D(0:31), DP(0:3)

High-Z GPCM write access,
TRLX = 0, CSNT = 1, ACS = 10, or
ACS = 11, EBDF = 0

13.15

10.5

8.00

5.58

B29d

WE(0:3) negated to D(0:31), DP(0:3)
High-Z GPCM write access,
TRLX = 1, CSNT = 1, EBDF = 0

43.45

35.5

28.00

20.73

B29e

CS negated to D(0:31), DP(0:3)
High-Z GPCM write access,
TRLX = 1, CSNT = 1, ACS = 10, or
ACS = 11, EBDF = 0

43.45

35.5

28.00

29.73

B29f

WE(0:3) negated to D(0:31), DP(0:3)
High-Z GPCM write access,
TRLX = 0, CSNT = 1, EBDF = 1

8.86

6.88

5.00

3.18

B29g

CS negated to D(0:31), DP(0:3)
High-Z GPCM write access,
TRLX = 0, CSNT = 1, ACS = 10, or
ACS = 11, EBDF = 1

8.86

6.88

5.00

3.18

B29h

WE(0:3) negated to D(0:31), DP(0:3)
High-Z GPCM write access,
TRLX = 1, CSNT = 1, EBDF = 1

38.67

31.38

24.50

17.83

Table 6. Bus Operation Timings (continued)

Num

Characteristic

33 MHz

40 MHz

50 MHz

66 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

MOTOROLA

MPC860 Family Hardware Specifications

Bus Signal Timing

B29i

CS negated to D(0:31), DP(0:3)
High-Z GPCM write access,
TRLX = 1, CSNT = 1, ACS = 10, or
ACS = 11, EBDF = 1

38.67

31.38

24.50

17.83

B30

CS, WE(0:3) negated to A(0:31),
BADDR(28:30) invalid GPCM write
access

5.58

4.25

3.00

1.79

B30a

WE(0:3) negated to A(0:31),
BADDR(28:30) invalid GPCM, write
access, TRLX = 0, CSNT = 1,
CS negated to A(0:31) invalid GPCM
write access, TRLX = 0, CSNT =1
ACS = 10, or ACS = 11, EBDF = 0

13.15

10.50

8.00

5.58

B30b

WE(0:3) negated to A(0:31),
invalid GPCM BADDR(28:30) invalid
GPCM write access, TRLX = 1,
CSNT = 1. CS negated to A(0:31),
Invalid GPCM, write access,
TRLX = 1, CSNT = 1, ACS = 10, or
ACS = 11, EBDF = 0

43.45

35.50

28.00

20.73

B30c

WE(0:3) negated to A(0:31),
BADDR(28:30) invalid GPCM write
access, TRLX = 0, CSNT = 1.
CS negated to A(0:31) invalid GPCM
write access, TRLX = 0, CSNT = 1,
ACS = 10, ACS = 11, EBDF = 1

8.36

6.38

4.50

2.68

B30d

WE(0:3) negated to A(0:31),
BADDR(28:30) invalid GPCM write
access, TRLX = 1, CSNT =1.
CS negated to A(0:31) invalid GPCM
write access TRLX = 1, CSNT = 1,
ACS = 10, or ACS = 11, EBDF = 1

38.67

31.38

24.50

17.83

B31

CLKOUT falling edge to CS
valid--as requested by control bit
CST4 in the corresponding word in
UPM

1.50

6.00

1.50

6.00

1.50

6.00

1.50

6.00

B31a

CLKOUT falling edge to CS
valid--as requested by control bit
CST1 in the corresponding word in
UPM

7.58

14.33

6.25

13.00

5.00

11.75

3.80

10.54

B31b

CLKOUT rising edge to CS valid--as
requested by control bit CST2 in the
corresponding word in UPM

1.50

8.00

1.50

8.00

1.50

8.00

1.50

8.00

B31c

CLKOUT rising edge to CS valid--as
requested by control bit CST3 in the
corresponding word in UPM

7.58

14.33

6.25

13.00

5.00

11.75

3.80

10.04

Table 6. Bus Operation Timings (continued)

Num

Characteristic

33 MHz

40 MHz

50 MHz

66 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

MPC860 Family Hardware Specifications

MOTOROLA

Bus Signal Timing

B31d

CLKOUT falling edge to CS
valid--as requested by control bit
CST1 in the corresponding word in
UPM, EBDF = 1

13.26

17.99

11.28

16.00

9.40

14.13

7.58

12.31

B32

CLKOUT falling edge to BS valid--as
requested by control bit BST4 in the
corresponding word in UPM

1.50

6.00

1.50

6.00

1.50

6.00

1.50

6.00

B32a

CLKOUT falling edge to BS valid--as
requested by control bit BST1 in the
corresponding word in UPM, EBDF =
0

7.58

14.33

6.25

13.00

5.00

11.75

3.80

10.54

B32b

CLKOUT rising edge to BS valid--as
requested by control bit BST2 in the
corresponding word in UPM

1.50

8.00

1.50

8.00

1.50

8.00

1.50

8.00

B32c

CLKOUT rising edge to BS valid--as
requested by control bit BST3 in the
corresponding word in UPM

7.58

14.33

6.25

13.00

5.00

11.75

3.80

10.54

B32d

CLKOUT falling edge to BS valid--as
requested by control bit BST1 in the
corresponding word in UPM, EBDF =
1

13.26

17.99

11.28

16.00

9.40

14.13

7.58

12.31

B33

CLKOUT falling edge to GPL
valid--as requested by control bit
GxT4 in the corresponding word in
UPM

1.50

6.00

1.50

6.00

1.50

6.00

1.50

6.00

B33a

CLKOUT rising edge to GPL
valid--as requested by control bit
GxT3 in the corresponding word in
UPM

7.58

14.33

6.25

13.00

5.00

11.75

3.80

10.54

B34

A(0:31), BADDR(28:30), and D(0:31)
to CS valid--as requested by control
bit CST4 in the corresponding word
in UPM

5.58

4.25

3.00

1.79

B34a

A(0:31), BADDR(28:30), and D(0:31)
to CS valid--as requested by control
bit CST1 in the corresponding word
in UPM

13.15

10.50

8.00

5.58

B34b

A(0:31), BADDR(28:30), and D(0:31)
to CS valid--as requested by control
bit CST2 in the corresponding word
in UPM

20.73

16.75

13.00

9.36

B35

A(0:31), BADDR(28:30) to CS
valid--as requested by control bit
BST4 in the corresponding word in
UPM

5.58

4.25

3.00

1.79

Table 6. Bus Operation Timings (continued)

Num

Characteristic

33 MHz

40 MHz

50 MHz

66 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

MOTOROLA

MPC860 Family Hardware Specifications

Bus Signal Timing

B35a

A(0:31), BADDR(28:30), and D(0:31)
to BS valid--as requested by control
bit BST1 in the corresponding word
in UPM

13.15

10.50

8.00

5.58

B35b

A(0:31), BADDR(28:30), and D(0:31)
to BS valid--as requested by control
bit BST2 in the corresponding word
in UPM

20.73

16.75

13.00

9.36

B36

A(0:31), BADDR(28:30), and D(0:31)
to GPL valid--as requested by
control bit GxT4 in the corresponding
word in UPM

5.58

4.25

3.00

1.79

B37

UPWAIT valid to CLKOUT falling
edge

6.00

B38

CLKOUT falling edge to UPWAIT
valid

1.00

B39

AS valid to CLKOUT rising edge

7.00

B40

A(0:31), TSIZ(0:1), RD/WR, BURST,
valid to CLKOUT rising edge

7.00

B41

TS valid to CLKOUT rising edge
(setup time)

7.00

B42

CLKOUT rising edge to TS valid
(hold time)

2.00

B43

AS negation to memory controller
signals negation

TBD

Phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed value.

If the rate of change of the frequency of EXTAL is slow (i.e., it does not jump between the minimum and maximum
values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long time) then
the maximum allowed jitter on EXTAL can be up to 2%.

The timings specified in B4 and B5 are based on full strength clock.

The timing for BR output is relevant when the MPC860 is selected to work with external bus arbiter. The timing for BG
output is relevant when the MPC860 is selected to work with internal bus arbiter.

The timing required for BR input is relevant when the MPC860 is selected to work with internal bus arbiter. The timing
for BG input is relevant when the MPC860 is selected to work with external bus arbiter.

The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input
signal is asserted.

The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only
for read accesses controlled by chip-selects under control of the UPM in the memory controller, for data beats where
DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)

The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.

The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified
in B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 17.

The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior
specified in Figure 20.

Table 6. Bus Operation Timings (continued)

Num

Characteristic

33 MHz

40 MHz

50 MHz

66 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

MOTOROLA

MPC860 Family Hardware Specifications

Bus Signal Timing

Figure 8 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the
UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)

Figure 8. Input Data Timing when Controlled by UPM in the Memory Controller

and DLT3 = 1

Figure 9 through Figure 12 provide the timing for the external bus read controlled by various GPCM factors.

Figure 9. External Bus Read Timing (GPCM Controlled--ACS = 00)

CLKOUT

D[0:31],

DP[0:3]

B20

B21

CLKOUT

A[0:31]

CSx

WE[0:3]

D[0:31],

DP[0:3]

B11

B12

B23

B22

B26

B19

B18

B25

B28

MOTOROLA

MPC860 Family Hardware Specifications

Bus Signal Timing

Figure 19 provides the timing for the synchronous external master access controlled by the GPCM.

Figure 19. Synchronous External Master Access Timing (GPCM Handled ACS = 00)

Figure 20 provides the timing for the asynchronous external master memory access controlled by the
GPCM.

Figure 20. Asynchronous External Master Memory Access Timing

(GPCM Controlled--ACS = 00)

Figure 21 provides the timing for the asynchronous external master control signals negation.

Figure 21. Asynchronous External Master--Control Signals Negation Timing

CLKOUT

A[0:31],

TSIZ[0:1],

R/W, BURST

CSx

B41

B42

B40

B22

CLKOUT

A[0:31],

TSIZ[0:1],

R/W

CSx

B39

B40

B22

CSx, WE[0:3],

OE, GPLx,

BS[0:3]

B43

MPC860 Family Hardware Specifications

MOTOROLA

Bus Signal Timing

Table 7 provides interrupt timing for the MPC860.

Figure 22 provides the interrupt detection timing for the external level-sensitive lines.

Figure 22. Interrupt Detection Timing for External Level Sensitive Lines

Figure 23 provides the interrupt detection timing for the external edge-sensitive lines.

Figure 23. Interrupt Detection Timing for External Edge Sensitive Lines

Table 7. Interrupt Timing

Num

Characteristic

The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as
level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference
to the CLKOUT.
The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and has
no direct relation with the total system interrupt latency that the MPC860 is able to support.

All Frequencies

Unit

Min

Max

I39

IRQx valid to CLKOUT rising edge (setup time)

6.00

I40

IRQx hold time after CLKOUT

2.00

I41

IRQx pulse width low

3.00

I42

IRQx pulse width high

3.00

I43

IRQx edge-to-edge time

× T

CLOCKOUT

CLKOUT

IRQx

I39

I40

CLKOUT

IRQx

I41

I42

I43

MOTOROLA

MPC860 Family Hardware Specifications

Bus Signal Timing

Table 8 shows the PCMCIA timing for the MPC860.

Table 8. PCMCIA Timing

Num

Characteristic

33 MHz

40 MHz

50 MHz

66 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

P44

A(0:31), REG valid to PCMCIA
Strobe asserted

PSST = 1. Otherwise add PSST times cycle time.
PSHT = 0. Otherwise add PSHT times cycle time.

These synchronous timings define when the WAITx signals are detected in order to freeze (or relieve) the
PCMCIA current cycle. The WAITx assertion will be effective only if it is detected 2 cycles before the PSL
timer expiration. See PCMCIA Interface in the MPC860 PowerQUICC User s Manual.

20.73

16.75

13.00

9.36

P45

A(0:31), REG valid to ALE negation

28.30

23.00

18.00

13.15

P46

CLKOUT to REG valid

7.58

15.58

6.25

14.25

5.00

13.00

3.79

11.84

P47

CLKOUT to REG invalid

8.58

7.25

6.00

4.84

P48

CLKOUT to CE1, CE2 asserted

7.58

15.58

6.25

14.25

5.00

13.00

3.79

11.84

P49

CLKOUT to CE1, CE2 negated

7.58

15.58

6.25

14.25

5.00

13.00

3.79

11.84

P50

CLKOUT to PCOE, IORD, PCWE,
IOWR assert time

11.00

P51

CLKOUT to PCOE, IORD, PCWE,
IOWR negate time

2.00

11.00

2.00

11.00

2.00

11.00

2.00

11.00

P52

CLKOUT to ALE assert time

7.58

15.58

6.25

14.25

5.00

13.00

3.79

10.04

P53

CLKOUT to ALE negate time

15.58

14.25

13.00

11.84

P54

PCWE, IOWR negated to D(0:31)
invalid

5.58

4.25

3.00

1.79

P55

WAITA and WAITB valid to CLKOUT
rising edge

8.00

P56

CLKOUT rising edge to WAITA and
WAITB invalid

2.00

MPC860 Family Hardware Specifications

MOTOROLA

Bus Signal Timing

Table 9 shows the PCMCIA port timing for the MPC860.

Figure 27 provides the PCMCIA output port timing for the MPC860.

Figure 27. PCMCIA Output Port Timing

Figure 28 provides the PCMCIA output port timing for the MPC860.

Figure 28. PCMCIA Input Port Timing

Table 9. PCMCIA Port Timing

Num

Characteristic

33 MHz

40 MHz

50 MHz

66 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

P57

CLKOUT to OPx valid

19.00

P58

HRESET negated to OPx drive

OP2 and OP3 only.

25.73

21.75

18.00

14.36

P59

IP_Xx valid to CLKOUT rising edge

5.00

P60

CLKOUT rising edge to IP_Xx
invalid

1.00

CLKOUT

HRESET

Output

Signals

OP2, OP3

P57

P58

CLKOUT

Input

Signals

P59

P60

MOTOROLA

MPC860 Family Hardware Specifications

Bus Signal Timing

Table 10 shows the debug port timing for the MPC860.

Figure 29 provides the input timing for the debug port clock.

Figure 29. Debug Port Clock Input Timing

Figure 30 provides the timing for the debug port.

Figure 30. Debug Port Timings

Table 10. Debug Port Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

P61

DSCK cycle time

× T

CLOCKOUT

P62

DSCK clock pulse width

1.25

× T

CLOCKOUT

P63

DSCK rise and fall times

0.00

3.00

P64

DSDI input data setup time

8.00

P65

DSDI data hold time

5.00

P66

DSCK low to DSDO data valid

0.00

15.00

P67

DSCK low to DSDO invalid

0.00

2.00

DSCK

D61

D63

D62

D63

DSCK

DSDI

DSDO

D64

D65

D66

D67

MPC860 Family Hardware Specifications

MOTOROLA

Bus Signal Timing

Table 11 shows the reset timing for the MPC860.

Table 11. Reset Timing

Num

Characteristic

33 MHz

40 MHz

50 MHz

66 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

R69

CLKOUT to HRESET high
impedance

20.00

R70

CLKOUT to SRESET high
impedance

20.00

R71

RSTCONF pulse width

515.1

425.0

340.0

257.5

R72

R73

Configuration data to HRESET rising
edge setup time

504.5

425.0

350.0

277.2

R74

Configuration data to RSTCONF
rising edge setup time

350.0

R75

Configuration data hold time after
RSTCONF negation

0.00

R76

Configuration data hold time after
HRESET negation

0.00

R77

HRESET and RSTCONF asserted to
data out drive

25.00

R78

RSTCONF negated to data out high
impedance

25.00

R79

CLKOUT of last rising edge before
chip three-state HRESET to data out
high impedance

25.00

R80

DSDI, DSCK setup

90.91

75.00

60.00

45.45

R81

DSDI, DSCK hold time

0.00

R82

SRESET negated to CLKOUT rising
edge for DSDI and DSCK sample

242.4

200.0

160.0

121.2

MPC860 Family Hardware Specifications

MOTOROLA

IEEE 1149.1 Electrical Specifications

Figure 33 provides the reset timing for the debug port configuration.

Figure 33. Reset Timing--Debug Port Configuration

IEEE 1149.1 Electrical Specifications

Table 12 provides the JTAG timings for the MPC860 shown in Figure 34 through Figure 37.

Table 12. JTAG Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

J82

TCK cycle time

100.00

J83

TCK clock pulse width measured at 1.5 V

40.00

J84

TCK rise and fall times

0.00

10.00

J85

TMS, TDI data setup time

5.00

J86

TMS, TDI data hold time

25.00

J87

TCK low to TDO data valid

27.00

J88

TCK low to TDO data invalid

0.00

J89

TCK low to TDO high impedance

20.00

J90

TRST assert time

100.00

J91

TRST setup time to TCK low

40.00

J92

TCK falling edge to output valid

50.00

J93

TCK falling edge to output valid out of high impedance

50.00

J94

TCK falling edge to output high impedance

50.00

J95

Boundary scan input valid to TCK rising edge

50.00

J96

TCK rising edge to boundary scan input invalid

50.00

CLKOUT

SRESET

DSCK, DSDI

R70

R82

R80

R81

MPC860 Family Hardware Specifications

MOTOROLA

CPM Electrical Characteristics

This section provides the AC and DC electrical specifications for the communications processor module
(CPM) of the MPC860.

11.1

PIP/PIO AC Electrical Specifications

Table 13 provides the PIP/PIO AC timings as shown in Figure 38 through Figure 42.

Figure 38. PIP Rx (Interlock Mode) Timing Diagram

Table 13. PIP/PIO Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

Data-in setup time to STBI low

Data-In hold time to STBI high

2.5 t3

t3 = Specification 23.

CLK

STBI pulse width

1.5

CLK

STBO pulse width

1 CLK 5 ns

Data-out setup time to STBO low

CLK

Data-out hold time from STBO high

CLK

STBI low to STBO low (Rx interlock)

CLK

STBI low to STBO high (Tx interlock)

CLK

Data-in setup time to clock high

Data-in hold time from clock high

7.5

Clock low to data-out valid (CPU writes data, control, or direction)

DATA-IN

STBI

STBO

MPC860 Family Hardware Specifications

MOTOROLA

CPM Electrical Characteristics

Figure 42. Parallel I/O Data-In/Data-Out Timing Diagram

11.2

IDMA Controller AC Electrical Specifications

Table 14 provides the IDMA controller timings as shown in Figure 43 through Figure 46.

Figure 43. IDMA External Requests Timing Diagram

Table 14. IDMA Controller Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

DREQ setup time to clock high

DREQ hold time from clock high

SDACK assertion delay from clock high

SDACK negation delay from clock low

SDACK negation delay from TA low

SDACK negation delay from clock high

TA assertion to falling edge of the clock setup time (applies to
external TA)

CLKO

DATA-IN

DATA-OUT

DREQ
(Input)

CLKO

(Output)

MPC860 Family Hardware Specifications

MOTOROLA

CPM Electrical Characteristics

Figure 46. SDACK Timing Diagram--Peripheral Read, Internally-Generated TA

11.3

Baud Rate Generator AC Electrical Specifications

Table 15 provides the baud rate generator timings as shown in Figure 47.

Figure 47. Baud Rate Generator Timing Diagram

Table 15. Baud Rate Generator Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

BRGO rise and fall time

BRGO duty cycle

BRGO cycle

DATA

CLKO

(Output)

R/W

(Output)

SDACK

BRGOX

MOTOROLA

MPC860 Family Hardware Specifications

CPM Electrical Characteristics

11.4

Timer AC Electrical Specifications

Table 16 provides the general-purpose timer timings as shown in Figure 48.

Figure 48. CPM General-Purpose Timers Timing Diagram

11.5

Serial Interface AC Electrical Specifications

Table 17 provides the serial interface timings as shown in Figure 49 through Figure 53.

Table 16. Timer Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

TIN/TGATE rise and fall time

TIN/TGATE low time

CLK

TIN/TGATE high time

CLK

TIN/TGATE cycle time

CLK

CLKO low to TOUT valid

Table 17. SI Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

L1RCLK, L1TCLK frequency (DSC = 0)

SYNCCLK/2.5

MHz

L1RCLK, L1TCLK width low (DSC = 0)

P + 10

71a

L1RCLK, L1TCLK width high (DSC = 0)

P + 10

L1TXD, L1ST(14), L1RQ, L1CLKO rise/fall time

15.00

L1RSYNC, L1TSYNC valid to L1CLK edge (SYNC setup time)

20.00

L1CLK edge to L1RSYNC, L1TSYNC, invalid (SYNC hold time)

35.00

L1RSYNC, L1TSYNC rise/fall time

15.00

CLKO

TIN/TGATE

(Input)

TOUT

(Output)

MPC860 Family Hardware Specifications

MOTOROLA

CPM Electrical Characteristics

L1RXD valid to L1CLK edge (L1RXD setup time)

17.00

L1CLK edge to L1RXD invalid (L1RXD hold time)

13.00

L1CLK edge to L1ST(14) valid

10.00

45.00

78A

L1SYNC valid to L1ST(14) valid

10.00

45.00

L1CLK edge to L1ST(14) invalid

10.00

45.00

L1CLK edge to L1TXD valid

10.00

55.00

80A

L1TSYNC valid to L1TXD valid

10.00

55.00

L1CLK edge to L1TXD high impedance

0.00

42.00

L1RCLK, L1TCLK frequency (DSC =1)

16.00 or

SYNCCLK/2

MHz

L1RCLK, L1TCLK width low (DSC =1)

P + 10

83a

L1RCLK, L1TCLK width high (DSC = 1)

P + 10

L1CLK edge to L1CLKO valid (DSC = 1)

30.00

L1RQ valid before falling edge of L1TSYNC

1.00

L1TCL

L1GR setup time

42.00

L1GR hold time

42.00

L1CLK edge to L1SYNC valid (FSD = 00) CNT = 0000, BYT = 0,
DSC = 0)

0.00

The ratio SYNCCLK/L1RCLK must be greater than 2.5/1.

These specs are valid for IDL mode only.

Where P = 1/CLKOUT. Thus, for a 25-MHz CLKO1 rate, P = 40 ns.

These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever is later.

Table 17. SI Timing (continued)

Num

Characteristic

All Frequencies

Unit

Min

Max

MPC860 Family Hardware Specifications

MOTOROLA

CPM Electrical Characteristics

11.6

SCC in NMSI Mode Electrical Specifications

Table 18 provides the NMSI external clock timing.

Table 19 provides the NMSI internal clock timing.

Table 18. NMSI External Clock Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

100

RCLK1 and TCLK1 width high

The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater than or equal to 2.25/1.

1/SYNCCLK

101

RCLK1 and TCLK1 width low

1/SYNCCLK + 5

102

RCLK1 and TCLK1 rise/fall time

15.00

103

TXD1 active delay (from TCLK1 falling edge)

0.00

50.00

104

RTS1 active/inactive delay (from TCLK1 falling edge)

0.00

50.00

105

CTS1 setup time to TCLK1 rising edge

5.00

106

RXD1 setup time to RCLK1 rising edge

5.00

107

RXD1 hold time from RCLK1 rising edge

Also applies to CD and CTS hold time when they are used as an external sync signal.

5.00

108 CD1 setup Time to RCLK1 rising edge

5.00

Table 19. NMSI Internal Clock Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

100

RCLK1 and TCLK1 frequency

The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater or equal to 3/1.

0.00

SYNCCLK/3

MHz

102

RCLK1 and TCLK1 rise/fall time

103

TXD1 active delay (from TCLK1 falling edge)

0.00

30.00

104

RTS1 active/inactive delay (from TCLK1 falling edge)

0.00

30.00

105

CTS1 setup time to TCLK1 rising edge

40.00

106

RXD1 setup time to RCLK1 rising edge

40.00

107

RXD1 hold time from RCLK1 rising edge

Also applies to CD and CTS hold time when they are used as an external sync signals.

0.00

108

CD1 setup time to RCLK1 rising edge

40.00

MPC860 Family Hardware Specifications

MOTOROLA

CPM Electrical Characteristics

Figure 56. HDLC Bus Timing Diagram

11.7

Ethernet Electrical Specifications

Table 20 provides the Ethernet timings as shown in Figure 57 through Figure 61.

Table 20. Ethernet Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

120

CLSN width high

121

RCLK1 rise/fall time

122

RCLK1 width low

123

RCLK1 clock period

120

124

RXD1 setup time

125

RXD1 hold time

126

RENA active delay (from RCLK1 rising edge of the last data bit)

127

RENA width low

100

128

TCLK1 rise/fall time

129

TCLK1 width low

130

TCLK1 clock period

101

131

TXD1 active delay (from TCLK1 rising edge)

132

TXD1 inactive delay (from TCLK1 rising edge)

133

TENA active delay (from TCLK1 rising edge)

134

TENA inactive delay (from TCLK1 rising edge)

TCLK1

CTS1

(Echo Input)

102

100

104

TxD1

(Output)

102

101

RTS1

(Output)

103

104

107

105

MOTOROLA

MPC860 Family Hardware Specifications

CPM Electrical Characteristics

Figure 57. Ethernet Collision Timing Diagram

Figure 58. Ethernet Receive Timing Diagram

135

RSTRT active delay (from TCLK1 falling edge)

136

RSTRT inactive delay (from TCLK1 falling edge)

137

REJECT width low

CLK

138

CLKO1 low to SDACK asserted

139

CLKO1 low to SDACK negated

The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater or equal to 2/1.

SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.

Table 20. Ethernet Timing (continued)

Num

Characteristic

All Frequencies

Unit

Min

Max

CLSN(CTS1)

120

(Input)

RCLK1

121

RxD1

(Input)

121

RENA(CD1)

(Input)

125

124

123

127

126

Last Bit

MPC860 Family Hardware Specifications

MOTOROLA

CPM Electrical Characteristics

Figure 59. Ethernet Transmit Timing Diagram

Figure 60. CAM Interface Receive Start Timing Diagram

Figure 61. CAM Interface REJECT Timing Diagram

TCLK1

128

TxD1

(Output)

128

TENA(RTS1)

(Input)

NOTES:

Transmit clock invert (TCI) bit in GSMR is set.
If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the
CSL bit is set in the buffer descriptor at the end of the frame transmission.

1.
2.

RENA(CD1)

(Input)

133

134

132

131

121

129

(NOTE 2)

RCLK1

RxD1

(Input)

RSTRT

(Output)

136

125

BIT1

BIT2

Start Frame

REJECT

137

MOTOROLA

MPC860 Family Hardware Specifications

CPM Electrical Characteristics

11.8

SMC Transparent AC Electrical Specifications

Table 21 provides the SMC transparent timings as shown in Figure 62.

Figure 62. SMC Transparent Timing Diagram

Table 21. SMC Transparent Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

150

SMCLK clock period

SYNCCLK must be at least twice as fast as SMCLK.

100

151

SMCLK width low

151A

SMCLK width high

152

SMCLK rise/fall time

153

SMTXD active delay (from SMCLK falling edge)

154

SMRXD/SMSYNC setup time

155

RXD1/SMSYNC hold time

SMCLK

SMRXD

(Input)

152

150

SMTXD

(Output)

152

151

SMSYNC

151

154

153

155

154

155

NOTE

NOTE:

This delay is equal to an integer number of character-length clocks.

MPC860 Family Hardware Specifications

MOTOROLA

CPM Electrical Characteristics

11.9

SPI Master AC Electrical Specifications

Table 22 provides the SPI master timings as shown in Figure 63 and Figure 64.

Figure 63. SPI Master (CP = 0) Timing Diagram

Table 22. SPI Master Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

160

MASTER cycle time

1024

cyc

161

MASTER clock (SCK) high or low time

512

cyc

162

MASTER data setup time (inputs)

163

Master data hold time (inputs)

164

Master data valid (after SCK edge)

165

Master data hold time (outputs)

166

Rise time output

167

Fall time output

SPIMOSI

(Output)

SPICLK

(CI=0)

(Output)

SPICLK

(CI=1)

(Output)

SPIMISO

(Input)

162

Data

166

167

161

160

msb

lsb

msb

Data

lsb

msb

167

166

163

166

167

165

164

MOTOROLA

MPC860 Family Hardware Specifications

CPM Electrical Characteristics

Figure 64. SPI Master (CP = 1) Timing Diagram

11.10 SPI Slave AC Electrical Specifications

Table 23 provides the SPI slave timings as shown in Figure 65 and Figure 66.

Table 23. SPI Slave Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

170

Slave cycle time

cyc

171

Slave enable lead time

172

Slave enable lag time

173

Slave clock (SPICLK) high or low time

cyc

174

Slave sequential transfer delay (does not require deselect)

cyc

175

Slave data setup time (inputs)

176

Slave data hold time (inputs)

177

Slave access time

SPIMOSI

(Output)

SPICLK

(CI=0)

(Output)

SPICLK

(CI=1)

(Output)

SPIMISO

(Input)

Data

166

167

161

160

msb

lsb

msb

Data

lsb

msb

167

166

163

166

167

165

164

162

MPC860 Family Hardware Specifications

MOTOROLA

CPM Electrical Characteristics

Figure 65. SPI Slave (CP = 0) Timing Diagram

Figure 66. SPI Slave (CP = 1) Timing Diagram

SPIMOSI

(Input)

SPICLK

(CI=0)

(Input)

SPICLK

(CI=1)

(Input)

SPIMISO

(Output)

180

Data

181

182

173

170

msb

lsb

msb

181

177

182

175

179

SPISEL

(Input)

171

172

174

Data

msb

lsb

msb

Undef

181

178

176

182

SPIMOSI

(Input)

SPICLK

(CI=0)

(Input)

SPICLK

(CI=1)

(Input)

SPIMISO

(Output)

180

Data

181

182

msb

lsb

181

177

182

175

179

SPISEL

(Input)

174

Data

msb

lsb

Undef

178

176

182

msb

172

173

171

170

181

MOTOROLA

MPC860 Family Hardware Specifications

CPM Electrical Characteristics

11.11 I

C AC Electrical Specifications

Table 24 provides the I

C (SCL < 100 kHz) timings.

Table 24. I

C Timing (SCL < 100 kH

)

Num

Characteristic

All Frequencies

Unit

Min

Max

200

SCL clock frequency (slave)

100

kHz

200

SCL clock frequency (master)

SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3

× pre_scaler × 2).

The ratio SYNCCLK/(BRGCLK / pre_scaler) must be greater or equal to 4/1.

1.5

100

kHz

202

Bus free time between transmissions

4.7

µs

203

Low period of SCL

4.7

µs

204

High period of SCL

4.0

µs

205

Start condition setup time

4.7

µs

206

Start condition hold time

4.0

µs

207

Data hold time

µs

208

Data setup time

250

209

SDL/SCL rise time

µs

210

SDL/SCL fall time

300

211

Stop condition setup time

4.7

µs

MPC860 Family Hardware Specifications

MOTOROLA

UTOPIA AC Electrical Specifications

Table 25 provides the I

C (SCL > 100 kHz) timings.

Figure 67 shows the I

C bus timing.

Figure 67. I

C Bus Timing Diagram

UTOPIA AC Electrical Specifications

Table 26 shows the AC electrical specifications for the UTOPIA interface.

Table 25. . I

C Timing (SCL > 100 kH

)

Num

Characteristic

Expression

All Frequencies

Unit

Min

Max

200

SCL clock frequency (slave)

fSCL

BRGCLK/48

200

SCL clock frequency (master)

SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3)

× pre_scaler × 2).

The ratio SYNCCLK/(BRGCLK / pre_scaler) must be greater or equal to 4/1.

fSCL

BRGCLK/16512

BRGCLK/48

202

Bus free time between transmissions

1/(2.2 * fSCL)

203

Low period of SCL

1/(2.2 * fSCL)

204

High period of SCL

1/(2.2 * fSCL)

205

Start condition setup time

1/(2.2 * fSCL)

206

Start condition hold time

1/(2.2 * fSCL)

207

Data hold time

208

Data setup time

1/(40 * fSCL)

209

SDL/SCL rise time

1/(10 * fSCL)

210

SDL/SCL fall time

1/(33 * fSCL)

211

Stop condition setup time

1/2(2.2 * fSCL)

Table 26. UTOPIA AC Electrical Specifications

Num

Signal Characteristic

Direction

Min

Max

Unit

UtpClk rise/fall time (Internal clock option)

Output

3.5

Duty cycle

Frequency

MHz

SCL

202

205

203

207

204

208

206

209

211

210

SDA

MOTOROLA

MPC860 Family Hardware Specifications

UTOPIA AC Electrical Specifications

Figure 68 shows signal timings during UTOPIA receive operations.

Figure 68. UTOPIA Receive Timing

U1a

UtpClk rise/fall time (external clock option)

Input

3.5

Duty cycle

Frequency

MHz

RxEnb and TxEnb active delay

Output

UTPB, SOC, Rxclav and Txclav setup time

Input

UTPB, SOC, Rxclav and Txclav hold time

Input

UTPB, SOC active delay (and PHREQ and PHSEL active delay
in MPHY mode)

Output

Table 26. UTOPIA AC Electrical Specifications (continued)

Num

Signal Characteristic

Direction

Min

Max

Unit

UtpClk

UTPB

RxEnb

SOC

RxClav

PHREQn

HighZ at MPHY

MPC860 Family Hardware Specifications

MOTOROLA

FEC Electrical Characteristics

Figure 69 shows signal timings during UTOPIA transmit operations.

Figure 69. UTOPIA Transmit Timing

FEC Electrical Characteristics

This section provides the AC electrical specifications for the Fast Ethernet controller (FEC). Note that the
timing specifications for the MII signals are independent of system clock frequency (part speed
designation). Also, MII signals use TTL signal levels compatible with devices operating at either 5.0 V or
3.3 V.

13.1

MII Receive Signal Timing (MII_RXD[3:0], MII_RX_DV,
MII_RX_ER, MII_RX_CLK)

The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed the
MII_RX_CLK frequency 1%.

Table 27 provides information on the MII receive signal timing.

Table 27. MII Receive Signal Timing

Num

Characteristic

Min

Max

Unit

MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup

MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold

MII_RX_CLK pulse width high

35%

65%

MII_RX_CL

K period

MII_RX_CLK pulse width low

35%

65%

MII_RX_CL

K period

UtpClk

UTPB

TxEnb

SOC

TxClav

PHSELn

HighZ at MPHY

MOTOROLA

MPC860 Family Hardware Specifications

FEC Electrical Characteristics

Figure 70 shows MII receive signal timing.

Figure 70. MII Receive Signal Timing Diagram

13.2

MII Transmit Signal Timing (MII_TXD[3:0], MII_TX_EN,
MII_TX_ER, MII_TX_CLK)

The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz +1%. There is
no minimum frequency requirement. In addition, the processor clock frequency must exceed the
MII_TX_CLK frequency 1%.

Table 28 provides information on the MII transmit signal timing.

Table 28. MII Transmit Signal Timing

Num

Characteristic

Min

Max

Unit

MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid

MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid

MII_TX_CLK pulse width high

65%

MII_TX_CLK

period

MII_TX_CLK pulse width low

35%

65%

MII_TX_CLK

period

MII_RX_CLK (Input)

MII_RXD[3:0] (Inputs)
MII_RX_DV
MII_RX_ER

MPC860 Family Hardware Specifications

MOTOROLA

FEC Electrical Characteristics

Figure 71 shows the MII transmit signal timing diagram.

Figure 71. MII Transmit Signal Timing Diagram

13.3

MII Async Inputs Signal Timing (MII_CRS, MII_COL)

Table 29 provides information on the MII async inputs signal timing.

Figure 72 shows the MII asynchronous inputs signal timing diagram.

Figure 72. MII Async Inputs Timing Diagram

Table 29. MII Async Inputs Signal Timing

Num

Characteristic

Min

Max

Unit

MII_CRS, MII_COL minimum pulse width

1.5

MII_TX_CLK

period

MII_TX_CLK (Input)

MII_TXD[3:0] (Outputs)
MII_TX_EN
MII_TX_ER

MII_CRS, MII_COL

MOTOROLA

MPC860 Family Hardware Specifications

FEC Electrical Characteristics

13.4

MII Serial Management Channel Timing (MII_MDIO,
MII_MDC)

Table 30 provides information on the MII serial management channel signal timing. The FEC functions
correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under
investigation.

Figure 73 shows the MII serial management channel timing diagram.

Figure 73. MII Serial Management Channel Timing Diagram

Table 30. MII Serial Management Channel Timing

Num

Characteristic

Min

Max

Unit

M10

MII_MDC falling edge to MII_MDIO output invalid (minimum
propagation delay)

M11

MII_MDC falling edge to MII_MDIO output valid (max prop delay)

M12

MII_MDIO (input) to MII_MDC rising edge setup

M13

MII_MDIO (input) to MII_MDC rising edge hold

M14

MII_MDC pulse width high

40%

60%

MII_MDC

period

M15

MII_MDC pulse width low

40%

60%

MII_MDC

period

M11

MII_MDC (Output)

MII_MDIO (Output)

M12

M13

MII_MDIO (Input)

M10

M14

MM15

MPC860 Family Hardware Specifications

MOTOROLA

Mechanical Data and Ordering Information

Table 31 provides information on the MPC860 revision D.3 and D.4 derivative devices.

Table 31. MPC860 Family Revision D.3 and D.4 Derivatives

Device

Number of

SCCs

Serial communications controller (SCC).

Ethernet Support

(Mbps)

Up to 4 channels at 40 MHz or 2 channels at 25 MHz.

Multi-Channel

HDLC Support

ATM

Support

MPC855T

10/100

yes

MPC860DE

N/A

MPC860DT

10/100

Yes

MPC860DP

10/100

Yes

MPC860EN

N/A

MPC860SR

Yes

MPC860T

10/100

Yes

MPC860P

10/100

Yes

MOTOROLA

MPC860 Family Hardware Specifications

Mechanical Data and Ordering Information

Table 32 identifies the packages and operating frequencies available for the MPC860.

Table 33 identifies the packages and operating frequencies available for the MPC860P.

Table 32. MPC860 Family Package/Frequency Availability

Package Type

Frequency

(MHz)

Temperature

(Tj)

Order Number

Ball grid array

(ZP suffix)

0° to 95°C

XPC860DEZP50nn

XPC860DTZP50nn
XPC860ENZP50nn
XPC860SRZP50nn
XPC860TZP50nn
XPC855TZP50D4

Where nn specifies version D.3 (as D3) or D.4 (as D4).

0° to 95°C

XPC860DEZP66nn
XPC860DTZP66nn
XPC860ENZP66nn
XPC860SRZP66nn
XPC860TZP66nn
XPC855TZP66D4

0° to 95°C

XPC860DEZP80nn
XPC860DTZP80nn
XPC860ENZP80nn
XPC860SRZP80nn
XPC860TZP80nn
XPC855TZP80D4

Ball grid array

(CZP suffix)

40° to 95°C

XPC860DECZP50nn
XPC860DTCZP50nn
XPC860ENCZP50nn
XPC860SRCZP50nn
XPC860TCZP50nn
XPC855TCZP50D4

40° to 95°C

XPC860DECZP66nn
XPC860DTCZP66nn
XPC860ENCZP66nn
XPC860SRCZP66nn
XPC860TCZP66nn
XPC855TCZP66D4

Table 33. MPC860P Package/Frequency Availability

Package Type

Frequency

(MHz)

Temperature

(Tj)

Order Number

Ball grid array

(ZP suffix)

0° to 95°C

XPC860DPZP50nn

XPC860PZP50nn

0° to 95°C

XPC860DPZP66nn
XPC860PZP66nn

0° to 95°C

XPC860DPZP80nn
XPC860PZP80nn

MOTOROLA

MPC860 Family Hardware Specifications

Mechanical Data and Ordering Information

14.1

Pin Assignments

Figure 74 shows the top view pinout of the PBGA package. For additional information, see the MPC860
PowerQUICC User's Manual, or the MPC855T User's Manual.

NOTE: This is the top view of the device.

Figure 74. Pinout of the PBGA Package

PD3

IRQ7

VDDL

D29

CLKOUT IPA3

DP2

A14

A27

A29

A30

A28

A31

VDDL BSA2

WE1

WE3

CE2A

CS1

CS4

A11

A13

A17

A21

A23

A22

TSIZ0 BSA3 M_CRS WE2 GPLA2

CE1A

CS5

A10

GPLB4

PA15

A12

A16

A20

A24

A26

TSIZ1 BSA1

WE0 GPLA1 GPLA3

CS0

CS7

PB31

GPLA4

PB30

PC14

PC15

N/C

A15

A19

A25

A18

BSA0 GPLA0

N/C

CS6

GPLA5 BDIP

CS2

PA14

TEA

PB28

PC13

PB29

VDDH

CS3

PA13

PB27

PC12

VDDL

GND

IRQ3

VDDL

PA12

BURST

PB26

TMS

PA11

IRQ6

IPB4

TDO

IPB3

TRST

M_MDIO

TCK

IRQ2

IPB0

M_COL

TDI

IPB7

VDDL

PB24

PB25

IPB1

IPB2

IPB5

PA10

ALEB

PC11

PA9

PB21

GND

IPB6 ALEA

BADDR30

PB23

IRQ4

PC10

PC9

PB20

OP1

OP0

PA8

MODCK1

PB22

PC8

PC7

BADDR28

BADDR29

MODCK2

PA6

VDDL

PA7

PA5

PB16

TEXP

EXTCLK

HRESET

PB18

EXTAL

PB19

PB17

VDDL

GND

RSTCONF SRESET

VDDL

PA3

GND

XTAL

PA4

PA2

PD12

VDDH

WAIT_A

PORESET

WAIT_B

PB15

VDDH

KAPWR

PC6

PC5

PD11

VDDH D12

D17

D15

D22

D25

D31

IPA6

IPA0

IPA7

XFC

IPA1

PC4

PD7

VDDSYN

PA1

PB14

PD4

IRQ1

D23

D11

D16

D19

D21

D26

D30

IPA5

IPA2

N/C

IPA4

PD15

PD5

VSSSYN

PA0

PD13

PD6

IRQ0 D13

D27

D10

D14

D18

D20

D24

D28

DP1

DP0

N/C

DP3

PD9

M_Tx_EN

VSSSYN1

PD14

PD10

PD8

MPC860 Family Hardware Specifications

MOTOROLA

Mechanical Data and Ordering Information

14.2

Mechanical Dimensions of the PBGA Package

For more information on the printed circuit board layout of the PBGA package, including thermal via design
and suggested pad layout, please refer to Motorola Application Note, Plastic Ball Grid Array (order
number: AN1231/D), available from your local Motorola sales office. Figure 75 shows the mechanical
dimensions of the PBGA package.

Figure 75. Mechanical Dimensions and Bottom Surface Nomenclature

of the PBGA Package

SIDE VIEW

BOTTOM VIEW

18X

357X

TOP VIEW

A2
A3

0.3 M C

0.15 M C

0.2 C

0.2

A B

0.25 C

0.35 C

NOTES:

1. Dimensions and tolerance per ASME Y14.5M, 1994.
2. Dimensions in millimeters.
3. Dimension b is the maximum solder ball diameter

measured parallel to datum C.

DIM

MIN

MAX

MILLIMETERS

---

2.05

0.50

0.70

0.95

1.35

0.70

0.90

0.60

0.90

25.00 BSC

22.86 BSC

22.40

22.60

1.27 BSC

25.00 BSC

22.86 BSC

22.40

22.60

Case No. 1103-01

MOTOROLA

MPC860 Family Hardware Specifications

Document Revision History

Table 34 lists significant changes between revisions of this document.

Table 34. Document Revision History

Revision

Date

Change

5.1

11/2001

Revised template format, removed references to MAC functionality, changed Table 6
B23 max value @ 66 Mhz from 2ns to 8ns, added this revision history table

10/2002

Added the MPC855T. Corrected Figure 25 on page 35.

6.1

11/2002

· Corrected UTOPIA RXenb* and TXenb* timing values.
· Changed incorrect usage of Vcc to Vdd.
· Corrected dual port RAM to 8Kbytes.

6.2

8/2003

· Changed B28a through B28d and B29d to show that TRLX can be 0 or 1.
· Changed reference documentation to reflect the Rev 2 MPC860 PowerQUICC Family

Users Manual.

· Nontechnical reformatting

MPC860EC/D

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Document Outline

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Document Outline

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