1
Motorola TMOS Power MOSFET Transistor Device Data
Designer's
TM
Data Sheet
SWITCHMODE
TM
Schottky Power Rectifier
D3PAK Power Surface Mount Package
Employing the Schottky Barrier principle in a large area metaltosilicon power
rectifier. Features epitaxial construction with oxide passivation and metal overlay
contact. Ideally suited for low voltage, high frequency switching power supplies;
free wheeling diodes and polarity protection diodes.
Compact Package Ideal for Automated Handling
Short Heat Sink Tab Manufactured -- Not Sheared
Highly Stable Oxide Passivated Junction
Guardring for Overvoltage Protection
Low Forward Voltage Drop
Monolithic Dual Die Construction. May be Paralleled for High Current Output.
Mechanical Characteristics:
Case: Epoxy, Molded
Weight: 2 Grams (approximately)
Finish: All External Surfaces Corrosion Resistant and Terminal Leads are
Readily Solderable
Maximum Temperature of 260
C for 10 Seconds for Soldering
Shipped 29 Units per Plastic Tube
Marking: MBRV7030CTL
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Peak Repetitive Reverse Voltage
Working Peak Reverse Voltage
DC Blocking Voltage
VRRM
VRWM
VR
30
V
Average Rectified Forward Current
Per Leg
(At Rated VR, TC = 135
C)
Per Package
IO
35
70
A
Peak Repetitive Forward Current
Per Leg
(At Rated VR, Square Wave, 20 kHz, TC = 135
C)
IFRM
70
A
NonRepetitive Peak Surge Current
Per Package
(Surge applied at rated load conditions, halfwave, single phase, 60 Hz)
IFSM
500
A
Storage / Operating Case Temperature
Tstg, TC
55 to 150
C
Operating Junction Temperature
TJ
55 to 150
C
Voltage Rate of Change (Rated VR, TJ = 25
C)
dv/dt
10,000
V/
m
s
THERMAL CHARACTERISTICS
Thermal Resistance -- JunctiontoCase
Per Leg
Thermal Resistance -- JunctiontoAmbient (2)
Per Leg
R
q
JC
R
q
JA
0.59
54
C/W
ELECTRICAL CHARACTERISTICS
Maximum Instantaneous Forward Voltage (1), see Figure 2
Per Leg
(IF = 35 A, TJ = 25
C)
(IF = 70 A, TJ = 25
C)
(IF = 35 A, TJ = 100
C)
VF
0.50
0.62
0.47
V
Maximum Instantaneous Reverse Current, see Figure 4
Per Leg
(Rated VR, TJ = 25
C)
(Rated VR, TJ = 100
C)
IR
2.0
40
mA
(1) Pulse Test: Pulse Width
250
s, Duty Cycle
2%
(2) Rating applies when using minimum pad size, FR4 PC Board
Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design.
Designer's and Switchmode are trademarks of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
Order this document
by MBRV7030CTL/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MBRV7030CTL
SCHOTTKY BARRIER
RECTIFIER
70 AMPERES
30 VOLTS
CASE 433A01, Style 1
D3PAK
1
3
2
1
2
3
Motorola Preferred Device
Motorola, Inc. 1997
MBRV7030CTL
2
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
VF, INSTANTANEOUS FORWARD VOLTAGE (VOLTS)
Figure 1. Typical Forward Voltage
I F
, INST
ANT
ANEOUS
FOR
W
ARD
CURRENT
(AMPS)
VF, MAXIMUM INSTANTANEOUS FORWARD VOLTAGE (VOLTS)
Figure 2. Maximum Forward Voltage
VR, REVERSE VOLTAGE (VOLTS)
Figure 3. Typical Reverse Current
VR, REVERSE VOLTAGE (VOLTS)
Figure 4. Maximum Reverse Current
TC, CASE TEMPERATURE (
C)
Figure 5. Current Derating (Per Leg)
IO, AVERAGE FORWARD CURRENT (AMPS)
Figure 6. Forward Power Dissipation (Per Leg)
TJ = 25
C
0.8
0.6
0.4
0.2
0
100
10
1.0
0.8
0.6
0.4
0.2
0
100
10
1.0
30
20
10
0
0.00001
0.0001
0.001
0.01
0.1
1.0
30
20
10
0
0.01
0.1
1.0
10
0.001
160
140
120
100
80
60
40
20
0
60
50
40
30
20
10
0
75
50
25
0
30
25
20
15
10
5
0
TJ = 150
C
TJ = 100
C
I F
, INST
ANT
ANEOUS
FOR
W
ARD
CURRENT
(AMPS)
I R
, REVERSE CURRENT
(AMPS)
TJ = 25
C
TJ = 150
C
TJ = 100
C
TJ = 25
C
TJ = 150
C
TJ = 100
C
I R
, MAXIMUM REVERSE CURRENT
(AMPS)
TJ = 25
C
TJ = 150
C
TJ = 100
C
I O
, A
VERAGE
FOR
W
ARD
CURRENT
(AMPS)
FREQ = 20 kHz
P
FO
,
A
VERAGE POWER DISSIP
A
TION
(W
A
TTS)
square wave
Ipk/Io =
p
Ipk/Io = 5
Ipk/Io = 10
Ipk/Io = 20
dc
square
wave
Ipk/Io =
p
Ipk/Io = 5
Ipk/Io = 10
Ipk/Io = 20
dc
TJ = 150
C
MBRV7030CTL
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
C, CAP
ACIT
ANCE
(pF)
Figure 7. Capacitance
VR, REVERSE VOLTAGE (VOLTS)
1.0
10
100
100,000
10,000
1,000
TJ = 25
C
SAFE OPERATING AREA
t, TIME (SECONDS)
r(t)
, NORMALIZED EFFECTIVE
TRANSIENT
THERMAL
RESIST
ANCE
R
JC(t) = r(t) R
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) R
JC(t)
P(pk)
t1
t2
DUTY CYCLE, D = t1/t2
Figure 8. Thermal Response
Figure 9. Test Circuit for Repetitive
Reverse Current
0.000001
0.00001
0.0001
0.001
0.01
0.1
1.0
10
0.01
0.1
1.0
2N6277
100
2N2222
+ 150 V,
10 mAdc
VCC
12 Vdc
CURRENT
AMPLITUDE
ADJUST
0 10 AMPS
12 V
100
W
CARBON
1 CARBON
1N5817
4
m
F
D.U.T.
2 k
W
2
m
s
1 kHz
+
MBRV7030CTL
4
Motorola TMOS Power MOSFET Transistor Device Data
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface
between the board and the package. With the correct pad
geometry, the packages will self align when subjected to a
solder reflow process.
0.190
4.826
mm
inches
0.100
2.54
0.063
1.6
0.165
4.191
0.118
3.0
0.243
6.172
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
The power dissipation for a surface mount device is a
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
mount device is determined by TJ(max), the maximum rated
junction temperature of the die, R
JA, the thermal resistance
from the device junction to ambient, and the operating
temperature, TA. Using the values provided on the data sheet,
PD can be calculated as follows:
PD =
TJ(max) TA
R
JA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25
C, one can
calculate the power dissipation of the device. For a D3PAK
device, PD is calculated as follows.
PD =
150
C 25
C
54
C/W
= 2.31 Watts
The 54
C/W for the D3PAK package assumes the use of the
recommended footprint on a glass epoxy printed circuit board
to achieve a power dissipation of 2.31 Watts. There are other
alternatives to achieving higher power dissipation from the
surface mount packages. One is to increase the area of the
drain pad. By increasing the area of the drain pad, the power
dissipation can be increased. Although one can almost double
the power dissipation with this method, one will be giving up
area on the printed circuit board which can defeat the purpose
of using surface mount technology. For example, a graph of
R
JA versus drain pad area is shown in Figure 11.
Figure 10. Thermal Resistance versus Drain Pad
Area for the D3PAK Package (Typical)
1.75 Watts
Board Material = 0.0625
G10/FR4, 2 oz Copper
80
100
60
40
20
10
8
6
4
2
0
3.0 Watts
5.0 Watts
TA = 25
C
A, AREA (SQUARE INCHES)
T
O
AMBIENT
(
C/W)
R
JA
, THERMAL
RESIST
ANCE,
JUNCTION
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad
TM
. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
MBRV7030CTL
5
Motorola TMOS Power MOSFET Transistor Device Data
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads. Solder
stencils are used to screen the optimum amount. These
stencils are typically 0.008 inches thick and may be made of
brass or stainless steel. For packages such as the SC59,
SC70/SOT323, SOD123, SOT23, SOT143, SOT223,
SO8, SO14, SO16, and SMB/SMC diode packages, the
stencil opening should be the same as the pad size or a 1:1
registration. This is not the case with the DPAK and D2PAK
packages. If one uses a 1:1 opening to screen solder onto the
drain pad, misalignment and/or "tombstoning" may occur due
to an excess of solder. For these two packages, the opening
in the stencil for the paste should be approximately 50% of the
tab area. The opening for the leads is still a 1:1 registration.
Figure 12 shows a typical stencil for the DPAK and D2PAK
packages. The pattern of the opening in the stencil for the
drain pad is not critical as long as it allows approximately 50%
of the pad to be covered with paste.
Figure 11. Typical Stencil for DPAK and
D2PAK Packages
SOLDER PASTE
OPENINGS
STENCIL
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
Always preheat the device.
The delta temperature between the preheat and soldering
should be 100
C or less.*
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10
C.
The soldering temperature and time shall not exceed
260
C for more than 10 seconds.
When shifting from preheating to soldering, the maximum
temperature gradient shall be 5
C or less.
After soldering has been completed, the device should be
allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
* Due to shadowing and the inability to set the wave height to
incorporate other surface mount components, the D2PAK is
not recommended for wave soldering.
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