MOTOROLA CMOS LOGIC DATA
1
MC14069UB
Hex Inverter
The MC14069UB hex inverter is constructed with MOS Pchannel and
Nchannel enhancement mode devices in a single monolithic structure.
These inverters find primary use where low power dissipation and/or high
noise immunity is desired. Each of the six inverters is a single stage to
minimize propagation delays.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two LowPower TTL Loads or One LowPower
Schottky TTL Load Over the Rated Temperature Range
Triple Diode Protection on All Inputs (see Page 52)
PinforPin Replacement for CD4069UB
Meets JEDEC UB Specifications
MAXIMUM RATINGS*
(Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage
0.5 to + 18.0
V
Vin, Vout
Input or Output Voltage (DC or Transient)
0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current (DC or Transient),
per Pin
10
mA
PD
Power Dissipation, per Package
500
mW
Tstg
Storage Temperature
65 to + 150
_
C
TL
Lead Temperature (8Second Soldering)
260
_
C
* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:
Plastic "P and D/DW" Packages: 7.0 mW/
_
C From 65
_
C To 125
_
C
Ceramic "L" Packages: 12 mW/
_
C From 100
_
C To 125
_
C
CIRCUIT SCHEMATIC
(1/6 OF CIRCUIT SHOWN)
LOGIC DIAGRAM
13
11
9
5
3
1
12
10
8
6
4
2
VDD = PIN 14
VSS = PIN 7
VDD
VSS
OUTPUT
INPUT*
* Double diode protection on all
inputs not shown.
Figure 1. Switching Time Test Circuit and Waveforms
PULSE
GENERATOR
VDD
VSS
7
INPUT
OUTPUT
CL
14
20 ns
20 ns
VDD
VSS
VOH
VOL
tTHL
tTLH
OUTPUT
INPUT
tPHL
tPLH
90%
50%
10%
90%
50%
10%
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
MC14068B
See Page 6-5
MC14069UB
L SUFFIX
CERAMIC
CASE 632
ORDERING INFORMATION
MC14XXXUBCP
Plastic
MC14XXXUBCL
Ceramic
MC14XXXUBD
SOIC
TA = 55
to 125
C for all packages.
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
PIN ASSIGNMENT
11
12
13
14
8
9
10
5
4
3
2
1
7
6
OUT 5
IN 5
OUT 6
IN 6
VDD
OUT 4
IN 4
OUT 2
IN 2
OUT 1
IN 1
VSS
OUT 3
IN 3
MOTOROLA CMOS LOGIC DATA
MC14069UB
2
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to VSS)
Characteristic
Symbol
VDD
Vdc
55
_
C
25
_
C
125
_
C
Unit
Characteristic
Symbol
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
Output Voltage
"0" Level
Vin = VDD
Vin = 0
"1" Level
VOL
5.0
10
15
--
--
--
0.05
0.05
0.05
--
--
--
0
0
0
0.05
0.05
0.05
--
--
--
0.05
0.05
0.05
Vdc
Vin = 0
"1" Level
VOH
5.0
10
15
4.95
9.95
14.95
--
--
--
4.95
9.95
14.95
5.0
10
15
--
--
--
4.95
9.95
14.95
--
--
--
Vdc
Input Voltage
"0" Level
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
"1" Level
(VO = 0.5 Vdc)
(VO = 1.0 Vdc)
(VO = 1.5 Vdc)
VIL
5.0
10
15
--
--
--
1.0
2.0
2.5
--
--
--
2.25
4.50
6.75
1.0
2.0
2.5
--
--
--
1.0
2.0
2.5
Vdc
"1" Level
(VO = 0.5 Vdc)
(VO = 1.0 Vdc)
(VO = 1.5 Vdc)
VIH
5.0
10
15
4.0
8.0
12.5
--
--
--
4.0
8.0
12.5
2.75
5.50
8.25
--
--
--
4.0
8.0
12.5
--
--
--
Vdc
Output Drive Current
(VOH = 2.5 Vdc)
Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
IOH
5.0
5.0
10
15
3.0
0.64
1.6
4.2
--
--
--
--
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
--
--
--
--
1.7
0.36
0.9
2.4
--
--
--
--
mAdc
(VOL = 0.4 Vdc)
Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOL
5.0
10
15
0.64
1.6
4.2
--
--
--
0.51
1.3
3.4
0.88
2.25
8.8
--
--
--
0.36
0.9
2.4
--
--
--
mAdc
Input Current
Iin
15
--
0.1
--
0.00001
0.1
--
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
--
--
--
--
5.0
7.5
--
--
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
--
--
--
0.25
0.5
1.0
--
--
--
0.0005
0.0010
0.0015
0.25
0.5
1.0
--
--
--
7.5
15
30
Adc
Total Supply Current**
(Dynamic plus Quiescent,
Per Gate) (CL = 50 pF)
IT
5.0
10
15
IT = (0.3
A/kHz) f + IDD/6
IT = (0.6
A/kHz) f + IDD/6
IT = (0.9
A/kHz) f + IDD/6
Adc
Output Rise and Fall Times**
(CL = 50 pF)
tTLH, tTHL = (1.35 ns/pF) CL + 33 ns
tTLH, tTHL = (0.60 ns/pF) CL + 20 ns
tTLH, tTHL = (0.40 ns/pF) CL + 20 ns
tTLH,
tTHL
5.0
10
15
--
--
--
--
--
--
--
--
--
100
50
40
200
100
80
--
--
--
--
--
--
ns
Propagation Delay Times**
(CL = 50 pF)
tPLH, tPHL = (0.90 ns/pF) CL + 20 ns
tPLH, tPHL = (0.36 ns/pF) CL + 22 ns
tPLH, tPHL = (0.26 ns/pF) CL + 17 ns
tPLH,
tPHL
5.0
10
15
--
--
--
--
--
--
--
--
--
65
40
30
125
75
55
--
--
--
--
--
--
ns
#Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
** The formulas given are for the typical characteristics only at 25
_
C.
To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL 50) Vfk
where: IT is in
A (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.002.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS
(Vin or Vout)
VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
MOTOROLA CMOS LOGIC DATA
3
MC14069UB
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 63208
ISSUE Y
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.750
0.785
19.05
19.94
B
0.245
0.280
6.23
7.11
C
0.155
0.200
3.94
5.08
D
0.015
0.020
0.39
0.50
F
0.055
0.065
1.40
1.65
G
0.100 BSC
2.54 BSC
J
0.008
0.015
0.21
0.38
K
0.125
0.170
3.18
4.31
L
0.300 BSC
7.62 BSC
M
0
15
0
15
N
0.020
0.040
0.51
1.01
_
_
_
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
A
B
C
14 PL
D
G
F
N
K
14 PL
J
M
L
S
B
M
0.25 (0.010)
T
S
A
M
0.25 (0.010)
T
T
SEATING
PLANE
1
7
14
9
P SUFFIX
PLASTIC DIP PACKAGE
CASE 64606
ISSUE L
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
1
7
14
8
B
A
F
H
G
D
K
C
N
L
J
M
SEATING
PLANE
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.715
0.770
18.16
19.56
B
0.240
0.260
6.10
6.60
C
0.145
0.185
3.69
4.69
D
0.015
0.021
0.38
0.53
F
0.040
0.070
1.02
1.78
G
0.100 BSC
2.54 BSC
H
0.052
0.095
1.32
2.41
J
0.008
0.015
0.20
0.38
K
0.115
0.135
2.92
3.43
L
0.300 BSC
7.62 BSC
M
0
10
0
10
N
0.015
0.039
0.39
1.01
_
_
_
_
MOTOROLA CMOS LOGIC DATA
MC14069UB
4
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
A
B
G
P
7 PL
14
8
7
1
M
0.25 (0.010)
B
M
S
B
M
0.25 (0.010)
A
S
T
T
F
R
X 45
SEATING
PLANE
D
14 PL
K
C
J
M
_
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
8.55
8.75
0.337
0.344
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.054
0.068
D
0.35
0.49
0.014
0.019
F
0.40
1.25
0.016
0.049
G
1.27 BSC
0.050 BSC
J
0.19
0.25
0.008
0.009
K
0.10
0.25
0.004
0.009
M
0
7
0
7
P
5.80
6.20
0.228
0.244
R
0.25
0.50
0.010
0.019
_
_
_
_
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MC14069UB/D
*MC14069UB/D*
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