MC145406
1
MOTOROLA
Driver/Receiver
EIA 232E and CCITT V.28 (Formerly RS232D)
The MC145406 is a silicongate CMOS IC that combines three drivers
and three receivers to fulfill the electrical specifications of standards
E I A 2 3 2 E a n d C C I T T V. 2 8 . T h e d r i v e r s f e a t u r e t r u e T T L i n p u t
compatibility, slewratelimited output, 300
poweroff source imped-
ance, and output typically switching to within 25% of the supply rails. The
receivers can handle up to
25 V while presenting 3 to 7 k
impedance.
Hysteresis in the receivers aids reception of noisy signals. By combining
both drivers and receivers in a single CMOS chip, the MC145406 provides
efficient, lowpower solutions for EIA 232E and V.28 applications.
Drivers
5 V to
12 V Supply Range
300
PowerOff Source Impedance
Output Current Limiting
TTL Compatible
Maximum Slew Rate = 30 V/
s
Receivers
25 V Input Voltage Range When VDD = 12 V, VSS = 12 V
3 to 7 k
Input Impedance
Hysteresis on Input Switchpoint
BLOCK DIAGRAM
VDD
RECEIVER
VCC
DO
DI
1.4 V
HYSTERESIS
1.8 V
1.0 V
DRIVER
LEVEL
SHIFT
300
Tx
VSS
5.4 k
Rx
15 k
*Protection circuit
VCC
VDD
VDD
VCC
VSS
+
+
*
Order this document
by MC145406/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
PIN ASSIGNMENT
MC145406
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOG
CASE 751G
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R
D
VDD
Rx1
Tx1
Rx2
Tx2
Rx3
Tx3
VSS
VCC
DO1
DI1
DO2
DI2
DO3
DI3
GND
D = DRIVER
R = RECEIVER
R
R
D
D
16
1
16
1
SD SUFFIX
SSOP
CASE 940B
Motorola, Inc. 1995
REV 4
1/95
MC145406
2
MOTOROLA
MAXIMUM RATINGS
(Voltage polarities referenced to GND)
Rating
Symbol
Value
Unit
DC Supply Voltages (VDD
VCC)
VDD
VSS
VCC
0.5 to + 13.5
+ 0.5 to 13.5
0.5 to + 6.0
V
Input Voltage Range
Rx13 Inputs
DI13 Inputs
VIR
(VSS 15) to (VDD + 15)
0.5 to (VCC + 0.5)
V
DC Current Per Pin
100
mA
Power Dissipation
PD
1.0
W
Operating Temperature Range
TA
40 to + 85
C
Storage Temperature Rate
Tstg
85 to + 150
C
DC ELECTRICAL CHARACTERISTICS
(All polarities referenced to GND = 0 V, TA = 40 to +85
C)
Parameter
Symbol
Min
Typ
Max
Unit
DC Supply Voltage
VDD
VSS
VCC (VDD
VCC)
VDD
VSS
VCC
4.5
4.5
4.5
5 to 12
5 to 12
5.0
13.2
13.2
5.5
V
Quiescent Supply Current (Outputs unloaded, inputs low)
VDD = + 12 V
VSS =
12 V
VCC = + 5 V
IDD
ISS
ICC
--
--
--
140
340
300
400
600
450
A
RECEIVER ELECTRICAL SPECIFICATIONS
(Voltage polarities referenced to GND = 0 V, VDD = +
5 to +
12 V, VSS =
5 to 12 V, VDD
VCC, TA =
40 to +
85
C)
Characteristic
Symbol
Min
Typ
Max
Unit
Input Turnon Threshold
Rx1Rx3
VDO1DO3 = VOL, VCC = 5.0 V
5%
Von
1.35
1.80
2.35
V
Input Turnoff Threshold
Rx1Rx3
VDO1DO3 = VOH, VCC = 5.0 V
5%
Voff
0.75
1.00
1.25
V
Input Threshold Hysteresis
Rx1Rx3
VCC = 5.0 V
5%
VonVoff
0.6
0.8
--
V
Input Resistance
Rx1Rx3
(VSS
15 V)
VRx1Rx3
(VDD + 15 V)
Rin
3.0
5.4
7.0
k
HighLevel Output Voltage (VRx1Rx3 = 3 V to (VSS 15 V))*
DO1DO3
IOH = 20
A, VCC = +
5.0 V
IOH = 1 mA, VCC = +
5.0 V
VOH
4.9
3.8
4.9
4.3
--
--
V
LowLevel Output Voltage (VRx1Rx3 = +
3 V to (VDD + 15 V))* DO1DO3
IOL = +
20
A, VCC = + 5.0 V
IOL = +
2 mA, VCC = + 5.0 V
IOL = + 4 mA, VCC = + 5.0 V
VOL
--
--
--
0.01
0.02
0.5
0.1
0.5
0.7
V
* This is the range of input voltages as specified by EIA 232E to cause a receiver to be in the high or low logic state.
This device contains protection circuitry to pro-
tect the inputs against damage due to high static
voltages or electric fields; however, it is advised
that normal precautions be taken to avoid applica-
tion of any voltage higher than maximum rated
voltages to this high impedance circuit. For proper
operation, it is recommended that the voltages at
the DI and DO pins be constrained to the range
GND
VDI
VCC and GND
VDO
VCC. Also, the
voltage at the Rx pin should be constrained to
(VSS 15 V)
VRx13
(VDD + 15 V), and Tx
should be constrained to VSS
VTx13
VDD.
Unused inputs must always be tied to an ap-
propriate logic voltage level (e.g., GND or VCC for
DI and Ground for Rx.)
MC145406
3
MOTOROLA
ELECTRICAL SPECIFICATIONS
(Voltage polarities referenced to GND = 0 V, VCC = + 5 V
5%, TA = 40 to +
85
C)
Characteristic
Symbol
Min
Typ
Max
Unit
Digital Input Voltage
DI1DI3
Logic 0
Logic 1
VIL
VIH
--
2.0
--
--
0.8
--
V
Input Current
DI1DI3
VDI1DI3 = VCC
Iin
--
--
1.0
A
Output High Voltage (VDI13 = Logic 0, RL = 3.0 k
)
Tx1Tx3
VDD = + 5.0 V, VSS =
5.0 V
VDD = + 6.0 V, VSS = 6.0
VDD = +
12.0 V, VSS =
12.0 V
VOH
3.5
4.3
9.2
3.9
4.7
9.5
--
--
--
V
Output Low Voltage* (VDI13 = Logic 1, RL = 3.0 k
)
Tx1Tx3
VDD = + 5.0 V, VSS = 5.0 V
VDD = + 6.0 V, VSS = 6.0 V
VDD = +
12.0 V, VSS = 12.0 V
VOL
4.0
4.5
10.0
4.3
5.2
10.3
--
--
--
V
Off Source Resistance (Figure 1)
Tx1Tx3
VDD = VSS = GND = 0 V, VTx1Tx3 =
2.0 V
300
--
--
Output ShortCircuit Current (VDD = +
12.0 V, VSS = 12.0 V)
Tx1Tx3
Tx1Tx3 shorted to GND**
Tx1Tx3 shorted to
15.0 V***
ISC
--
--
22
60
60
100
mA
* The voltage specifications are in terms of absolute values.
** Specification is for one Tx output pin to be shorted at a time. Should all three driver outputs be shorted simultaneously, device power dissipation
limits will be exceeded.
*** This condition could exceed package limitations.
SWITCHING CHARACTERISTICS
(VCC = +
5 V
5%, TA =
40 to + 85
C; See Figures NO TAG and NO TAG)
Drivers
Characteristic
Symbol
Min
Typ
Max
Unit
Propagation Delay Time
Tx1Tx3
LowtoHigh
RL = 3 k
, CL = 50 pF
tPLH
--
300
500
ns
HightoLow
RL = 3 k
CL = 50 pF
tPHL
--
300
500
Output Slew Rate
Tx1Tx3
Minimum Load
RL = 7 k
, CL = 0 pF, VDD = +
6 to +
12 V, VSS =
6 to
12 V
SR
--
9
30
V/
s
Maximum Load
RL = 3 k
, CL = 2500 pF
VDD = + 12 V, VSS = 12 V
VDD = + 5 V, VSS = 5 V
4
--
--
--
--
--
Receivers (CL = 50 pF)
Characteristic
Symbol
Min
Typ
Max
Unit
Propagation Delay Time
DO1DO3
LowtoHigh
tPLH
--
150
425
ns
HightoLow
tPHL
--
150
425
Output Rise Time
DO1DO3
tr
--
250
400
ns
Output Fall Time
DO1DO3
tf
--
40
100
ns
MC145406
4
MOTOROLA
Vin =
2 V
3
5
7
14
12
10
8
9
1
16
VDD VCC
DI1
DI2
DI3
VSS GND
Tx3
Tx2
Tx1
Rout =
Vin
I
Figure 1. PowerOff Source Resistance (Drivers)
Figure 2. Switching Characteristics
Figure 3. SlewRate Characterization
DRIVERS
DI1DI3
3 V
0 V
VOH
VOL
Tx1Tx3
tPLH
tPHL
50%
tf
tr
10%
90%
RECEIVERS
Rx1Rx3
DO1DO3
+ 3 V
0 V
VOH
VOL
tPLH
tPHL
tf
tr
50%
DRIVERS
Tx1Tx3
90%
50%
3 V
3 V
3 V
3 V
tSHL
tSLH
SLEW RATE (SR) =
3 V (3 V)
OR
3 V ( 3 V)
tSLH
tSHL
10%
PIN DESCRIPTIONS
VDD
Positive Power Supply (Pin 1)
The most positive power supply pin, which is typically + 5
to +
12V.
VSS
Negative Power Supply (Pin 8)
The most negative power supply pin, which is typically 5
to
12 V.
VCC
Digital Power Supply (Pin 16)
The digital supply pin, which is connected to the logic
power supply (maximum +
5.5 V). VCC must be less than
or equal to VDD.
GND
Ground (Pin 9)
Ground return pin is typically connected to the signal
ground pin of the EIA 232E connector (Pin 7) as well as to
the logic power supply ground.
Rx1, Rx2, Rx3
Receive Data Input (Pins 2, 4, 6)
These are the EIA 232E receive signal inputs whose
voltages can range from (VDD + 15 V) to (VSS 15 V). A volt-
age between +
3 and (VDD + 15 V) is decoded as a space
and causes the corresponding DO pin to swing to ground (0
V); a voltage between 3 and (VDD 15 V) is decoded as a
mark and causes the DO pin to swing up to VCC. The actual
turnon input switchpoint is typically biased at 1.8 V above
ground, and includes 800 mV of hysteresis for noise rejec-
tion. The nominal input impedance is 5 k
. An open or
grounded input pin is interpreted as a mark, forcing the DO
pin to VCC.
DO1, DO2, DO3
Data Output (Pins 11, 13, 15)
These are the receiver digital output pins, which swing
from VCC to GND. A space on the Rx pin causes DO to pro-
duce a logic 0; a mark produces a logic 1. Each output pin is
capable of driving one LSTTL input load.
DI1, DI2, DI3
Data Input (Pins 10, 12,14)
These are the highimpedance digital input pins to the
drivers. TTL compatibility is accomplished by biasing the in-
put switchpoint at 1.4 V above GND. However, 5V CMOS
compatibility is maintained as well. Input voltage levels on
these pins must be between VCC and GND.
Tx1, Tx2, Tx3
Transmit Data Output (Pins 3, 5, 7)
These are the EIA 232E transmit signal output pins,
which swing toward VDD and VSS. A logic 1 at a DI input
causes the corresponding Tx output to swing toward VSS. A
logic 0 causes the output to swing toward VDD (the output
voltages will be slightly less than VDD or VSS depending upon
the output load). Output slew rates are limited to a maximum
of 30 V per
s. When the MC145406 is off (VDD = VSS = VCC
= GND), the minimum output impedance is 300
.
MC145406
5
MOTOROLA
APPLICATIONS INFORMATION
The MC145406 has been designed to meet the electrical
specifications of standards EIA 232E and CCITT V.28.
EIA 232E defines the electrical and physical interface be-
tween Data Communication Equipment (DCE) and Data
Terminal Equipment (DTE). A DCE is connected to a DTE
using a cable that typically carries up to 25 leads. These
leads, referred to as interchange circuits, allow the transfer
of timing, data, control, and test signals. Electrically this
transfer requires level shifting between the TTL/CMOS log-
ic levels of the computer or modem and the high voltage lev-
els of EIA 232E, which can range from
3 to
25 V. The
MC145406 provides the necessary level shifting as well as
meeting other aspects of the EIA 232E specification.
DRIVERS
As defined by the specification, an EIA 232E driver pres-
ents a voltage of between
5 to
15 V into a load of be-
tween 3 to 7 k
. A logic 1 at the driver input results in a
voltage of between
5 to 15 V. A logic 0 results in a voltage
between + 5 to + 15V. When operating VDD and VSS at
7 to
12 V, the MC145406 meets this requirement. When operat-
ing at
5 V, the MC145406 drivers produce less than
5 V at the output (when terminated), which does not meet
EIA 232E specification. However, the output voltages when
using a
5 V power supply are high enough (around
4 V) to permit proper reception by an EIA 232E receiver,
and can be used in applications where strict compliance to
EIA 232E is not required.
Another requirement of the MC145406 drivers is that
they withstand a short to another driver in the EIA 232E
cable. The worstcase condition that is permitted by
EIA 232E is a
15 V source that is current limited to 500
mA. The MC145406 drivers can withstand this condition
momentarily. In most short circuit conditions the source
driver will have a series 300
output impedance needed
to satisfy the EIA 232E driver requirements. This will re-
duce the short circuit current to under 40 mA which is an
acceptable level for the MC145406 to withstand.
Unlike some other drivers, the MC145406 drivers feature
an internallylimited output slewrate that does not exceed
30 V per
s.
RECEIVERS
The job of an EIA 232E receiver is to levelshift voltages
in the range of 25 to + 25 V down to TTL/CMOS logic lev-
els (0 to + 5 V). A voltage of between 3 and 25 V on Rx1
is defined as a mark and produces a logic 1 at DO1. A volt-
age between + 3 and + 25 V is a space and produces a logic
zero. While receiving these signals, the Rx inputs must pres-
ent a resistance between 3 and 7 k
. Nominally, the input re-
sistance of the Rx1Rx3 inputs is 5.4 k
.
The input threshold of the Rx1Rx3 inputs is typically
biased at 1.8 V above ground (GND) with typically 800 mV of
hysteresis included to improve noise immunity. The 1.8 V
bias forces the appropriate DO pin to a logic 1 when its Rx
input is open or grounded as called for in the EIA 232E
specification. Notice that TTL logic levels can be applied to
the Rx inputs in lieu of normal EIA 232E signal levels. This
might be helpful in situations where access to the modem or
computer through the EIA 232E connector is necessary
with TTL devices. However, it is important not to connect the
EIA 232E outputs (Tx1Tx3) to TTL inputs since TTL oper-
ates off + 5 V only, and may be damaged by the high output
voltage of the MC145406.
The DO outputs are to be connected to a TTL or CMOS
input (such as an input to a modem chip). These outputs
will swing from VCC to ground, allowing the designer to op-
erate the DO and DI pins from digital power supply. The Tx
and Rx sections are independently powered by VDD and
VSS so that one may run logic at + 5 V and the EIA 232E
signals at
12 V.
POWER SUPPLY CONSIDERATIONS
Figure 4 shows a technique to guard against excessive
device current.
The diode D1 prevents excessive current from flowing
through an internal diode from the VCC pin to the VDD pin
when VDD < VCC by approximately 0.6 V. This high current
condition can exist for a short period of time during power
up/down. Additionally, if the + 12 V supply is switched off
while the + 5 V is on and the off supply is a low impedance
to ground, the diode D1 will prevent current flow through
the internal diode.
The diode D2 is used as a voltage clamp, to prevent VSS
from drifting positive to VCC, in the event that power is re-
moved from VSS (Pin 12). If VSS power is removed, and the
impedance from the VSS pin to ground is greater than
approximately 3 k
, this pin will be pulled to VCC by internal
circuitry causing excessive current in the VCC pin.
If by design, neither of the above conditions are allowed
to exist, then the diodes D1 and D2 are not required.
ESD PROTECTION
ESD protection on IC devices that have their pins accessi-
ble to the outside world is essential. High static voltages ap-
plied to the pins when someone touches them either directly
or indirectly can cause damage to gate oxides and transistor
junctions by coupling a portion of the energy from the I/O pin
to the power supply buses of the IC. This coupling will usually
occur through the internal ESD protection diodes. The key to
protecting the IC is to shunt as much of the energy to ground
as possible before it enters the IC. Figure 4 shows a tech-
nique which will clamp the ESD voltage at approximately
15 V using the MMVZ15VDLT1. Any residual voltage which
appears on the supply pins is shunted to ground through the
capacitors C1C3. This scheme has provided protection to
the interface part up to
10 kV, using the human body model
test.
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