MPC2605
1
MOTOROLA
Product Preview
Integrated Secondary Cache
for PowerPC
TM
Microprocessors
The MPC2605 is a single chip, 256KB integrated lookaside cache with
copyback capability designed for PowerPC applications (MPC603 and
MPC604). Using 0.38
m technology along with standard cell logic technology,
the MPC2605 integrates data, tag, host interface, and least recently used (LRU)
memory with a cache controller to provide a 256KB, 512KB, or 1 MB Level 2
cache with one, two, or four chips on a 64bit PowerPC bus.
Single Chip L2 Cache for PowerPC
66 MHz Zero Wait State Performance (2111 Burst)
FourWay Set Associative Cache Design
32K x 72 Data Memory Array
8K x 18 Tag Array
Address Parity Support
LRU Cache Control Logic
CopyBack or WriteThrough Modes of Operation
CopyBack Buffer for Improved Performance
Single 3.3 V Power Supply
5 V Tolerant I/O
One, Two, or Four Chip Cache Solution (256KB, 512KB, or 1MB)
Single Clock Operation
Compliant with IEEE Standard 1149.1 Test Access Port (JTAG)
Supports up to Four Processors in a Shared Cache Configuration
High Board Density 25 mm 241 PBGA Package
WAY SELECT
DH0 DH31
DL0 DL31
DP0 DP7
RD/WR
A27, A28
A0 A31
60X BUS
INTERFACE
RD/WR
BLOCK DIAGRAM
CONTROL
CONTROLLER
AND
BUS INTERFACE
8K x 72 x 4
DATA RAM
COPYBACK
BUFFER
2K x 8 LRU
2K x 18 x 4
TAG RAM
COMPARE
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
Order this document
by MPC2605/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MPC2605
ZP PACKAGE
PBGA
CASE 113801
REV 6
2/26/98
Motorola, Inc. 1998
MPC2605
MOTOROLA
2
PIN ASSIGNMENT
8
5
4
3
2
1
9
B
C
G
A
D
E
F
H
J
DH21
ABB
DH19
DH29
CPU3
BR
CPU3
DBG
DP2
DP3
CFG1
L2 DBG
DH28
VSS
VDD
DH4
CFG0
DBB
CI
AACK
TA
DP0
DH6
DL13
DL29
DL30
DL31
VSS
VSS
VDD
FDN
CPU3
BG
CFG4
L2
MISS INH
K
L
M
N
P
R
V
W
DH27
DH30
HRESET
6
7
DH17
DH22
DH16
VSS
VSS
CPU
BR
WT
DH31
DH18
TEA
PWRDN
VDD
VDD
T
U
CPU2
DBG
ARTRY
17
14
13
12
11
10
18
DL24
DL16
DL19
DP6
DL18
DL21
VSS
AP3
TT2
L2
TAG CLR
TRST
CPU BG
DP7
AP2
L2
FLUSH
TT3
A1
A15
TSIZ0
APEN
VSS
TDO
TDI
SRESET
TT4
TT0
TCK
A14
TSIZ1
VSS
CFG3
VSS
DH24
DH25 DL17
DL20
DL23
DL22
DH26
TT1
A0
15
16
DL25
VDD
CPU4
DBG
DL28
VDD
AP0
CLK
DL27
DL26
CPU4
BR
TS
VDD
A3
A5
NC
TMS
TBST
L2 UPDATE
INH
VDD
CPU4
BG
19
APE
AP1
L2 CI
A2
A16
TSIZ2
GBL
A13
A4
A6
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VSS
VDD
A18
A19
A17
VDD
VSS
VDD
VSS
VDD
VSS
VDD
A22
A20
A21
VDD
CFG2
VDD
VDD
VSS
VDD
VSS
VSS
A24
A25
A23
VDD
VDD
VDD
VSS
VSS
VDD
VSS
A27
A28
A26
VSS
VDD
VSS
VDD
VSS
VDD
VSS
A30
A31
A29
A11
A10
A12
A8
A7
A9
L2 BG
VSS
VSS
VDD
VDD
VDD
VSS
VSS
CPU2
BG
DH5
L2 CLAIM
DH20
DH23
CPU2
BR
L2 BR
CPU
DBG
NC
VDD
VSS
VSS
VSS
DH14
DH10
DL1
DL4
VSS
VSS
VSS
VDD
DL15
DH1
DP1
DH13
DH11
DL0
DL3
DL6
DP4
DL10
DL12
DL14
DH7
DH3
DH0
DH15
DH12
DH9
DH8
DL2
DL5
DL7
DL8
DL9
DL11
DH2
DP5
TOP VIEW (XRAY VIEW)
VSS
VSS
MPC2605
3
MOTOROLA
PIN DESCRIPTIONS
Pin Locations
Pin Name
Type
Description
19G, 17H 19H, 17J 19J,
17K 19K, 17L 19L,
17M 19M, 17N 19N,
17P 19P, 17R 19R,
18T, 19T, 18U, 19U,
18V, 19V, 18W
*
A0 A31
I/O
Address inputs from processor. Can also be outputs for processor snoop
addresses. A0 is the MSB. A31 is the LSB.
3G
AACK
I/O
Address acknowledge input/output.
2A
ABB
I/O
Used as an input to qualify bus grants. Driven as an output during address tenure
initiated by the MPC2605.
17C 19C, 17D
*
AP0 AP3
I/O
Address parity.
19B
APE
O
Address parity error. When an address parity error is detected, APE will be driven
low one clock cycle after the assertion of TS then HighZ following clock cycle.
18E
APEN
I
Address parity enable. When tied low, enables address parity bits and the
address parity error bit.
1G
ARTRY
I/O
Address retry status I/O. Generated when a read or write snoop to a dirty
processor cache line has occurred.
2U
2V
1V
17E
2B
CFG0
CFG1
CFG2
CFG3
CFG4
I
Configuration inputs. These must be tied to either VDD or VSS.
CFG0
CFG1
CFG2
0
0
0
256KB
0
1
0
512KB; A26 = 0
0
1
1
512KB; A26 = 1
1
0
0
1MB; A25 A26 = 00
1
0
1
1MB; A25 A26 = 01
1
1
0
1MB; A25 A26 = 10
1
1
1
1MB; A25 A26 = 11
CFG3
Snoop Data Tenure Selector
0
Supports snoop data tenure
1
Does not support snoop data tenure
CFG4
AACK Driver Enable
0
Disable AACK driver
1
Enable AACK driver
2G
CI
I/O
Cache inhibit I/O.
3M
CLK
I
Clock input. This must be the same as the processor clock input.
2M
CPU BG
I
CPU bus grant input.
3E
CPU2 BG
I
MPC2605 logically ORs this signal with CPU BG. Used in multiprocessor
configuration as the second CPU BG.
1B
CPU3 BG
I
MPC2605 logically ORs this signal with CPU BG. Used in multiprocessor
configuration as the third CPU BG.
1T
CPU4 BG
I
MPC2605 logically ORs this signal with CPU BG. Used in multiprocessor
configuration as the fourth CPU BG.
2H
CPU BR
I
CPU bus request input.
2D
CPU2 BR
I
MPC2605 logically ORs this signal with CPU BR. Used in multiprocessor
configuration as the second CPU BR.
2C
CPU3 BR
I
MPC2605 logically ORs this signal with CPU BR. Used in multiprocessor
configuration as the third CPU BR.
1U
CPU4 BR
I
MPC2605 logically ORs this signal with CPU BR. Used in multiprocessor
configuration as the fourth CPU BR.
1F
CPU DBG
I
CPU data bus grant input from arbiter.
3D
CPU2 DBG
I
MPC2605 logically ORs this signal with CPU DBG. Used in multiprocessor
configuration as the second CPU DBG.
3C
CPU3 DBG
I
MPC2605 logically ORs this signal with CPU DBG. Used in multiprocessor
configuration as the third CPU DBG.
* See pin diagram (page 2) for specific pin assignment of these bus signals.
MPC2605
MOTOROLA
4
Pin Locations
Pin Name
Type
Description
2T
CPU4 DBG
I
MPC2605 logically ORs this signal with CPU DBG. Used in multiprocessor
configuration as the fourth CPU DBG.
11A 13A, 15A 18A,
11B 17B, 11C, 12C, 10U,
11U, 10V 12V, 14V 17V,
11W 17W
*
DL0 DL31
I/O
Data bus low input and output. DL0 is the MSB. DL31 is the LSB.
4A 10A, 4B 10B, 6C,
10C, 8U, 9U, 3V 6V,
8V, 9V, 3W 10W
*
DH0 DH31
I/O
Data bus high input and output. DH0 is the MSB. DH31 is the LSB.
2J
DBB
I/O
Data bus busy. Used as input when processor is master, driven as an output after
a qualified L2 DBG when MPC2605 is the bus master. Note: To operate in Fast
L2 mode, this pin must be tied high.
14A, 18B, 5C, 8C,
16U, 7V, 13V, 2W
*
DP0 DP7
I/O
Data bus parity input and output.
1C
FDN
I/O
Flush done I/O used for communication between other MPC2605 devices. Must
be tied together between all MPC2605 parts along with a pullup resistor.
19E
GBL
O
Global transaction. Always negated when MPC2604 is bus master.
1J
HRESET
I
Hard reset input from processor bus. This is an asynchronous input that must be
low for at least 16 clock cycles to ensure the MPC2605 is properly reset. For
proper initialization, TRST must be asserted before HRESET is asserted.
3A
L2 BG
I
Bus grant input from arbiter.
1D
L2 BR
I/O
Bus request I/O. Normally used as an output.
19D
L2 CI
I
Secondary cache inhibit sampled, after assertion of TS. Assertion prevents
linefill.
2F
L2 CLAIM
O
L2 cache claim output. Used to claim the bus for processor initiated memory
operations that hit the L2 cache. L2 CLAIM goes true (low) before the rising edge
of CLK following TS true. Because this output is not always driven, a pullup
resistor may be necessary to ensure proper system functioning.
2E
L2 DBG
I
Data bus grant input. Comes from system arbiter, used to start data tenure for
bus operations where MPC2605 is the bus master.
18D
L2 FLUSH
I
Causes cache to write back dirty lines and clears all tag valid bits.
3B
L2 MISS INH
I
Prevents line fills on misses when asserted.
2N
L2 TAG CLR
I
Invalidates all tags and holds cache in a reset condition.
3N
L2 UPDATE
INH
I
Cache disable. When asserted, the MPC2605 will not respond to signals on the
local bus and internal states do not change.
3J
PWRDN
I
Provides low power mode. Prevents address and data transitions into the RAM
array. MPC2605 becomes active 4
s after deassertion. Clock must be externally
disabled.
1N
SRESET
I
Soft reset input from processor bus.
1E
TA
I/O
Transfer acknowledge status I/O from processor bus.
3K
TBST
I/O
Transfer burst status I/O from processor bus. Used to distinguish between
burstable and nonburstable memory operations.
2P
TCK
I
Test clock input for IEEE 1149.1 boundary scan (JTAG).
1P
TDI
I
Test data input for IEEE 1149.1 boundary scan (JTAG).
1R
TDO
O
Test data output for IEEE 1149.1 boundary scan (JTAG).
1H
TEA
I
Transfer error acknowledge status input from processor bus.
3P
TMS
I
Test mode select for IEEE 1149.1 boundary scan (JTAG).
* See pin diagram (page 2) for specific pin assignment of these bus signals.
MPC2605
5
MOTOROLA
Pin Locations
Pin Name
Type
Description
2R
TRST
I
Test reset input for IEEE 1149.1 boundary scan (JTAG). If JTAG will not be used,
TRST should be tied low.
3L
TS
I/O
Transfer start I/O from processor bus (can also come from any bus master on the
processor bus). Signals the start of either a processor or bus master cycle.
17F 19F
*
TSIZ0 TSIZ2
I/O
Transfer size I/O from processor bus.
1K, 2K, 1L, 2L, 1M
*
TT0 TT4
I/O
Transfer type I/O from processor bus.
3H
WT
I/O
Write through status input from processor bus. When tied to ground, the
MPC2605 will operate in writethrough mode only (no copyback).
4C, 15C, 16C, 9D 11D,
8H 10H, 4J, 8J, 9J, 16J, 4K,
8K, 12K, 16K, 4L, 11L, 12L,
16L, 10M 12M, 3T, 9T 11T,
17T, 3U, 4U, 15U, 17U
VDD
Supply
Power supply: 3.3 V
5%.
7C, 9C, 13C, 14C, 7D, 8D,
12D, 13D, 4G, 16G 18G,
4H, 11H, 12H, 16H, 10J 12J,
9K 11K, 8L 10L, 4M,
8M, 9M, 16M, 4N, 16N, 7T, 8T,
12T, 13T, 5U 7U, 12U 14U
VSS
Supply
Ground.
3F, 3R
NC
--
No connection: There is no connection to the chip.
* See pin diagram (page 2) for specific pin assignment of these bus signals.
ABSOLUTE MAXIMUM RATINGS
(See Note 1)
Rating
Symbol
Value
Unit
Power Supply Voltage
VDD
0.5 to + 4.6
V
Voltage Relative to VSS
Vin, Vout
0.5 to VDD + 0.5
V
Output Current (per I/O)
Iout
20
mA
Power Dissipation (Note 2)
PD
--
W
Temperature Under Bias
Tbias
10 to + 85
C
Operating Temperature
TJ
0 to + 125
C
Storage Temperature
Tstg
55 to + 125
C
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2. Power dissipation capability is dependent upon package characteristics and use
environment. See Package Thermal Characteristics.
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this highimpedance
circuit.
This BiCMOS memory circuit has been de-
signed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
PDF 
ZIP