PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
This hardware specification contains detailed information on power considerations, DC/AC
electrical characteristics, and AC timing specifications for the MPC8272 family of
devices--the MPC8272, the MPC8248, the MPC8271, and the MPC8247. These devices are
.13m (HiP7) members of the PowerQUICC IITM family of integrated communications
processors. They include on a single chip a 32-bit PowerPC
TM
core that incorporates memory
management units (MMUs) and instruction and data caches and that implements the PowerPC
instruction set; a modified communications processor module (CPM); and an integrated
security engine (SEC) for encryption (the MPC8272 and the MPC8248 only).
All four devices are collectively referred to throughout this hardware specification as `the
MPC8272' unless otherwise noted. The following topics are addressed:
Topic
Page
Section 1, "Overview"
2
Section 2, "Operating Conditions"
7
Section 3, "DC Electrical Characteristics"
8
Section 4, "Thermal Characteristics"
11
Section 5, "Power Dissipation"
14
Section 6, "AC Electrical Characteristics"
14
Section 7, "Clock Configuration Modes"
22
Section 8, "Pinout"
39
Section 9, "Package"
51
Section 10, "Ordering Information"
53
Section 11, "Document Revision History"
53
Advance Information
MPC8272EC
Rev. 0.2 12/2003
MPC8272
PowerQUICC IITM Family
Hardware Specifications
F
r
e
e
s
c
a
l
e
S
e
m
i
c
o
n
d
u
c
t
o
r
,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
.
.
2
MPC8272 PowerQUICC IITM Family Hardware Specifications
MOTOROLA
PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
Overview
Overview
1
Overview
Table 1 shows the functionality supported by each device in the MPC8272 family.
Devices in the MPC8272 family are available in two packages--the VR or ZQ package--as shown in
Table 2. For package ordering information, refer to Section 10, "Ordering Information."
Figure 1 shows the block diagram of the MPC8272.
Table 1. MPC8272 PowerQUICC II Family Functionality
Functionality
Devices
MPC8272
MPC8248
MPC8271
MPC8247
Package
1
1
Refer to Table 2.
516 PBGA
Serial communications controllers (SCCs)
3
3
3
3
QUICC multi-channel controller (QMC)
Yes
Yes
Yes
Yes
Fast communication controllers (FCCs)
2
2
2
2
I-Cache (Kbyte)
16
16
16
16
D-Cache (Kbyte)
16
16
16
16
Ethernet (10/100)
2
2
2
2
UTOPIA II Ports
1
0
1
0
Multi-channel controllers (MCCs)
0
0
0
0
PCI bridge
Yes
Yes
Yes
Yes
Transmission convergence (TC) layer
--
--
--
--
Inverse multiplexing for ATM (IMA)
--
--
--
--
Universal serial bus (USB) 2.0 full/low rate
1
1
1
1
Security engine (SEC)
Yes
Yes
--
--
Table 2. MPC8272 PowerQUICC II Device Packages
Code
(Package)
VR
(516 PBGA--Lead free)
ZQ
(516 PBGA--Lead spheres)
Device
MPC8272VR
MPC8272ZQ
MPC8248VR
MPC8248ZQ
MPC8271VR
MPC8271ZQ
MPC8247VR
MPC8247ZQ
F
r
e
e
s
c
a
l
e
S
e
m
i
c
o
n
d
u
c
t
o
r
,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
.
.
MOTOROLA
MPC8272 PowerQUICC IITM Family Hardware Specifications
3
PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
Overview
Figure 1. Block Diagram
1.1
Features
The major features of the MPC8272 are as follows:
Dual-issue integer (G2_LE) core
-- A core version of the MPC603e microprocessor
-- System core microprocessor supporting frequencies of 266-400 MHz
-- Separate 16-Kbyte data and instruction caches:
Four-way set associative
Physically addressed
LRU replacement algorithm
-- PowerPC architecture-compliant memory management unit (MMU)
-- Common on-chip processor (COP) test interface
-- Supports bus snooping for cache coherency
-- Floating-point unit (FPU) supports floating-point arithmetic
-- Support for cache locking
Low-power consumption
Separate power supply for internal logic (1.5 V) and for I/O (3.3 V)
16 Kbytes
G2_LE Core
I-Cache
I-MMU
16 Kbytes
D-Cache
D-MMU
Communication Processor Module (CPM)
Timers
Parallel I/O
Baud Rate
Generators
32-bit RISC Microcontroller
and Program ROM
Serial
DMA
60x-to-PCI
Bridge
Memory Controller
Clock Counter
System Functions
System Interface Unit
(SIU)
PCI Bus
32 bits, up to 66 MHz
FCC1
FCC2
SCC1
SCC3
SCC4
SMC1
SMC2
SPI
I
2
C
Serial Interface
2 MII/RMII
Port
Ports
60x Bus
Interrupt
Controller
Time Slot Assigner
2 TDM Ports
Non-Multiplexed
I/O
Bus Interface Unit
Virtual
IDMAs
16 KB
Security (SEC)
1
2
1 8-bit Utopia
Serial interface
4 KB
Instruction
RAM
Data
RAM
Note
1
MPC8272/8248 only
2
MPC8272/8271 only
USB 2.0
F
r
e
e
s
c
a
l
e
S
e
m
i
c
o
n
d
u
c
t
o
r
,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
.
.
4
MPC8272 PowerQUICC IITM Family Hardware Specifications
MOTOROLA
PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
Overview
Overview
Separate PLLs for G2_LE core and for the communications processor module (CPM)
-- G2_LE core and CPM can run at different frequencies for power/performance optimization
-- Internal core/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 5.5:1, 6:1,
7:1, and 8:1 ratios
-- Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, and 6:1 ratios
64-bit data and 32-bit address 60x bus
-- Bus supports multiple master designs--up to two external masters
-- Supports single transfers and burst transfers
-- 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
60x-to-PCI bridge
-- Programmable host bridge and agent
-- 32-bit data bus, 66 MHz, 3.3 V
-- Synchronous and asynchronous 60x and PCI clock modes
-- All internal address space available to external PCI host
-- DMA for memory block transfers
-- PCI-to-60x address remapping
System interface unit (SIU)
-- Clock synthesizer
-- Reset controller
-- Real-time clock (RTC) register
-- Periodic interrupt timer
-- Hardware bus monitor and software watchdog timer
-- IEEE 1149.1 JTAG test access port
Eight bank memory controller
-- Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash, and other
user-definable peripherals
-- Byte write enables
-- 32-bit address decodes with programmable bank size
-- Three user programmable machines, general-purpose chip-select machine, and page mode
pipeline SDRAM machine
-- Byte selects for 64-bit bus width (60x)
-- Dedicated interface logic for SDRAM
Disable CPU mode
Integrated security engine (SEC) (MPC8272 and MPC8248 only)
-- Supports DES, 3DES, MD-5, SHA-1, AES, PKEU, RNG and RC-4 encryption algorithms
in hardware
Communications processor module (CPM)
-- Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support
for communications peripherals
-- Interfaces to G2_LE core through on-chip dual-port RAM and DMA controller. (Dual-port
RAM size is 16 Kbyte plus 4Kbyte dedicated instruction RAM.)
F
r
e
e
s
c
a
l
e
S
e
m
i
c
o
n
d
u
c
t
o
r
,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
.
.
MOTOROLA
MPC8272 PowerQUICC IITM Family Hardware Specifications
5
PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
Overview
Universal serial bus (USB) controller
-- Supports USB 2.0 full/low rate compatible
-- USB host mode
Supports control, bulk, interrupt, and isochronous data transfers
CRC16 generation and checking
NRZI encoding/decoding with bit stuffing
Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and
data rate configuration). Note that low-speed operation requires an external hub.
Flexible data buffers with multiple buffers per frame
Supports local loopback mode for diagnostics (12 Mbps only)
-- Supports USB slave mode
Four independent endpoints support control, bulk, interrupt, and isochronous data transfers
CRC16 generation and checking
CRC5 checking
NRZI encoding/decoding with bit stuffing
12- or 1.5-Mbps data rate
Flexible data buffers with multiple buffers per frame
Automatic retransmission upon transmit error
-- Serial DMA channels for receive and transmit on all serial channels
-- Parallel I/O registers with open-drain and interrupt capability
-- Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
-- Two fast communication controllers (FCCs) supporting the following protocols:
10-/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent
interface (MII)
Transparent
HDLC--up to T3 rates (clear channel)
One of the FCCs supports ATM (MPC8272 and MPC8271 only)--full-duplex SAR at 155
Mbps, 8-bit UTOPIA interface 31 Mphys, AAL5, AAL1, AAL2, AAL0 protocols, TM 4.0
CBR, VBR, UBR, ABR traffic types, up to 64-K external connections
-- Three serial communications controllers (SCCs) identical to those on the MPC860 supporting
the digital portions of the following protocols:
Ethernet/IEEE 802.3 CDMA/CS
HDLC/SDLC and HDLC bus
Universal asynchronous receiver transmitter (UART)
Synchronous UART
Binary synchronous (BiSync) communications
Transparent
QUICC multichannel controller (QMC) up to 64 channels
Independent transmit and receive routing, frame synchronization.
Serial-multiplexed (full-duplex) input/output 2048-, 1544-, and 1536-Kbps PCM
highways
F
r
e
e
s
c
a
l
e
S
e
m
i
c
o
n
d
u
c
t
o
r
,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
.
.
PDF 
ZIP