MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
31
REV 1
Motorola, Inc. 1995
10/95
Octal 3-State Non-Inverting
Buffer/Line Driver/
Line Receiver
HighPerformance SiliconGate CMOS
The MC54/74HC541A is identical in pinout to the LS541. The device
inputs are compatible with Standard CMOS outputs. External pullup
resistors make them compatible with LSTTL outputs.
The HC541A is an octal noninverting buffer/line driver/line receiver
designed to be used with 3state memory address drivers, clock drivers, and
other busoriented systems. This device features inputs and outputs on
opposite sides of the package and two ANDed activelow output enables.
The HC541A is similar in function to the HC540A, which has inverting
outputs.
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2 to 6V
Low Input Current: 1
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 134 FETs or 33.5 Equivalent Gates
18
Y1
2
A1
17
Y2
3
A2
16
Y3
4
A3
15
Y4
5
A4
14
Y5
6
A5
13
Y6
7
A6
12
Y7
8
A7
11
Y8
9
A8
OE1
OE2
1
19
Output
Enables
Data
Inputs
NonInverting
Outputs
PIN 20 = VCC
PIN 10 = GND
LOGIC DIAGRAM
Pinout: 20Lead Packages (Top View)
19
20
18
17
16
15
14
2
1
3
4
5
6
7
VCC
13
8
12
9
11
10
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
L
L
H
X
L
L
X
H
L
H
X
X
MC54/74HC541A
FUNCTION TABLE
Inputs
Output Y
OE1
OE2
A
L
H
Z
Z
Z = High Impedance
X = Don't Care
DW SUFFIX
SOIC PACKAGE
CASE 751D04
N SUFFIX
PLASTIC PACKAGE
CASE 73803
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW
Ceramic
Plastic
SOIC
J SUFFIX
CERAMIC PACKAGE
CASE 73203
1
20
1
20
1
20
MC54/74HC541A
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
32
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
0.5 to VCC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
20
mA
Iout
DC Output Current, per Pin
35
mA
ICC
DC Supply Current, VCC and GND Pins
75
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP
SOIC Package
750
500
mW
Tstg
Storage Temperature Range
65 to + 150
_
C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP or SOIC Package
Ceramic DIP)
260
300
_
C
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating -- Plastic DIP: 10 mW/
_
C from 65
_
to 125
_
C
Ceramic DIP: 10 mW/
_
C from 100
_
to 125
_
C
SOIC Package: 7 mW/
_
C from 65
_
to 125
_
C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, Vout
DC Input Voltage, Output Voltage (Referenced to GND)
0
VCC
V
TA
Operating Temperature Range, All Package Types
55
+ 125
_
C
tr, tf
Input Rise/Fall Time
VCC = 2.0 V
(Figure 1)
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
DC CHARACTERISTICS
(Voltages Referenced to GND)
VCC
V
Guaranteed Limit
Symbol
Parameter
Condition
VCC
V
55 to 25
C
85
C
125
C
Unit
VIH
Minimum HighLevel Input Voltage
Vout = 0.1V
|Iout|
20
A
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
VIL
Maximum LowLevel Input Voltage
Vout = VCC 0.1V
|Iout|
20
A
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
VOH
Minimum HighLevel Output
Voltage
Vin = VIL
|Iout|
20
A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIL
|Iout|
3.6mA
|Iout|
6.0mA
|Iout|
7.8mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOL
Maximum LowLevel Output
Voltage
Vin = VIH
|Iout|
20
A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH
|Iout|
3.6mA
|Iout|
6.0mA
|Iout|
7.8mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND
v
(Vin or Vout)
v
VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC54/74HC541A
HighSpeed CMOS Logic Data
DL129 -- Rev 6
33
MOTOROLA
DC CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
VCC
V
Symbol
Unit
125
C
85
C
55 to 25
C
VCC
V
Condition
Parameter
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
0.1
1.0
1.0
A
IOZ
Maximum ThreeState Leakage
Current
Output in High Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
0.5
5.0
10.0
A
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0
A
6.0
4
40
160
A
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
AC CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6 ns)
VCC
V
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to 25
C
85
C
125
C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
2.0
3.0
4.5
6.0
80
30
18
15
100
40
23
20
120
55
28
25
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
2.0
3.0
4.5
6.0
110
45
25
21
140
60
31
26
165
75
38
31
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
2.0
3.0
4.5
6.0
110
45
25
21
140
60
31
26
165
75
38
31
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
3.0
4.5
6.0
60
22
12
10
75
28
15
13
90
34
18
15
ns
Cin
Maximum Input Capacitance
10
10
10
pF
Cout
Maximum ThreeState Output Capacitance (Output in High
Impedance State)
15
15
15
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High
Speed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Buffer)*
Typical @ 25
C, VCC = 5.0 V, VEE = 0 V
pF
CPD
Power Dissipation Capacitance (Per Buffer)*
35
pF
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
Figure 1.
VCC
GND
INPUT A
OUTPUT Y
tPLH
OE1 or OE2
50%
VCC
GND
OUTPUT Y
tPZL
OUTPUT Y
tPZH
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
10%
90%
tPLZ
tPHZ
50%
50%
tPHL
90%
50%
10%
tr
tTLH
tf
tTHL
Figure 2.
SWITCHING WAVEFORMS
90%
50%
10%
50%
MC54/74HC541A
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
34
CL*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT
TEST CIRCUITS
Figure 3.
Figure 4.
CL*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT
1k
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ and tPZH.
PIN DESCRIPTIONS
INPUTS
A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8,
9) -- Data input pins. Data on these pins appear in nonin-
verted form on the corresponding Y outputs, when the out-
puts are enabled.
CONTROLS
OE1, OE2 (PINS 1, 19) -- Output enables (activelow).
When a low voltage is applied to both of these pins, the out-
puts are enabled and the device functions as an noninvert-
ing buffer. When a high voltage is applied to either input, the
outputs assume the high impedance state.
OUTPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
13, 12, 11) -- Device outputs. Depending upon the state of
the output enable pins, these outputs are either noninvert-
ing outputs or highimpedance outputs.
VCC
To 7 Other
Buffers
LOGIC DETAIL
One of Eight
Buffers
INPUT A
OE1
OE2
OUTPUT Y
MC54/74HC541A
HighSpeed CMOS Logic Data
DL129 -- Rev 6
35
MOTOROLA
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 73203
ISSUE E
N SUFFIX
PLASTIC PACKAGE
CASE 73803
ISSUE E
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D04
ISSUE E
NOTES:
1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSIONS A AND B INCLUDE MENISCUS.
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
23.88
25.15
0.940
0.990
B
6.60
7.49
0.260
0.295
C
3.81
5.08
0.150
0.200
D
0.38
0.56
0.015
0.022
F
1.40
1.65
0.055
0.065
G
2.54 BSC
0.100 BSC
H
0.51
1.27
0.020
0.050
J
0.20
0.30
0.008
0.012
K
3.18
4.06
0.125
0.160
L
7.62 BSC
0.300 BSC
M
0
15
0
15
N
0.25
1.02
0.010
0.040
_
_
_
_
A
20
1
10
11
B
F
C
SEATING
PLANE
D
H
G
K
N
J
M
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
M
L
J
20 PL
M
B
M
0.25 (0.010)
T
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
25.66
27.17
1.010
1.070
B
6.10
6.60
0.240
0.260
C
3.81
4.57
0.150
0.180
D
0.39
0.55
0.015
0.022
G
2.54 BSC
0.100 BSC
J
0.21
0.38
0.008
0.015
K
2.80
3.55
0.110
0.140
L
7.62 BSC
0.300 BSC
M
0
15
0
15
N
0.51
1.01
0.020
0.040
_
_
_
_
E
1.27
1.77
0.050
0.070
1
11
10
20
A
SEATING
PLANE
K
N
F
G
D
20 PL
T
M
A
M
0.25 (0.010)
T
E
B
C
F
1.27 BSC
0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
A
B
20
1
11
10
S
A
M
0.010 (0.25)
B
S
T
D
20X
M
B
M
0.010 (0.25)
P
10X
J
F
G
18X
K
C
T
SEATING
PLANE
M
R
X 45
_
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
12.65
12.95
0.499
0.510
B
7.40
7.60
0.292
0.299
C
2.35
2.65
0.093
0.104
D
0.35
0.49
0.014
0.019
F
0.50
0.90
0.020
0.035
G
1.27 BSC
0.050 BSC
J
0.25
0.32
0.010
0.012
K
0.10
0.25
0.004
0.009
M
0
7
0
7
P
10.05
10.55
0.395
0.415
R
0.25
0.75
0.010
0.029
_
_
_
_
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