5-1
FAST AND LS TTL DATA
8-BIT SHIFT REGISTERS
WITH SIGN EXTEND
These 8-bit shift registers have multiplexed input/output data ports to
accomplish full 8-bit data handling in a single 20-pin package. Serial data may
enter the shift-right register through either D0 or D1 inputs as selected by the
data select pin. A serial output is also provided. Synchronous parallel loading
is achieved by taking the register enable and the S / P inputs low. This places
the three-state input / output ports in the data input mode. Data is entered on
the low-to-high clock transition. The data extend function repeats the sign in
the QA flip-flop during shifting. An overriding clear input clears the internal
registers when taken low whether the outputs are enabled or off. The output
enable does not affect synchronous operation of the register.
Multiplexed Inputs / Outputs Provide Improved Bit Density
Sign Extend Function
Direct Overriding Clear
3-State Outputs Drive Bus Lines Directly
VCC
DATA
SELECT
SIGN
EXTEND D1
B/QB D/QD F/QF H/QH
Q/H CLOCK
D0
A/QA C/QC E/QE G/QG
S/P
REGISTER
ENABLE
OUTPUT
ENABLE
CLEAR GND
(TOP VIEW)
18
17
16
15
14
13
1
2
3
4
5
6
7
20
19
8
9
10
12
11
DS
SE
D1
B/QB D/QD F/QF H/GH Q/H
G
CK
S/P
D0
A/QA C/QC
E/QE G/QG OE
CLR
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
55
0
25
25
125
70
C
IOH
Output Current -- High
QH
54, 74
0.4
mA
IOL
Output Current -- Low
QH
QH
54
74
4.0
8.0
mA
IOH
Output Current -- High
QA QH
QA QH
54
74
1.0
2.6
mA
IOL
Output Current -- Low
QA QH
QA QH
54
74
12
24
mA
SN54/74LS322A
8-BIT SHIFT REGISTERS
WITH SIGN EXTEND
LOW POWER SCHOTTKY
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN
Plastic
SN74LSXXXDW SOIC
20
1
J SUFFIX
CERAMIC
CASE 732-03
20
1
N SUFFIX
PLASTIC
CASE 738-03
20
1
DW SUFFIX
SOIC
CASE 751D-03
5-2
FAST AND LS TTL DATA
SN54/74LS322A
BLOCK DIAGRAM
REGISTER
ENABLE
G
S/P
SIGN
EXTEND
SE
D1
DATA
SELECT
DS
D0
CLOCK
CLEAR
OUTPUT
ENABLE
OE
(8)
(9)
(11)
(3)
(19)
(18)
(2)
(1)
(12)
(13)
(7)
(16)
(4)
(17)
CK
D
Q
Q
CLR
CK
D
Q
Q
CLR
CK
D
Q
Q
CLR
CK
D
Q
Q
CLR
A/QA
B/QB
G/QG
H/QH
FOUR
IDENTICAL
CHANNELS
NOT
SHOWN
QH
FUNCTION TABLE
OPERATION
INPUTS
INPUTS/OUTPUTS
OUTPUT
QH
OPERATION
CLEAR
REGISTER
ENABLE
S/P
SIGN
EXTEND
DATA
SELECT
OUTPUT
ENABLE
CLOCK
A/QA B/QB C/QC H/QH
OUTPUT
QH
Clear
L
H
X
X
X
L
X
L
L
L
L
L
L
X
H
X
X
L
X
L
L
L
L
L
Hold
H
H
X
X
X
L
X
QA0
QB0
QC0
QH0
QH0
Shift Right
H
L
H
H
L
L
D0
QAn
QBn
QGn
QGn
Shift Right
H
L
H
H
H
L
D1
QAn
QBn
QGn
QGn
Sign Extend
H
L
H
L
X
L
QAn
QAn
QBn
QGn
QGn
Load
H
L
L
X
X
X
a
b
c
h
h
When the output enable is high, the eight input/output terminals are disabled to the high-impedance state; however, sequential operation or
clearing of the register is not affected. If both the register enable input and the S/P input are low while the clear input is low, the register is
cleared while the eight input/output terminals are disabled to the high-impedance state.
H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Irrelevant (any input, including transitions)
= Transition from LOW to HIGH level
QA0
...
QH0 = the level of QA through QH, respectively, before the indicated steady-state conditions were established
QAn
...
QHn = the level of QA through QH, respectively, before the most recent
transition of the clock
D0, D1 = the level of steady-state inputs at inputs D0 and D1 respectively
a
...
h = the level of steady-state inputs at inputs A through H respectively
...
5-3
FAST AND LS TTL DATA
SN54/74LS322A
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54
0.7
V
Guaranteed Input LOW Voltage for
All Inputs
VIL
Input LOW Voltage
74
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK
Input Clamp Diode Voltage
0.65
1.5
V
VCC = MIN, IIN = 18 mA
VOH
Output HIGH Voltage
QA QH
54
2.4
3.2
V
VCC = MIN, IOH = MAX
VOH
Output HIGH Voltage
QA QH
74
2.4
3.2
V
VCC = MIN, IOH = MAX
VOH
Output HIGH Voltage
QH
54
2.5
3.4
V
VCC = MIN, IOH = MAX
VOH
Output HIGH Voltage
QH
74
2.7
3.4
V
VCC = MIN, IOH = MAX
VOL
Output LOW Voltage
QA QH
54, 74
0.25
0.4
V
IOL = 12 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VOL
Output LOW Voltage
QA QH
74
0.35
0.5
V
IOL = 24 mA
VIN = VIL or VIH
per Truth Table
VOL
Output LOW Voltage
QH
54, 74
0.4
V
IOL = 4.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VOL
Output LOW Voltage
QH
74
0.5
V
IOL = 8.0 mA
VIN = VIL or VIH
per Truth Table
IOZH
Output Off Current HIGH
QA QH
40
A
VCC = MAX, VOUT = 2.7 V
IOZL
Output Off Current LOW
QA QH
400
A
VCC = MAX, VOUT = 0.4 V
IIH
Input HIGH Current
Other
20
A
VCC = MAX, VIN = 2.7 V
IIH
Input HIGH Current
A H,
Data Select
40
A
VCC = MAX, VIN = 2.7 V
IIH
Input HIGH Current
Sign Extend
60
A
IIH
Input HIGH Current
Other
0.1
mA
VCC = MAX, VIN = 7.0 V
Data Select
0.2
mA
VCC = MAX, VIN = 7.0 V
Sign Extend
0.3
mA
CC = MAX, VIN = 7.0 V
A H
0.1
mA
VCC = MAX, VIN = 5.5 V
IIL
Input LOW Current
Other
0.4
mA
VCC = MAX, VIN = 0.4 V
IIL
Input LOW Current
Data Select
0.8
mA
VCC = MAX, VIN = 0.4 V
IL
Sign Extend
1.2
mA
CC = MAX, VIN = 0.4 V
IOS
Short Circuit Current
(Note 1)
QH
20
100
mA
VCC = MAX
IOS
Short Circuit Current
(Note 1)
QA QH
30
130
mA
VCC = MAX
ICC
Power Supply Current
60
mA
VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
5-4
FAST AND LS TTL DATA
SN54/74LS322A
AC CHARACTERISTICS
(TA = 25
C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
fMAX
Maximum Clock Frequency
25
35
MHz
CL = 15 pF
tPHL
tPLH
Propagation Delay, Clock
to QH
26
22
35
33
ns
CL = 15 pF
tPHL
Propagation Delay, Clear
to QH
27
35
ns
L = 15 pF
tPHL
tPLH
Propagation Delay, Clock
to QA QH
22
16
33
25
ns
CL = 45 pF,
RL = 667
tPHL
Propagation Delay, Clear
to QA QH
22
35
ns
CL = 45 pF,
RL = 667
tPZH
tPZL
Output Enable Time
15
15
35
35
ns
tPHZ
tPLZ
Output Disable Time
15
15
25
25
ns
CL = 5.0 pF
AC SETUP REQUIREMENTS
(TA = 25
C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
tW
Clock Pulse Width HIGH
25
ns
VCC = 5.0 V
tW
Clock Pulse Width LOW
15
ns
VCC = 5.0 V
tW
Clear Pulse Width LOW
20
ns
VCC = 5.0 V
ts
Data Setup Time
20
ns
VCC = 5.0 V
ts
Select Setup Time
15
ns
VCC = 5.0 V
th
Data Hold Time
0
ns
th
Select Hold Time
10
ns
trec
Recovery Time
20
ns
DEFINITIONS OF TERMS
SETUP TIME (ts) -- is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW-to-HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) -- is defined as the minimum time following
the clock transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the correct
logic level may be released prior to the clock transition from
LOW-to-HIGH and still be recognized.
RECOVERY TIME (trec) -- is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
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