NOTES:
tn = bit time before enable
negative-going transition
tn+1 = bit time after enable
negative-going transition
5-75
FAST AND LS TTL DATA
4-BIT D LATCH
The TTL/MSI SN54/ 74LS75 and SN54/ 74LS77 are latches used as tem-
porary storage for binary information between processing units and input /out-
put or indicator units. Information present at a data (D) input is transferred to
the Q output when the Enable is HIGH and the Q output will follow the data
input as long as the Enable remains HIGH. When the Enable goes LOW, the
information (that was present at the data input at the time the transition oc-
curred) is retained at the Q output until the Enable is permitted to go HIGH.
The SN54 / 74LS75 features complementary Q and Q output from a 4-bit
latch and is available in the 16-pin packages. For higher component density
applications the SN54/ 74LS77 4-bit latch is available in the 14-pin package
with Q outputs omitted.
14
13
12
11
10
9
1
2
3
4
5
6
7
16
15
8
CONNECTION DIAGRAMS DIP (TOP VIEW)
SN54 / 74LS75
14
13
12
11
10
9
1
2
3
4
5
6
8
7
SN54 / 74LS77
Q0
Q0
Q1
Q1
E01 GND
Q2
Q2
Q3
D0
D1
E23 VCC
D2
D3
Q3
Q0
Q1
E01 GND
NC
Q2
Q3
D0
D1
E23 VCC
D2
D3
NC
PIN NAMES
LOADING (Note a)
HIGH
LOW
D1D4
E01
E23
Q1Q4
Q1Q4
Data Inputs
Enable Input Latches 0, 1
Enable Input Latches 2, 3
Latch Outputs (Note b)
Complimentary Latch Outputs (Note b)
0.5 U.L.
2.0 U.L.
2.0 U.L.
10 U.L.
10 U.L.
0.25 U.L.
1.0 U.L.
1.0 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a) 1 Unit Load (U.L.) = 40
A HIGH.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
TRUTH TABLE
(Each latch)
tn
tn + 1
D
H
L
Q
H
L
SN54/74LS75
SN54/74LS77
4-BIT D LATCH
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
ORDERING INFORMATION
SN54LSXXJ
Ceramic
SN74LSXXN
Plastic
SN74LSXXD
SOIC
16
1
D SUFFIX
SOIC
CASE 751B-03
J SUFFIX
CERAMIC
CASE 632-08
N SUFFIX
PLASTIC
CASE 646-06
14
1
14
1
14
1
D SUFFIX
SOIC
CASE 751A-02
5-76
FAST AND LS TTL DATA
SN54/74LS75
LOGIC SYMBOLS
VCC = PIN 5
GND = PIN 12
2
3
6
7
16 1 15 14 10 11 9
8
D0
D1
D2
D3
13
4
E01
E23
Q0 Q1
Q2
Q3
Q0
Q1
Q2
Q3
SN54/74LS75
VCC = PIN 4
GND = PIN 11
NC = PIN 7, 10
1
2
5
6
14
13
9
8
D0
D1
D2
D3
12
3
E01
E23
Q0
Q3
Q1
Q2
SN54/74LS77
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54
0.7
V
Guaranteed Input LOW Voltage for
All Inputs
VIL
Input LOW Voltage
74
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK
Input Clamp Diode Voltage
0.65
1.5
V
VCC = MIN, IIN = 18 mA
VOH
Output HIGH Voltage
54
2.5
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOH
Output HIGH Voltage
74
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL
Output LOW Voltage
54, 74
0.25
0.4
V
IOL = 4.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VOL
Output LOW Voltage
74
0.35
0.5
V
IOL = 8.0 mA
VIN = VIL or VIH
per Truth Table
IIH
Input HIGH Current
D Input
E Input
20
80
A
VCC = MAX, VIN = 2.7 V
IIH
Input HIGH Current
D Input
E Input
0.1
0.4
mA
VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
D Input
E Input
0.4
1.6
mA
VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current (Note 1)
20
100
mA
VCC = MAX
ICC
Power Supply Current
12
mA
VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25
C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
tPLH
tPHL
Propagation Delay, Data to Q
15
9.0
27
17
ns
VCC = 5.0 V
CL = 15 pF
tPLH
tPHL
Propagation Delay, Data to Q
12
7.0
20
15
ns
VCC = 5.0 V
CL = 15 pF
tPLH
tPHL
Propagation Delay, Enable to Q
15
14
27
25
ns
VCC = 5.0 V
CL = 15 pF
tPLH
tPHL
Propagation Delay, Enable to Q
16
7.0
30
15
ns
5-77
FAST AND LS TTL DATA
SN54/74LS77
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54
0.7
V
Guaranteed Input LOW Voltage for
All Inputs
VIL
Input LOW Voltage
74
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK
Input Clamp Diode Voltage
0.65
1.5
V
VCC = MIN, IIN = 18 mA
VOH
Output HIGH Voltage
54
2.5
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOH
Output HIGH Voltage
74
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL
Output LOW Voltage
54, 74
0.25
0.4
V
IOL = 4.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VOL
Output LOW Voltage
74
0.35
0.5
V
IOL = 8.0 mA
VIN = VIL or VIH
per Truth Table
IIH
Input HIGH Current
D Input
E Input
20
80
A
VCC = MAX, VIN = 2.7 V
IIH
Input HIGH Current
D Input
E Input
0.1
0.4
mA
VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
D Input
E Input
0.4
1.6
mA
VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current (Note 1)
20
100
mA
VCC = MAX
ICC
Power Supply Current
13
mA
VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25
C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
tPLH
tPHL
Propagation Delay, Data to Q
11
9.0
19
17
ns
VCC = 5.0 V
CL = 15 pF
tPLH
tPHL
Propagation Delay, Enable to Q
10
10
18
18
ns
VCC = 5.0 V
CL = 15 pF
5-78
FAST AND LS TTL DATA
SN54/74LS75
D
SN54/74LS77
LOGIC DIAGRAM
DATA
ENABLE
TO OTHER LATCH
Q (SN54/74LS75 ONLY)
Q
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
55
0
25
25
125
70
C
IOH
Output Current -- High
54, 74
0.4
mA
IOL
Output Current -- Low
54
74
4.0
8.0
mA
AC SETUP REQUIREMENTS
(TA = 25
C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
tW
Enable Pulse Width High
20
ns
VCC = 5.0 V
ts
Setup Time
20
ns
VCC = 5.0 V
th
Hold Time
0
ns
CC = 5.0 V
AC WAVEFORMS
D
E
Q
Q
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
th
ts
tPLH
tPLH
tPHL
tPHL
tPLH
tPHL
tPHL
tPLH
DEFINITION OF TERMS
SETUP TIME (ts) -- is defined as the minimum time required for the correct logic level to be present at the logic input prior to the
clock transition from HIGH-to-LOW in order to be recognized and transferred to the outputs.
HOLD TIME (th) -- is defined as the minimum time following the clock transition from HIGH-to-LOW that the logic level must be
maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may
be released prior to the clock transition from HIGH-to-LOW and still be recognized.
PDF 
ZIP