DSP56852/D

Rev. 3.0 3/2003

DSP56852

Preliminary Technical Data

DSP56852 16-bit Digital Signal Processor

· 120 MIPS at 120MHz

· 6K x 16-bit Program SRAM

· 4K x 16-bit Data SRAM

· 1K x 16-bit Boot ROM

· 21 External Memory Address lines, 16 data lines

and four chip selects

· One (1) Serial Port Interface (SPI) or one (1)

Improved Synchronous Serial Interface (ISSI)

· One (1) Serial Communication Interface (SCI)

· Interrupt Controller

· General Purpose 16-bit Quad Timer

· JTAG/Enhanced On-Chip Emulation (OnCETM) for

unobtrusive, real-time debugging

· Computer Operating Properly (COP)/Watchdog

Timer

· 81-pin MAPBGA package

· Up to 11 GPIO

Figure 1. DSP56852 Block Diagram

JTAG/

Enhanced

OnCE

Program Controller

and

Hardware Looping Unit

Data ALU

16 x 16 + 36

36-Bit MAC

Three 16-bit Input Registers

Four 36-bit Accumulators

Address

Generation Unit

Bit

Manipulation

Unit

PLL

Clock

Generator

16-Bit

DSP56800E Core

XTAL

EXTAL

Interrupt

Controller

COP/

Watch-

dog

1 Quad

Timer

or A17,

A18

CLKO

muxed (A20)

External Address

Bus Switch

External Bus

Interface Unit

RESET

IRQA

IRQB

SSIO

DDA

SSA

External Data

Bus Switch

Bus Control

WR Enable

RD Enable

CS[2:0] muxed (GPIOA)

A0-16

MODE

D0-D12[12:0]

Program Memory

6144 x 16 SRAM

Boot ROM

1024 x 16 ROM

Data Memory

4096 x 16 SRAM

PDB

XAB1

XAB2

XDB2

CDBR

SSI or
SPI or

GPIOC

SCI or

GPIOE

IPBus Bridge (IPBB)

muxed (D13-15)

A17-18 muxed (timer pins)

A19 muxed (CS3)

D13-15 muxed (Mode A,B,C)

DDIO

Integration

Module

System

P
O
R

O
S
C

Decoding
Peripherals

Peripheral

Address

Decoder

Peripheral

Device

Selects

System

Address

Decoder

RW
Control

IPAB

IPWDB

IPRDB

System

Device

System

Bus

Control

R/W Control

Memory

PAB

CDBW

CDBR

CDBW

Clock

resets

DSP56852 Preliminary Technical Data

MOTOROLA

Part 1 Overview

1.1 DSP56852 Features

1.1.1

Digital Signal Processing Core

Efficient 16-bit DSP engine with dual Harvard architecture

120 Million Instructions Per Second (MIPS) at 120MHz core frequency

Single-cycle 16

× 16-bit parallel Multiplier-Accumulator (MAC)

Four (4) 36-bit accumulators including extension bits

16-bit bidirectional shifter

Parallel instruction set with unique DSP addressing modes

Hardware DO and REP loops

Three (3) internal address buses and one (1) external address bus

Four (4) internal data buses and one (1) external data bus

Instruction set supports both DSP and controller functions

Four (4) hardware interrupt levels

Five (5) software interrupt levels

Controller-style addressing modes and instructions for compact code

Efficient C Compiler and local variable support

Software subroutine and interrupt stack with depth limited only by memory

JTAG/Enhanced OnCE debug programming interface

1.1.2

Memory

Harvard architecture permits as many as three simultaneous accesses to program and data memory

On-chip memory includes:

-- 6K

× 16-bit Program SRAM

-- 4K

× 16-bit Data SRAM

-- 1K

× 16-bit Boot ROM

21 External Memory Address lines, 16 data lines and four (4) programmable chip select signals

1.1.3

Peripheral Circuits for DSP56852

General Purpose 16-bit Quad Timer with two external pins*

One (1) Serial Communication Interface (SCI)*

One (1) Serial Port Interface (SPI) or one (1) Improved Synchronous Serial Interface (ISSI)
module*

Interrupt Controller

Computer Operating Properly (COP)/Watchdog Timer

JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging

DSP56852 Description

MOTOROLA

DSP56852 Preliminary Technical Data

81-pin MAPBGA package

Up to 11 GPIO

* Each peripheral I/O can be used alternately as a General Purpose I/O if not needed

1.1.4

Energy Information

Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs

Wait and Stop modes available

1.2 DSP56852 Description

The DSP56852 is a member of the DSP56800E core-based family of Digital Signal Processors (DSPs). On
a single chip it combines the processing power of a DSP and the functionality of a microcontroller with a
flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the DSP56852 is well-suited for many applications.
The DSP56852 includes many peripherals especially useful for low-end Internet appliance applications
and low-end client applications such as telephony; portable devices; Internet audio; and point-of-sale
systems such as noise suppression; ID tag readers; sonic/subsonic detectors; security access devices;
remote metering; and sonic alarms.

The DSP56800E core is based on a Harvard-style architecture consisting of three execution units operating
in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C-Compilers, enabling rapid
development of optimized control applications.

The DSP56852 supports program execution from either internal or external memories. Two data operands
can be accessed from the on-chip Data RAM per instruction cycle. The DSP56852 also provides two
external dedicated interrupt lines, and up to 11 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.

The DSP56852 DSP controller includes 6K words of Program RAM, 4K words of Data RAM and 1K of
Boot RAM. It also supports program execution from external memory.

This DSP controller also provides a full set of standard programmable peripherals that include one improved
Synchronous Serial Interface (SSI) or one Serial Peripheral Interface (SPI), one Serial Communications
Interface (SCI), and one Quad Timer. The SSI, SPI, SCI I/O and three chip selects can be used as General
Purpose Input/Outputs when its primary function is not required. The SSI and SPI share I/O, so, at most,
one of these two peripherals can be in use at any time.

1.3 "Best in Class" Development Environment

The SDK (Software Development Kit) provides fully debugged peripheral drivers, libraries and interfaces
that allow a programmer to create his own unique C application code independent of component
architecture. The CodeWarrior Integrated Development Environment is a sophisticated tool for code
navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development
system cards support concurrent engineering. Together, the SDK, CodeWarrior, and EVMs create a
complete, scalable tools solution for easy, fast and efficient development.

DSP56852 Preliminary Technical Data

MOTOROLA

1.4 Product Documentation

The four documents listed in

Table 1

are required for a complete description of and proper design with the

DSP56852. Documentation is available from local Motorola distributors, Motorola semiconductor sales
offices, Motorola Literature Distribution Centers, or online at www.motorola.com/semiconductors/.

Table 1. DSP56852 Chip Documentation

1.5 Data Sheet Conventions

This data sheet uses the following conventions:

Topic

Description

Order Number

DSP56800E
Reference Manual

Detailed description of the DSP56800E architecture,
16-bit DSP core processor and the instruction set

DSP56800ERM/D

DSP56852
User's Manual

Detailed description of memory, peripherals, and
interfaces of the DSP56852

DSP56852UM/D

DSP56852
Technical Data Sheet

Electrical and timing specifications, pin descriptions,
and package descriptions (this document)

DSP56852/D

DSP56852
Product Brief

Summary description and block diagram of the
DSP56852 core, memory, peripherals and interfaces

DSP56852PB/D

OVERBAR

This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.

"asserted"

A high true (active high) signal is high or a low true (active low) signal is low.

"deasserted"

A high true (active high) signal is low or a low true (active low) signal is high.

Examples:

Signal/Symbol

Logic State

Signal State

Voltage

Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

True

Asserted

False

Deasserted

True

Asserted

False

Deasserted

Introduction

MOTOROLA

DSP56852 Preliminary Technical Data

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the DSP56852 are organized into functional groups, as shown in

Table 2

and as illustrated in

Figure 2

. In

Table 3

each table row describes the package pin and the signal or signals

present.

1. V

= V

DD CORE,

= V

SS CORE,

DDIO

= V

DD IO,

SSIO

= V

SS IO,

DDA

= V

DD ANA,

SSA

= V

SS ANA

2. CLKOUT is muxed Address pin A20.

3. Four Address pins are multiplexed with the timer, CS3 and CLKOUT pins.

4. CS3 is multiplexed with external Address Bus pin A19.

5. Mode pins are multiplexed with External Data pins D13-D15 like A17and A18.

6. Four of these pins are multiplexed with SSI.

7. Two of these pins are multiplexed with 2 bits of the External Address Bus A17and A18.

Table 2. Functional Group Pin Allocations

Functional Group

Number of Pins

Power (V

DD,

DDIO, or

DDA

)

Ground (V

SS,

SSIO,

or V

SSA

)

Phase Lock Loop (PLL) and Clock

External Bus Signals

External Chip Select*

Interrupt and Program Control

Synchronous Serial Interface (SSI) Port*

Serial Communications Interface (SCI) Port*

Serial Peripheral Interface (SPI) Port

Quad Timer Module Port

JTAG/Enhanced On-Chip Emulation (EOnCE)

*Alternately, GPIO pins

DSP56852 Preliminary Technical Data

MOTOROLA

Figure 2. DSP56852 Signals Identified by Functional Group

1. Specifically for PLL, OSC, and POR.

2. Alternate pin functions are shown in parentheses.

DSP56852

Logic

Power

I/O

Power

SCI

Reset

JTAG/Enhanced
OnCE

VDD

VSS

VDDIO

VSSIO

VDDA

VSSA

A016

A17(TI/O)

A18(TI/O)

A19(CS3)

CLKO(A20)

GPIOA0(CS0)

GPIOA1(CS1)

GPIOA2(CS2)

D0-D12

D13-D15/MODEA-C

Bus

Control

RXD(GPIOE0)

TXD(GPIOE1)

GPIOC0(STXD)

GPIOC1(SRXD)

SCLK(GPIOC2)(STCK)

SS(GPIOC3)(STFS)

MISO(GPIOC4)(SRCK)

MOSI(GPIOC5)(SRFS)

IRQA

IRQB

XTAL

EXTAL

RESET

TCK

TDI

TDO

TMS

TRST

SSI

SPI

Chip

Select

Address

Bus

Analog

Power

Interrupt
Request

Oscillator

Data

Bus

Introduction

MOTOROLA

DSP56852 Preliminary Technical Data

Part 3 Signals and Package Information

All digital inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are
enabled by default. Exceptions:

1. When a pin has GPIO functionality, the pull-up may be disabled under software control.

2. Mode pins D13, D14 and D15 have no pull-up.

3. TCK has a weak pull-down circuit always active.

4. Bidirectional I/O pullups automatically disable when the output is enabled.

This table is presented consistently with the Signals Identified by Functional Group figure.

1. BOLD entries in the Type column represents the state of the pin just out of reset.

2. Ouput(Z) means an output in a High-Z condition.

Table 3. DSP56852 Signal and Package Information for the 81-pin MAPBGA

Pin No.

Signal Name

Type

Description

Logic Power --These pins provide power to the internal
structures of the chip, and should all be attached to V

DD.

Logic Power - GND--These pins provide grounding for the
internal structures of the chip and should all be attached to
V

SS.

DDIO

I/O Power --These pins provide power for all I/O and ESD
structures of the chip, and should all be attached to V

DDIO.

DDIO

SSIO

I/O Power - GND--These pins provide grounding for all I/O
and ESD structures of the chip and should all be attached to
V

SS.

SSIO

DDA

Analog Power--These pins supply an analog power source

SSA

Analog Ground--This pin supplies an analog ground.

DSP56852 Preliminary Technical Data

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Output(Z)

Address Bus (A0A16)--These pins specify a word
address for external program or data memory addresses.

A10

A11

A12

A13

A14

A15

A16

A17

TIO0

Output(Z)

Input/Output

Address Bus (A17)

Timer I/O (0)--Can be programmed as either a timer input
source or as a timer output flag.

A18

TIO1

Output(Z)

Input/Output

Address Bus (A18)

Timer I/O (1)--Can be programmed as either a timer input
source or as a timer output flag.

A19

CS3

Output(Z)

Output

Address Bus (A19)

External Chip Select 3 --When enabled, a CSx signal is
asserted for external memory accesses that fall within a
programmable address range.

CLKO

A20

Output

Output

Output clock (CLKO)--User programmable clock out
reference

Address Bus--A20

CS0

GPIOA0

Output

Input/Output

Chip Select 0 (CS0) --When enabled, a CSx signal is
asserted for external memory accesses that fall within a
programmable address range.

Port A GPIO (0) --A general purpose IO pin.

Table 3. DSP56852 Signal and Package Information for the 81-pin MAPBGA

Pin No.

Signal Name

Type

Description

Introduction

MOTOROLA

DSP56852 Preliminary Technical Data

CS1

GPIOA1

Output

Input/Output

Chip Select 1 (CS1) --When enabled, a CSx signal is
asserted for external memory accesses that fall within a
programmable address range.

Port A GPIO (1) --A general purpose IO pin.

CS2

GPIOA2

Output

Input/Output

Chip Select 2 (CS2)--When enabled, a CSx signal is
asserted for external memory accesses that fall within a
programmable address range.

Port A GPIO (2) --A general purpose IO pin.

Input/Output

Data Bus (D0D12) --specify the data for external program or
data memory accesses. D0D15 are tri-stated when the
external bus is inactive.

D10

D11

D12

D13

MODE A

Input/Output

Data Bus (D13D15) -- specify the data for external program
or data memory accesses. D0D15 are tri-stated when the
external bus is inactive.

Mode Select--During the bootstrap process the MODE A,
MODE B, and MODE C pins select one of the eight
bootstrap modes. These pins are sampled at the end of
reset.

Note: Any time POR and EXTERNAL resets are active, the
state of MODE A, B and C pins get asynchronously
transferred to the SIM Control Register [14:12] ($1FFF08)
respectively. These bits determine the mode in which the
part will boot up.

Note: Software and COP resets do not update the SIM
Control Register.

D14

MODE B

D15

MODE C

Output

Bus Control Read Enable (RD)--is asserted during
external memory read cycles. When RD is asserted low,
pins D0D15 become inputs and an external device is
enabled onto the DSP data bus. When RD is deasserted
high, the external data is latched inside the DSP. RD can be
connected directly to the OE pin of a Static RAM or ROM.

Table 3. DSP56852 Signal and Package Information for the 81-pin MAPBGA

Pin No.

Signal Name

Type

Description

DSP56852 Preliminary Technical Data

MOTOROLA

Output

Bus ControlWrite Enable (WR)-- is asserted during
external memory write cycles. When WR is asserted low,
pins D0D15 become outputs and the DSP puts data on the
bus. When WR is deasserted high, the external data is
latched inside the external device. When WR is asserted, it
qualifies the A0A15 pins. WR can be connected directly to
the WE pin of a Static RAM.

RXD

GPIOE0

Input

Input/Output

SCI Receive Data (RXD)--This input receives byte-
oriented serial data and transfers it to the SCI receive shift
register.

Port E GPIO (0)--A general purpose I/O pin.

TXD

GPIOE1

Output(Z)

Input/Output

SCI Transmit Data (TXD)--This signal transmits data from
the SCI transmit data register.

Port E GPIO (1)--A general purpose I/O pin.

GPIOC0

STXD

Input/Output

Output

Port C GPIO (0)--This pin is a General Purpose I/O (GPIO)
pin when the SSI is not in use.

SSI Transmit Data (STXD)--This output pin transmits serial
data from the SSI Transmitter Shift Register.

GPIOC1

SRXD

Input/Output

Input

Port C GPIO (1)--This pin is a General Purpose I/O (GPIO)
pin when the SSI is not in use.

SSI Receive Data (SRXD)--This input pin receives serial
data and transfers the data to the SSI Receive Shift
Register.

SCLK

GPIOC2

STCK

Input/Output

Input/Output

SPI Serial Clock (SCLK)--In Master mode, this pin serves
as an output, clocking slaved listeners. In Slave mode, this
pin serves as the data clock input.

Port C GPIO (2)--This pin is a General Purpose I/O (GPIO)
pin that can individually be programmed as input or output
pin.

SSI Serial Transfer Clock (STCK)--This bidirectional pin
provides the serial bit rate clock for the transmit section of
the SSI. The clock signal can be continuous or gated.

GPIOC3

STFS

Input

Input/Output

SPI Slave Select (SS)--In Master mode, this pin is used to
arbitrate multiple masters. In Slave mode, this pin is used to
select the slave.

Port C GPIO (3)--This pin is a General Purpose I/O (GPIO)
pin that can individually be programmed as input or output
pin.

SSI Serial Transfer Frame Sync (STFS) --This
bidirectional pin is used to count the number of words in a
frame while transmitting. A programmable frame rate divider
and a word length divider are used for frame rate sync signal
generation.

Table 3. DSP56852 Signal and Package Information for the 81-pin MAPBGA

Pin No.

Signal Name

Type

Description

Introduction

MOTOROLA

DSP56852 Preliminary Technical Data

MISO

GPIOC4

SRCK

Input/Output

Input/Output

SPI Master In/Slave Out (MISO)--This serial data pin is an
input to a master device and an output from a slave device.
The MISO line of a slave device is placed in the high-
impedance state if the slave device is not selected.

Port C GPIO (4)--This pin is a General Purpose I/O (GPIO)
pin that can individually be programmed as input or output
pin.

SSI Serial Receive Clock (SRCK)--This bidirectional pin
provides the serial bit rate clock for the receive section of the
SSI. The clock signal can be continuous or gated.

MOSI

GPIOC5

SRFS

Input/

Output (Z)

Input/Output

SPI Master Out/Slave In (MOSI)--This serial data pin is an
output from a master device and an input to a slave device.
The master device places data on the MOSI line a half-cycle
before the clock edge that the slave device uses to latch the
data.

Port C GPIO (5)--This pin is a General Purpose I/O (GPIO)
pin that can individually be programmed as input or output
pin.

SSI Serial Receive Frame Sync (SRFS)-- This
bidirectional pin is used to count the number of words in a
frame while receiving. A programmable frame rate divider
and a word length divider are used for frame rate sync signal
generation.

IRQA

Input

External Interrupt Request A (IRQA)--The IRQA Schmitt
trigger input is a synchronized external interrupt request that
indicates that an external device is requesting service. It can
be programmed to be level-sensitive or negative-edge-
triggered.

IRQB

Input

External Interrupt Request B (IRQB)--The IRQB Schmitt
trigger input is an external interrupt request that indicates
that an external device is requesting service. It can be
programmed to be level-sensitive or negative-edge-
triggered.

EXTAL

Input

External Crystal Oscillator Input (EXTAL)--This input
should be connected to an external crystal. If an external
clock source other than a crystal oscillator is used, EXTAL
must be tied off.

XTAL

Input/Output

Crystal Oscillator Output (XTAL)--This output connects
the internal crystal oscillator output to an external crystal. If
an external clock source other than a crystal oscillator is
used, XTAL must be used as the input.

Table 3. DSP56852 Signal and Package Information for the 81-pin MAPBGA

Pin No.

Signal Name

Type

Description

DSP56852 Preliminary Technical Data

MOTOROLA

RESET

Input

Reset (RESET)--This input is a direct hardware reset on the
processor. When RESET is asserted low, the DSP is
initialized and placed in the Reset state. A Schmitt trigger
input is used for noise immunity. When the RESET pin is
deasserted, the initial Chip Operating mode is latched from
the D[15:13] pins. The internal reset signal will be
deasserted synchronous with the internal clocks, after a
fixed number of internal clocks.

To ensure complete hardware reset, RESET and TRST
should be asserted together. The only exception occurs in a
debugging environment when a hardware DSP reset is
required and it is necessary not to reset the JTAG/Enhanced
OnCE module. In this case, assert RESET, but do not assert
TRST.

TCK

Input

Test Clock Input (TCK)--This input pin provides a gated
clock to synchronize the test logic and shift serial data to the
JTAG/Enhanced OnCE port. The pin is connected internally
to a pull-down resistor.

TDI

Input

Test Data Input (TDI)--This input pin provides a serial input
data stream to the JTAG/Enhanced OnCE port. It is sampled
on the rising edge of TCK and has an on-chip pull-up
resistor.

TDO

Output

Test Data Output (TDO)--This tri-statable output pin
provides a serial output data stream from the JTAG/
Enhanced OnCE port. It is driven in the Shift-IR and Shift-
DR controller states, and changes on the falling edge of
TCK.

TMS

Input

Test Mode Select Input (TMS)--This input pin is used to
sequence the JTAG TAP controller's state machine. It is
sampled on the rising edge of TCK and has an on-chip pull-
up resistor.

TRST

Input

Test Reset (TRST)--As an input, a low signal on this pin
provides a reset signal to the JTAG TAP controller. To
ensure complete hardware reset, TRST should be asserted
whenever RESET is asserted. The only exception occurs in
a debugging environment, since the Enhanced OnCE/JTAG
module is under the control of the debugger. In this case it is
not necessary to assert TRST when asserting RESET .
Outside of a debugging environment RESET should be
permanently asserted by grounding the signal, thus
disabling the Enhanced OnCE/JTAG module on the DSP.

Input/Output

Debug Even (DE)-- is an open-drain, bidirectional, active
low signal. As an input, it is a means of entering Debug
mode of operation from an external command controller. As
an output, it is a means of acknowledging that the chip has
entered Debug mode.

Table 3. DSP56852 Signal and Package Information for the 81-pin MAPBGA

Pin No.

Signal Name

Type

Description

General Characteristics

MOTOROLA

DSP56852 Preliminary Technical Data

Part 4 Specifications

4.1 General Characteristics

The DSP56852 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs.
The term "5-volt tolerant" refers to the capability of an I/O pin, built on a 3.3V compatible process
technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture
of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V-
compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V
±10% during normal operation without causing damage). This 5V-tolerant capability therefore offers the
power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged.

Absolute maximum ratings given in

Table 4

are stress ratings only, and functional operation at the

maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.

The DSP56852 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.

CAUTION

This device contains protective circuitry to guard
against damage due to high static voltage or
electrical fields. However, normal precautions are
advised to avoid application of any voltages higher
than maximum rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate voltage level.

Table 4. Absolute Maximum Ratings

Characteristic

Symbol

Min

Max

Unit

Supply voltage, core

must not exceed V

DDIO

0.3

+ 2.0

Supply voltage, IO
Supply voltage, analog

DDIO

and V

DDA

must not differ by more that 0.5V

SSIO

0.3

SSA

0.3

SSIO

+ 4.0

DDA

+ 4.0

Digital input voltages
Analog input voltages (XTAL, EXTAL)

INA

SSIO

0.3

SSA

0.3

SSIO

+ 5.5

DDA

+ 0.3

Current drain per pin excluding V

, V

SS,

DDA

SSA,

DDIO

, V

SSIO

Junction temperature

-40

120

°C

Storage temperature range

STG

-55

150

°C

DSP56852 Preliminary Technical Data

MOTOROLA

4.2 DC Electrical Characteristics

Table 5. Recommended Operating Conditions

Characteristic

Symbol

Min

Max

Unit

Supply voltage for Logic Power

1.62

1.98

Supply voltage for I/O Power

DDIO

3.0

3.6

Supply voltage for Analog Power

DDA

3.0

3.6

Ambient operating temperature

-40

°C

PLL clock frequency

Assumes clock source is direct clock to EXTAL or crystal oscillator running 2-4MHz PLL must be enabled, locked, and

selected. The actual frequency depends on the source clock frequency and programming of the CGM module.

pll

240

MHz

Operating Frequency

Master clock is derived from one of the following four sources:

clk

= f

xtal

when the source clock is the direct clock to EXAL

clk

= f

pll

when PLL is selected

clk

= f

osc

when the source clock is the crystal oscillator and PLL is not selected

clk

= f

extal

when the source clock is the direct clock to EXAL and PLL is not selected

120

MHz

Frequency of peripheral bus

ipb

MHz

Frequency of external clock

clk

240

MHz

Frequency of oscillator

osc

MHz

Frequency of clock via XTAL

xtal

240

MHz

Frequency of clock via EXTAL

extal

MHz

Table 6. Thermal Characteristics

See

Section 6.1

for more detail.

Characteristic

81-pin MAPBGA

Symbol

Value

Unit

Thermal resistance junction-to-ambient
(estimated)

36.9

°C/W

I/O pin power dissipation

I/O

User Determined

Power dissipation

= (I

) + P

I/O

Maximum allowed P

DMAX

) /

Table 7. DC Electrical Characteristics

Operating Conditions: V

= V

SSIO

= V

SSA

= 0V, V

= 1.62-1.98V, V

DDIO

= V

DDA

= 3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

Characteristic

Symbol

Min

Typ

Max

Unit

Input high voltage (XTAL/EXTAL)

IHC

DDA

0.8

DDA

+ 0.3

DC Electrical Characteristics

MOTOROLA

DSP56852 Preliminary Technical Data

Input low voltage (XTAL/EXTAL)

ILC

-0.3

0.5

Input high voltage

2.0

5.5

Input low voltage

-0.3

0.8

Input current low (pullups disabled)

-1

Input current high (pullups disabled)

-1

Output tri-state current low

OZL

-10

Output tri-state current high

OZH

-10

Output High Voltage at I

DDIO

0.7

Output Low Voltage at I

0.4

Output High Current at V

Output Low Current at V

Input capacitance

Output capacitance

OUT

supply current @ nominal voltage and 25

Run

Deep Stop

Light Stop

--
--
--

70
30

2.6

--
--
--

DDIO

supply current @ nominal voltage and 25

Run

DDIO

DDA

supply current @ nominal voltage and 25

Deep Stop

DDA

Low Voltage Interrupt

2.5

2.85

Low Voltage Interrupt Recovery Hysteresis

EIH

Power on Reset

POR

1.5

2.0

Run (operating) I

measured using external square wave clock source (f

osc

= 4MHz) into XTAL. All inputs 0.2V from

rail; no DC loads; outputs unloaded. All ports configured as inputs; measured with all modules enabled. PLL set to 240MHz
out. Running Core, performing 50% NOP and 50% FIR. Clock at 120 MHz.

Deep Stop Mode - Operation frequency = 4 MHz, PLL set to 4 MHz, crystal oscillator and time of day module operating.

Light Stop Mode - Operation frequency = 120 MHz, PLL set to 240 MHz, crystal oscillator and time of day module oper-

ating.

includes current for core logic, internal memories, and all internal peripheral logic circuitry.

Running core and performing external memory access. Clock at 120 MHz.

When V

drops below V

max value, an interrupt is generated.

Power-on reset occurs whenever the digital supply drops below 1.8V. While power is ramping up, this signal remains

active as long as the internal 2.5V is below 1.8V, no matter how long the ramp up rate is. The internally regulated voltage is
typically 100mV less than V

during ramp up until 2.5V is reached, at which time it self-regulates.

Table 7. DC Electrical Characteristics (Continued)

Operating Conditions: V

= V

SSIO

= V

SSA

= 0V, V

= 1.62-1.98V, V

DDIO

= V

DDA

= 3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

Characteristic

Symbol

Min

Typ

Max

Unit

DSP56852 Preliminary Technical Data

MOTOROLA

4.3 Supply Voltage Sequencing and Separation Cautions

Figure 3

shows two situations to avoid in sequencing the V

and V

DDIO,

DDA

supplies.

Notes: 1. V

rising before V

DDIO

, V

DDA

2. V

DDIO

, V

DDA

rising much faster than V

Figure 3. Supply Voltage Sequencing and Separation Cautions

should not be allowed to rise early (1). This is usually avoided by running the regulator for the V

supply (1.8V) from the voltage generated by the 3.3V V

DDIO

supply, see

Figure 4

. This keeps V

from

rising faster than V

DDIO

should not rise so late that a large voltage difference is allowed between the two supplies (2). Typically

this situation is avoided by using external discrete diodes in series between supplies, as shown in

Figure 4

The series diodes forward bias when the difference between V

DDIO

and V

reaches approximately 2.1,

causing V

to rise as V

DDIO

ramps up. When the V

regulator begins proper operation, the difference

between supplies will typically be 0.8V and conduction through the diode chain reduces to essentially
leakage current. During supply sequencing, the following general relationship should be adhered to:
V

DDIO

> V

> (V

DDIO

- 2.1V)

In practice, V

DDA

is typically connected directly to V

DDIO

with some filtering.

Figure 4. Example Circuit to Control Supply Sequencing

3.3V

1.8V

Time

Supplies Stable

DDIO,

DDA

DC Power

Supp

ly V

l
t
a
ge

3.3V

Regulator

1.8V

Regulator

Supply

DDIO,

DDA

AC Electrical Characteristics

MOTOROLA

DSP56852 Preliminary Technical Data

4.4 AC Electrical Characteristics

Timing waveforms in

Section 4.2

are tested with a V

maximum of 0.8V and a V

minimum of 2.0V for

all pins except XTAL, which is tested using the input levels in

Section 4.2

. In

Figure 5

the levels of V

and V

for an input signal are shown.

Figure 5. Input Signal Measurement References

Figure 6

shows the definitions of the following signal states:

Active state, when a bus or signal is driven, and enters a low impedance state

Tri-stated, when a bus or signal is placed in a high impedance state

Data Valid state, when a signal level has reached V

or V

Data Invalid state, when a signal level is in transition between V

and V

Figure 6. Signal States

4.5 External Clock Operation

The DSP56852 system clock can be derived from a crystal or an external system clock signal. To generate
a reference frequency using the internal oscillator, a reference crystal must be connected between the
EXTAL and XTAL pins.

4.5.1

Crystal Oscillator for use with PLL

The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency
range specified for the external crystal in

Table 9

. In

Figure 7

a typical crystal oscillator circuit is shown.

Follow the crystal supplier's recommendations when selecting a crystal, because crystal parameters
determine the component values required to provide maximum stability and reliable start-up. The crystal
and associated components should be mounted as close as possible to the EXTAL and XTAL pins to
minimize output distortion and start-up stabilization time.

Fall Time

Input Signal

Note: The midpoint is V

+ (V

)/2.

Midpoint1

Low

High

90%

50%

10%

Rise Time

Data Invalid State

Data1

Data2 Valid

Data

Tri-stated

Data3 Valid

Data2

Data3

Data1 Valid

Data Active

DSP56852 Preliminary Technical Data

MOTOROLA

Figure 7. Crystal Oscillator

4.5.2

High Speed External Clock Source (> 4MHz)

The recommended method of connecting an external clock is given in

Figure 8

. The external clock source

is connected to XTAL and the EXTAL pin is held at ground, V

DDA

, or V

DDA

/2. The TOD_SEL bit in

CGM must be set to 0.

Figure 8. Connecting a High Speed External Clock Signal using XTAL

4.5.3

Low Speed External Clock Source (2-4MHz)

The recommended method of connecting an external clock is given in

Figure 9

. The external clock source

is connected to XTAL and the EXTAL pin is held at V

DDA

/2. The TOD_SEL bit in CGM must be set to 0.

Figure 9. Connecting a Low Speed External Clock Signal using XTAL

Sample External Crystal Parameters:
R

= 10M

TOD_SEL bit in CGM must be set to 0

Crystal Frequency = 24MHz (optimized for 4MHz)

EXTAL XTAL

DSP56852

XTAL

EXTAL

External

GND,

DDA

Clock

(up to 240MHz)

or V

DDA

DSP56852

XTAL

EXTAL

External

Clock

(2-4MHz)

DDA

External Clock Operation

MOTOROLA

DSP56852 Preliminary Technical Data

Figure 10. External Clock Timing

Table 8. External Clock Operation Timing Requirements

Operating Conditions: V

= V

SSIO

= V

SSA

= 0V, V

= 1.62-1.98V, V

DDIO

= V

DDA

= 3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

Characteristic

Symbol

Min

Typ

Max

Unit

Frequency of operation (external clock driver)

See

Figure 8

for details on using the recommended connection of an external clock driver.

osc

240

MHz

Clock Pulse Width

6.25

External clock input rise time

External clock input rise time is measured from 10 to 90 percent.

rise

TBD

External clock input fall time

External clock input fall time is measured from 90 to 10percent.

Parameters listed are guaranteed by design.

fall

TBD

Table 9. PLL Timing

Operating Conditions: V

= V

SSIO

= V

SSA

= 0V, V

= 1.62-1.98V, V

DDIO

= V

DDA

= 3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

Characteristic

Symbol

Min

Typ

Max

Unit

External reference crystal frequency for the PLL

An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.

The PLL is optimized for 4MHz input crystal.

osc

MHz

PLL output frequency

clk

240

MHz

PLL stabilization time

This is the minimum time required after the PLL setup is changed to ensure reliable operation.

plls

External

Clock

Note: The midpoint is V

+ (V

)/2.

90%

50%

10%

90%

50%

10%

fall

rise

DSP56852 Preliminary Technical Data

MOTOROLA

4.6 External Memory InterfaceTiming

The External Memory Interface is designed to access static memory and peripheral devices.

Figure 11

shows sample timing and parameters that are detailed in

Table 10

The timing of each parameter consists of both a fixed delay portion and a clock related portion; as well as
user controlled wait states. The equation:

t = D + P * (M + W)

should be used to determine the actual time of each parameter. The terms in the above equation are
defined as:

parameter delay time

fixed portion of the delay, due to on-chip path delays.

the period of the system clock, which determines the execution rate of the part (i.e. when the
device is operating at 120 MHz, P = 8.33 ns).

M Fixed portion of a clock period inherent in the design. This number is adjusted to account for

possible clock duty cycle derating.

W the sum of the applicable wait state controls. See the "Wait State Controls" column of

Table 10

for the applicable controls for each parameter. See the EMI chapter of the 83x

Peripheral Manual for details of what each wait state field controls.

Some of the parameters contain two sets of numbers. These parameters have two different paths and clock
edges that must be considered. Check both sets of numbers and use the smaller result. The appropriate
entry may change if the operating frequency of the part changes.

The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters
contain two sets of numbers to account for this difference. The "Wait States Configuration" column of

Table 10

should be used to make the appropriate selection.

Figure 11. External Memory Interface Timing

DRD

RDD

DOH

DOS

DWR

RDWR

WAC

WRRD

AWR

WRWR

ARDD

RDA

RDRD

ARDA

Data Out

Data In

A0-Axx,CS

D0-D15

Note: During read-modify-write instructions and internal instructions, the address lines do not change state.

External Memory InterfaceTiming

MOTOROLA

DSP56852 Preliminary Technical Data

Table 10. External Memory Interface Timing

Operating Conditions: V

= V

SSIO

= V

SSA

= 0 V, V

= 1.62-1.98 V, V

DDIO

= V

DDA

3.03.6V, T

= 40

° to +120°C, C

50pF, P = 8.333ns

Characteristic

Symbol

Wait States

Configuration

Wait States

Controls

Unit

Address Valid to WR Asserted

AWR

WWS=0 -0.75

0.50

WWSS

WWS>0

-1.50

0.69

WR Width Asserted to WR
Deasserted

WWS=0 -0.52

0.19

WWS

WWS>0

-0.13

0.00

Data Out Valid to WR Asserted

DWR

WWS=0

-1.86

0.00

WWSS

WWS=0 -

6.03

0.25

WWS>0

-1.73

0.19

WWS>0

-4.29

0.50

Valid Data Out Hold Time after WR
Deasserted

DOH

-1.71

0.25

WWSH

Valid Data Out Set Up Time to WR
Deasserted

DOS

-2.38

0.19

WWS,WWSS

-4.42

0.50

Valid Address after WR
Deasserted

WAC

-1.44

0.25

WWSH

RD Deasserted to Address Invalid

RDA

- 0.51

0.00

RWSH

Address Valid to RD Deasserted

ARDD

-2.03

1.00

RWSS,RWS

Valid Input Data Hold after RD
Deasserted

DRD

0.00

N/A

N/A since device captures data before it deasserts RD

RD Assertion Width

-0.97

1.00

RWS

Address Valid to Input Data Valid

-10.13

1.00

RWSS,RWS

-13.22

1.19

Address Valid to RD Asserted

ARDA

- 1.06

0.00

RWSS

RD Asserted to Input Data Valid

RDD

-9.06

1.00

RWSS,RWS

-12.65

1.19

WR Deasserted to RD Asserted

WRRD

-0.70

0.25

WWSH,RWSS

RD Deasserted to RD Asserted

RDRD

-0.17

If RWSS = RWSH = 0, RD does not deassert during back-to-back reads and D=0.00 should be used.

0.00

RWSS,RWSH

WR Deasserted to WR Asserted

WRWR

WWS=0

-0.47

0.75

WWSS, WWSH

WWS>0

-0.07

1.00

RD Deasserted to WR Asserted

RDWR

0.10

0.50

MDAR, BMDAR,

RWSH, WWSS

-0.31

0.69

DSP56852 Preliminary Technical Data

MOTOROLA

4.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Table 11. Reset, Stop, Wait, Mode Select, and Interrupt Timing

1, 2

Operating Conditions: V

= V

SSIO

= V

SSA

= 0V, V

= 1.62-1.98V, V

DDIO

= V

DDA

= 3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

In the formulas, T = clock cycle. For f

= 120MHz operation and f

ipb

= 60MHz, T = 8.33ns.

Parameters listed are guaranteed by design.

Characteristic

Symbol

Min

Max

Unit

See

Figure

RESET Assertion to Address, Data and Control
Signals High Impedance

RAZ

Figure 12

Minimum RESET Assertion Duration

At reset, the PLL is disabled and bypassed. The part is then put into run mode and t

clk

assumes the period of the source

clock, t

xtal

, t

extal

or t

osc

Figure 12

RESET Deassertion to First External Address Output

RDA

120T

Figure 12

Edge-sensitive Interrupt Request Width

IRW

1T + 3

Figure 13

IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine

IDM

18T

Figure 14

IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine

18T

Figure 14

IRQA Low to First Valid Interrupt Vector Address Out

recovery from Wait State

The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state.

This is not the minimum required so that the IRQA interrupt is accepted.

IRI

13T

Figure 15

IRQA Width Assertion to Recover from Stop State

Fast

Normal

The interrupt instruction fetch is visible on the pins only in Mode 3.

Fast stop mode:

Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery

is requested (OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery
takes one less cycle and t

clk

will continue same value it had before stop mode was entered.

Normal stop mode:

As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the mas-

ter clock, recovery will take an extra cycle (to restart the clock), and t

clk

will resume at the input clock source rate.

8ET

--
--

ns
ns

Figure 16

Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)

Fast

Normal

--
--

13T

25ET

ns
ns

Figure 16

RSTO pulse width

normal operation
internal reset mode

ET = External Clock period, For an external crystal frequency of 8MHz, ET=125 ns.

RSTO

128ET

8ET

--
--

Figure 17

Reset, Stop, Wait, Mode Select, and Interrupt Timing

MOTOROLA

DSP56852 Preliminary Technical Data

Figure 12. Asynchronous Reset Timing

Figure 13. External Interrupt Timing (Negative-Edge-Sensitive)

Figure 14. External Level-Sensitive Interrupt Timing

Figure 15. Interrupt from Wait State Timing

First Fetch

A0A20,

D0D15

CS,

RD, WR

RESET

First Fetch

RDA

RAZ

IRQA

IRQB

IRW

A0A20,

CS,

IRQA,

IRQB

First Interrupt Instruction Execution

a) First Interrupt Instruction Execution

Purpose

I/O Pin

IRQA,

IRQB

b) General Purpose I/O

IDM

Instruction Fetch

IRQA,

IRQB

First Interrupt Vector

A0A20,

CS,

RD, WR

IRI

Serial Peripheral Interface (SPI) Timing

MOTOROLA

DSP56852 Preliminary Technical Data

4.8 Serial Peripheral Interface (SPI) Timing

Parameters listed are guaranteed by design.

Table 12. SPI Timing

Operating Conditions: V

= V

SSIO

= V

SSA

= 0V, V

= 1.62-1.98V, V

DDIO

= V

DDA

= 3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

Characteristic

Symbol

Min

Max

Unit

See

Figure

Cycle time
Master
Slave

25
25

--
--

ns
ns

Figures

Enable lead time
Master
Slave

ELD

12.5

--
--

ns
ns

Figure

Enable lag time
Master
Slave

ELG

12.5

--
--

ns
ns

Figure

Clock (SCLK) high time
Master
Slave

12.5

--
--

ns
ns

Figures

Clock (SCLK) low time
Master
Slave

12.5

--
--

ns
ns

Figure

Data setup time required for inputs
Master
Slave

--
--

ns
ns

Figures

Data hold time required for inputs
Master
Slave

0
2

--
--

ns
ns

Figures

Access time (time to data active from high-impedance
state)
Slave

ns
ns

Figure

Disable time (hold time to high-impedance state)
Slave

ns
ns

Figure

Data Valid for outputs
Master
Slave (after enable edge)

--
--

ns
ns

Figures

Data invalid
Master
Slave

0
0

--
--

ns
ns

Figures

Rise time
Master
Slave

--
--

11.5
10.0

ns
ns

Figures

Fall time
Master
Slave

--
--

9.7
9.0

ns
ns

Figures

DSP56852 Preliminary Technical Data

MOTOROLA

Figure 18. SPI Master Timing (CPHA = 0)

Figure 19. SPI Master Timing (CPHA = 1)

SCLK (CPOL = 0)

(Output)

SCLK (CPOL = 1)

(Output)

MISO

(Input)

MOSI

(Output)

MSB in

Bits 141

LSB in

Master MSB out

Bits 141

Master LSB out

(Input)

SS is held High on master

(ref)

SCLK (CPOL = 0)

(Output)

SCLK (CPOL = 1)

(Output)

MISO

(Input)

MOSI

(Output)

MSB in

Bits 141

LSB in

Master MSB out

Bits 14 1

Master LSB out

(Input)

SS is held High on master

(ref)

Serial Peripheral Interface (SPI) Timing

MOTOROLA

DSP56852 Preliminary Technical Data

Figure 20. SPI Slave Timing (CPHA = 0)

Figure 21. SPI Slave Timing (CPHA = 1)

SCLK (CPOL = 0)

(Input)

SCLK (CPOL = 1)

(Input)

MISO

(Output)

MOSI

(Input)

Slave MSB out

Bits 141

MSB in

Bits 141

LSB in

(Input)

Slave LSB out

ELG

ELD

SCLK (CPOL = 0)

(Input)

SCLK (CPOL = 1)

(Input)

MISO

(Output)

MOSI

(Input)

Slave MSB out

Bits 141

MSB in

Bits 141

LSB in

(Input)

Slave LSB out

ELG

ELD

DSP56852 Preliminary Technical Data

MOTOROLA

4.9 Quad Timer Timing

Figure 22. Timer Timing

Table 13. Timer Timing

1, 2

Operating Conditions: V

= V

SSIO

= V

SSA

= 0V, V

= 1.62-1.98V, V

DDIO

= V

DDA

= 3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

In the formulas listed, T = clock cycle. For f

= 120MHz operation and fipb = 60MHz, T = 8.33ns

Parameters listed are guaranteed by design.

Characteristic

Symbol

Min

Max

Unit

Timer input period

2T + 3

Timer input high/low period

INHL

1T + 3

Timer output period

OUT

2T - 3

Timer output high/low period

OUTHL

1T - 3

Timer Inputs

Timer Outputs

INHL

OUTHL

OUT

Synchronous Serial Interface (SSI) Timing

MOTOROLA

DSP56852 Preliminary Technical Data

4.10 Synchronous Serial Interface (SSI) Timing

Table 14. SSI Master Mode

Switching Characteristics

Operating Conditions: V

= V

SSIO

= V

SSA

= 0V, V

= 1.62-1.98V, V

DDIO

= V

DDA

= 3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

Master mode is internally generated clocks and frame syncs

Parameter

Symbol

Min

Typ

Max

Units

STCK frequency

Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for a 120MHz part.

MHz

STCK period

All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)

and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync has
been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS in
the tables and in the figures.

SCKW

66.7

STCK high time

SCKH

33.4

STCK low time

SCKL

33.4

Output clock rise/fall time

Delay from STCK high to STFS (bl) high - Master

bl = bit length; wl = word length

TFSBHM

-1.0

-0.1

Delay from STCK high to STFS (wl) high - Master

TFSWHM

-1.0

-0.1

Delay from SRCK high to SRFS (bl) high - Master

RFSBHM

0.1

1.0

Delay from SRCK high to SRFS (wl) high - Master

RFSWHM

0.1

1.0

Delay from STCK high to STFS (bl) low - Master

TFSBLM

-1.0

-0.1

Delay from STCK high to STFS (wl) low - Master

TFSWLM

-1.0

-0.1

Delay from SRCK high to SRFS (bl) low - Master

RFSBLM

-0.1

0.1

Delay from SRCK high to SRFS (wl) low - Master

RFSWLM

-0.1

0.1

STCK high to STXD enable from high impedance - Master

TXEM

STCK high to STXD valid - Master

TXVM

STCK high to STXD not valid - Master

TXNVM

-0.1

STCK high to STXD high impedance - Master

TXHIM

-4

SRXD Setup time before SRCK low - Master

SRXD Hold time after SRCK low - Master

Synchronous Operation (in addition to standard internal clock parameters)

SRXD Setup time before STCK low - Master

TSM

SRXD Hold time after STCK low - Master

THM

DSP56852 Preliminary Technical Data

MOTOROLA

Figure 23. Master Mode Timing Diagram

Table 15. SSI Slave Mode

Switching Characteristics

Operating Conditions: V

= V

SSIO

= V

SSA

= 0V, V

= 1.62-1.98V, V

DDIO

= V

DDA

= 3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

Parameter

Symbol

Min

Typ

Max

Units

STCK frequency

MHz

STCK period

SCKW

66.7

STCK high time

SCKH

33.4

STCK low time

SCKL

33.4

Output clock rise/fall time

Delay from STCK high to STFS (bl) high - Slave

TFSBHS

-1

Delay from STCK high to STFS (wl) high - Slave

TFSWHS

-1

THM

TSM

RFSWLM

RFSWHM

RFBLM

RFSBHM

TXHIM

TXNVM

TXVM

TXEM

TFSWLM

TFSWHM

TFSBLM

TFSBHM

SCKL

SCKW

SCKH

First Bit

Last Bit

STCK output

STFS (bl) output

STFS (wl) output

STXD

SRCK output

SRFS (bl) output

SRFS (wl) output

SRXD

Synchronous Serial Interface (SSI) Timing

MOTOROLA

DSP56852 Preliminary Technical Data

Delay from SRCK high to SRFS (bl) high - Slave

RFSBHS

-1

Delay from SRCK high to SRFS (wl) high - Slave

RFSWHS

-1

Delay from STCK high to STFS (bl) low - Slave

TFSBLS

-29

Delay from STCK high to STFS (wl) low - Slave

TFSWLS

-29

Delay from SRCK high to SRFS (bl) low - Slave

RFSBLS

-29

Delay from SRCK high to SRFS (wl) low - Slave

RFSWLS

-29

STCK high to STXD enable from high impedance - Slave

TXES

STCK high to STXD valid - Slave

TXVS

STFS high to STXD enable from high impedance (first bit) -
Slave

FTXES

STFS high to STXD valid (first bit) - Slave

FTXVS

STCK high to STXD not valid - Slave

TXNVS

STCK high to STXD high impedance - Slave

TXHIS

SRXD Setup time before SRCK low - Slave

SRXD Hold time after SRCK low - Slave

Synchronous Operation (in addition to standard external clock parameters)

SRXD Setup time before STCK low - Slave

TSS

SRXD Hold time after STCK low - Slave

THS

Slave mode is externally generated clocks and frame syncs

Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for a 120MHz part.

All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)

and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync
has been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS
in the tables and in the figures.

50 percent duty cycle

bl = bit length; wl = word length

Table 15. SSI Slave Mode

Switching Characteristics (Continued)

Operating Conditions: V

= V

SSIO

= V

SSA

= 0V, V

= 1.62-1.98V, V

DDIO

= V

DDA

= 3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

Parameter

Symbol

Min

Typ

Max

Units

DSP56852 Preliminary Technical Data

MOTOROLA

Figure 24. Slave Mode Clock Timing

4.11 Serial Communication Interface (SCI) Timing

Table 16. SCI Timing

Operating Conditions: V

= V

SSIO

= V

SSA

= 0V, V

= 1.62-1.98V, V

DDIO

= V

DDA

= 3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

Characteristic

Symbol

Min

Max

Unit

Baud Rate

MAX

is the frequency of operation of the system clock in MHz.

MAX

)/(32)

Mbps

RXD

Pulse Width

The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.

RXD

0.965/BR

1.04/BR

TXD

Pulse Width

The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.

Parameters listed are guaranteed by design.

TXD

0.965/BR

1.04/BR

THS

TSS

RFSWLS

RFSWHS

RFSBLS

RFSBHS

TXHIS

TXNVS

FTXVS

TXVS

FTXES

TXES

TFSWLS

TFSWHS

TFSBLS

TFSBHS

SCKL

SCKW

SCKH

First Bit

Last Bit

STCK input

STFS (bl) input

STFS (wl) input

STXD

SRCK input

SRFS (bl) input

SRFS (wl) input

SRXD

JTAG Timing

MOTOROLA

DSP56852 Preliminary Technical Data

Figure 25. RXD Pulse Width

Figure 26. TXD Pulse Width

Figure 27. Bus Wakeup Detection

4.12 JTAG Timing

Table 17. JTAG Timing

1, 3

Operating Conditions: V

= V

SSIO

= V

SSA

= 0V, V

= 1.62-1.98V, V

DDIO

= V

DDA

= 3.03.6V, T

= 40

to +120

C, C

50pF, f

= 120MHz

Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For120MHz

operation, T = 8.33 ns

Characteristic

Symbol

Min

Max

Unit

TCK frequency of operation

TCK frequency of operation must be less than 1/4 the processor rate.

Parameters listed are guaranteed by design.

MHz

TCK cycle time

33.3

TCK clock pulse width

16.6

TMS, TDI data setup time

TMS, TDI data hold time

TCK low to TDO data valid

TCK low to TDO tri-state

TRST assertion time

TRST

DE assertion time

RXD

SCI receive

data pin

(Input)

RXD

TXD

SCI receive

data pin

(Input)

TXD

MSCAN_RX

CAN receive

data pin

(Input)

WAKE-UP

DSP56852 Preliminary Technical Data

MOTOROLA

Part 5 DSP56852 Packaging & Pinout Information

This section contains package and pin-out information for the 81-pin MAPBGA configuration of the
DSP56852.

Figure 33. Bottom-View, DSP56852 81-pin MAPBGA Package

METALLIZED MARK FOR

PIN 1 IDENTIFICATION

IN THIS AREA

IRQA

GPIOC1

SCK

DDIO

SSIO

TD0

EXTAL

DDA

TDI

GPIOC0

RXD

IRQB

DDIO

SSIO

TXD

CS0

MOSI

MISO

CS1

D14

TMS

TCK

D15

SSA

DDIO

SSIO

CS2

RESET

D13

D12

TRST

D11

D10

A16

SSIO

DDIO

A17

A18

A12

A14

A15

DDIO

A11

A19

SSIO

CLKO

DDIO

SSIO

A13

A10

XTAL

GPIO Timing

MOTOROLA

DSP56852 Preliminary Technical Data

Table 19. DSP56852 Pin Identification by Pin Number

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

CS0

EXTAL

DDIO

CS1

SSA

DDIO

CS2

DDIO

SSIO

RESET

SSIO

RXD

SSIO

SCK

SSIO

GPIOC1

A10

SSIO

A11

IRQA

GPIOC0

A12

IRQB

TCK

A13

D10

MISO

TDI

A14

D11

MOSI

TDO

A15

D12

DDA

TMS

A16

D13

TRST

A17

D14

TXD

A18

D15

A19

DDIO

XTAL

CLKO

DSP56852 Preliminary Technical Data

MOTOROLA

Figure 34. 81-pin MAPBGA Mechanical Information

NOTES:
1.

DIMENSIONS ARE IN MILLIMETERS.

INTERPRET DIMENSIONS AND
TOLERANCES PER ASME Y14.5M, 1994.

DIMENSION b IS MEASURED AT THE
MAXIMUM SOLDER BALL DIAMETER,
PARALLEL TO DATUM PLANE Z.

DATUM Z (SEATING PLANE) IS DEFINED BY
THE SPHERICAL CROWNS OF THE SOLDER
BALLS.

PARALLELISM MEASUREMENT SHALL
EXCLUDE ANY EFFECT OF MARK ON TOP
SURFACE OF PACKAGE.

CASE 1224B-01

ISSUE A

DATE 06/30/00

0.20

LASER MARK FOR PIN 1
IDENTIFICATION IN
THIS AREA

0.15 Z

0.30 Z

ROTATED 90 CLOCKWISE

DETAIL K

VIEW M-M

0.25

0.10

81X

160X

DIM MIN

MAX

MILLIMETERS

0.95

1.3

0.2

0.34

0.96 REF

0.3

0.5

8.00 BSC

0.80 BSC

Detail K

METALIZED MARK FOR

PIN 1 IDENTIFICATION

IN THIS AREA

Thermal Design Considerations

MOTOROLA

DSP56852 Preliminary Technical Data

Part 6 Design Considerations

6.1 Thermal Design Considerations

An estimation of the chip junction temperature, T

, in

°C can be obtained from the equation:

Equation 1:

= T

+ (P

x R

)

Where:

= ambient temperature °C

= package junction-to-ambient thermal resistance °C/W

= power dissipation in package

Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and
a case-to-ambient thermal resistance:

Equation 2:

= R

+ R

Where:

= package junction-to-ambient thermal resistance °C/W

= package junction-to-case thermal resistance °C/W

= package case-to-ambient thermal resistance °C/W

is device-related and cannot be influenced by the user. The user controls the thermal environment to

change the case-to-ambient thermal resistance, R

. For example, the user can change the air flow around

the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the
heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device
thermal performance may need the additional modeling capability of a system level thermal simulation tool.

The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the
package is mounted. Again, if the estimations obtained from R

do not satisfactorily answer whether the

thermal performance is adequate, a system level model may be appropriate.

A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:

Measure the thermal resistance from the junction to the outside surface of the package (case) closest
to the chip mounting area when that surface has a proper heat sink. This is done to minimize
temperature variation across the surface.

Measure the thermal resistance from the junction to where the leads are attached to the case. This
definition is approximately equal to a junction to board thermal resistance.

Use the value obtained by the equation (T

)/P

where T

is the temperature of the package

case determined by a thermocouple.

As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the
first definition. From a practical standpoint, that value is also suitable for determining the junction
temperature from a case thermocouple reading in forced convection environments. In natural convection,
using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading

DSP56852 Preliminary Technical Data

MOTOROLA

on the case of the package will estimate a junction temperature slightly hotter than actual. Hence, the new
thermal metric, Thermal Characterization Parameter, or

, has been defined to be (T

)/P

. This value

gives a better estimate of the junction temperature in natural convection when using the surface temperature
of the package. Remember that surface temperature readings of packages are subject to significant errors
caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor.
The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the
package with thermally conductive epoxy.

6.2 Electrical Design Considerations

Use the following list of considerations to assure correct DSP operation:

Provide a low-impedance path from the board power supply to each V

pin on the DSP, and from

the board ground to each V

(GND) pin.

The minimum bypass requirement is to place six 0.010.1

µF capacitors positioned as close as

possible to the package supply pins. The recommended bypass configuration is to place one bypass
capacitor on each of the ten V

pairs, including V

DDA

SSA.

Ensure that capacitor leads and associated printed circuit traces that connect to the chip V

and

(GND) pins are less than 0.5 inch per capacitor lead.

Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for V

and GND.

Bypass the V

and GND layers of the PCB with approximately 100

µF, preferably with a high-

grade capacitor such as a tantalum capacitor.

Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal.

Consider all device loads as well as parasitic capacitance due to PCB traces when calculating
capacitance. This is especially critical in systems with higher capacitive loads that could create
higher transient currents in the V

and GND circuits.

All inputs must be terminated (i.e., not allowed to float) using CMOS levels.

Take special care to minimize noise levels on the V

DDA

and V

SSA

pins.

When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pull-
up device.

CAUTION

This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.

DSP56852/D

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