DSP56F826 Data Sheet

DSP56F826/D

Rev. 9.0, 04/2003

56F826

Technical Data

56F826 16-bit Hybrid Controller

Up to 40 MIPS at 80MHz core frequency

DSP and MCU functionality in a unified,
C-efficient architecture

Hardware DO and REP loops

MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes

31.5K

× 16-bit words Program Flash

512

× 16-bit words Program RAM

× 16-bit words Data Flash

× 16-bit words Data RAM

× 16-bit words BootFLASH

Up to 64K

× 16-bit words each of external

memory expansion for Program and Data
memory

One Serial Port Interface (SPI)

One additional SPI or two optional Serial
Communication Interfaces (SCI)

One Synchronous Serial Interface (SSI)

One General Purpose Quad Timer

JTAG/OnCE

for debugging

100-pin LQFP Package

16 dedicated and 30 shared GPIO

Time-of-Day (TOD) Timer

Figure 1. 56F826 Block Diagram

JTAG/
OnCE

Port

Program Controller

and

Hardware Looping Unit

Data ALU

16 x 16 + 36

36-Bit MAC

Three 16-bit Input Registers

Two 36-bit Accumulators

Address

Generation

Unit

Bit

Manipulation

Unit

PLL

Clock Gen

16-Bit
56800

Core

PAB

PDB

XDB2

CGDB

XAB1

XAB2

XTAL

EXTAL

INTERRUPT

CONTROLS

IPBB

CONTROLS

IPBus Bridge

(IPBB)

MODULE CONTROLS

ADDRESS BUS [8:0]

DATA BUS [15:0]

COP

RESET

Application-

Specific

Memory &

Peripherals

Interrupt

Controller

Program Memory
32252 x 16 Flash

512 x 16 SRAM

Boot Flash

2048 x 16 Flash

Data Memory

2048 x 16 Flash

4096 x 16 SRAM

COP/

Watchdog

SCI0 & SCI1

SPI0

SSI

GPIO

Quad Timer

GPIO

DDIO

SSIO

DDA

SSA

SPI1

GPIO

Dedicated

GPIO

External

Bus

Interface

Unit

External

Address Bus

Switch

Bus

Control

External

Data Bus

Switch

RD Enable

WR Enable

DS Select[1]

PS Select[0]

D[00:15]

A[00:15]
or
GPIO

CLKO

RESET

IRQA

IRQB

EXTBOOT

TOD

Timer

Low Voltage

Superviso

Analog Reg

56F826 Technical Data

MOTOROLA

Part 1 Overview

1.1 56F826 Features

1.1.1

Digital Signal Processing Core

Efficient 16-bit 56800 Family hybrid controller engine with dual Harvard architecture

As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency

Single-cycle 16

× 16-bit parallel Multiplier-Accumulator (MAC)

Two 36-bit accumulators, including extension bits

16-bit bidirectional barrel shifter

Parallel instruction set with unique DSP addressing modes

Hardware DO and REP loops

Three internal address buses and one external address bus

Four internal data buses and one external data bus

Instruction set supports both DSP and controller functions

Controller style addressing modes and instructions for compact code

Efficient C Compiler and local variable support

Software subroutine and interrupt stack with depth limited only by memory

JTAG/OnCE Debug Programming Interface

1.1.2

Memory

Harvard architecture permits as many as three simultaneous accesses to Program and Data memory

On-chip memory including a low-cost, high-volume Flash solution

-- 31.5K

× 16-bit

words of Program Flash

-- 512

× 16-bit

words of Program RAM

-- 2K

× 16-bit

words of Data Flash

-- 4K

× 16-bit

words of Data RAM

-- 2K

× 16-bit

words of BootFLASH

Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states

-- As much as 64 K

× 16-bit

Data memory

-- As much as 64 K

× 16-bit

Program memory

1.1.3

Peripheral Circuits for 56F826

One General Purpose Quad Timer totalling 7 pins

One Serial Peripheral Interface with 4 pins (or four additional GPIO lines)

One Serial Peripheral Interface, or multiplexed with two Serial Communications Interfaces
totalling 4 pins

Synchronous Serial Interface (SSI) with configurable six-pin port (or six additional GPIO lines)

56F826 Description

MOTOROLA

56F826 Technical Data

Sixteen (16) dedicated general purpose I/O (GPIO) pins

Thirty (30) shared general purpose I/O (GPIO) pins

Computer-Operating Properly (COP) Watchdog timer

Two external interrupt pins

External reset pin for hardware reset

JTAG/On-Chip Emulation (OnCETM) for unobtrusive, processor speed-independent debugging

Software-programmable, Phase Locked Loop-based frequency synthesizer for the hybrid controller
core clock

Fabricated in high-density EMOS with 5V-tolerant, TTL-compatible digital inputs

One Time of Day module

1.1.4

Energy Information

Dual power supply, 3.3V and 2.5V

Wait and Multiple Stop modes available

1.2 56F826 Description

The 56F826 is a member of the 56800 core-based family of hybrid controllers. It combines, on a single
chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of
peripherals to create an extremely cost-effective solution for general purpose applications. Because of its
low cost, configuration flexibility, and compact program code, the 56F826 is well-suited for many
applications. The 56F826 includes many peripherals that are especially useful for applications such as:
noise suppression, ID tag readers, sonic/subsonic detectors, security access devices, remote metering,
sonic alarms, POS terminals, feature phones.

The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C/C++ Compilers to enable rapid
development of optimized control applications.

The 56F826 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F826 also provides two external
dedicated interrupt lines, and up to 46 General Purpose Input/Output (GPIO) lines, depending on peripheral
configuration.

The 56F826 controller includes 31.5K words (16-bit) of Program Flash and 2K words of Data Flash (each
programmable through the JTAG port) with 512 words of Program RAM, and 4K words of Data RAM. It
also supports program execution from external memory.

The 56F826 incorporates a total of 2K words of Boot Flash for easy customer-inclusion of field-
programmable software routines that can be used to program the main Program and Data Flash memory
areas. Both Program and Data Flash memories can be independently bulk-erased or erased in page sizes of
256 words. The Boot Flash memory can also be either bulk or page erased.

This controller also provides a full set of standard programmable peripherals including one Synchronous
Serial Interface (SSI), one Serial Peripheral Interface (SPI), the option to select a second SPI or two Serial
Communications Interfaces (SCIs), and one Quad Timer. The SSI, SPI, and Quad Timer can be used as
General Purpose Input/Outputs (GPIOs) if a timer function is not required.

56F826 Technical Data

MOTOROLA

1.3 "Best in Class" Development Environment

The SDK (Software Development Kit) provides fully debugged peripheral drivers, libraries and interfaces
that allow a programmer to create their unique C application code independent of component architecture.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, the SDK, CodeWarrior, and EVMs create a complete,
scalable tools solution for easy, fast, and efficient development.

1.4 Product Documentation

The four documents listed in

Table 1

are required for a complete description and proper design with the

56F826. Documentation is available from local Motorola distributors, Motorola semiconductor sales
offices, Motorola Literature Distribution Centers, or online at www.motorola.com/dsp.

Table 1. 56F826 Chip Documentation

1.5 Data Sheet Conventions

This data sheet uses the following conventions:

Topic

Description

Order Number

DSP56800
Family Manual

Detailed description of the 56800 family architecture,
and 16-bit DSP core processor and the instruction set

DSP56800FM/D

DSP56F826/F827
User's Manual

Detailed description of memory, peripherals, and
interfaces of the 56F826 and 56F827

DSP56F826-827UM/D

DSP56F826
Technical Data Sheet

Electrical and timing specifications, pin descriptions,
and package descriptions (this document)

DSP56F826/D

DSP56F826
Product Brief

Summary description and block diagram of the 56F826
core, memory, peripherals and interfaces

DSP56F826PB/D

OVERBAR

This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.

"asserted"

A high true (active high) signal is high or a low true (active low) signal is low.

"deasserted"

A high true (active high) signal is low or a low true (active low) signal is high.

Examples:

Signal/Symbol

Logic State

Signal State

Voltage

Values for V

, V

, and V

are defined by individual product specifications.

True

Asserted

False

Deasserted

True

Asserted

False

Deasserted

Introduction

MOTOROLA

56F826 Technical Data

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56F826 are organized into functional groups, as shown in

Table 2

and

as illustrated in

Figure 2

Table 3

describes the signal or signals present on a pin.

Table 2. Functional Group Pin Allocations

Functional Group

Number of Pins

Power (V

, V

DDIO or

DDA

)

(3,4,1)

Ground (V

, V

SSIO or

SSA

)

(3,4,1)

PLL and Clock

Address Bus

Data Bus

Bus Control

Interrupt and Program Control

Dedicated General Purpose Input/Output

Synchronous Serial Interface (SSI) Port

Serial Peripheral Interface (SPI) Port

1. Alternately,

GPIO

pins

Serial Communications Interface (SCI) Ports

Quad Timer Module Ports

JTAG/On-Chip Emulation (OnCE)

56F826 Technical Data

MOTOROLA

Figure 2. 56F826 Signals Identified by Functional Group

1. Alternate pin functionality is shown in parenthesis.

56F826

2.5V Power

Ground

3.3V Power

Ground

3.3V Analog Power

Analog Ground

PLL

and

Clock

External

Address Bus or

GPIO

External Data

Bus

External

Bus Control

Dedicated
GPIO

SPI1 Port
or GPIO

SCI0, SCI1
Port or
SPI0 Port

DDIO

SSIO

DDA

SSA

EXTAL

XTAL (CLOCKIN)

CLKO

A0-A7 (GPIOE)

A8-A15 (GPIOA)

D0D15

TA0 (GPIOF0)

TA1 (GPIOF1)

TA2 (GPIOF2)

TA3 (GPIOF3)

TCK

TMS

TDI

TDO

TRST

Quad Timer A

or GPIO

JTAG/OnCE

Port

GPIOB07

GPIOD07

SRD (GPIOC0)

SRFS (GPIOC1)

SRCK (GPIOC2)

STD (GPIOC3)

STFS (GPIOC4)

STCK (GPIOC5)

SCLK (GPIOF4)

MOSI (GPIOF5)

MISO (GPIOF6)

SS (GPIOF7)

TXD0 (SCLK0)

RXD0 (MOSI0)

TXD1 (MISO0)

RXD1 (SS0)

IRQA

IRQB

RESET

EXTBOOT

SSI Port
or GPIO

Interrupt/
Program
Control

Signals and Package Information

MOTOROLA

56F826 Technical Data

2.2 Signals and Package Information

All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always
enabled. Exceptions:

1. When a pin is owned by GPIO, then the pull-up may be disabled under software control.

2. TCK has a weak pull-down circuit always active.

Table 3. 56F826 Signal and Package Information for the 100 Pin LQFP

Signal

Name

Pin No.

Type

Description

Power--These pins provide power to the internal structures of the chip,
and are generally connected to a 2.5V supply.

GND--These pins provide grounding for the internal structures of the
chip. All should be attached to V

SS.

DDIO

Power In/Out--These pins provide power to the I/O structures of the
chip, and are generally connected to a 3.3V supply.

DDIO

SSIO

GND In/Out--These pins provide grounding for the I/O ring on the chip.
All should be attached to V

SS.

SSIO

DDA

Analog Power--This pin is a dedicated power pin for the analog portion
of the chip and should be connected to a low noise 3.3V supply.

SSA

Analog Ground--This pin supplies an analog ground.

EXTAL

Input

External Crystal Oscillator Input--This input should be connected to
an 4MHz external crystal or ceramic resonator. For more information,
please refer to

Section 3.6

56F826 Technical Data

MOTOROLA

XTAL

(CLOCKIN)

Output

Input

Crystal Oscillator Output--This output connects the internal crystal
oscillator output to an external crystal or ceramic resonator. If an external
clock source over 4MHz is used, XTAL must be used as the input and
EXTAL connected to

SS. For more information, please refer to

Section

3.6.3

External Clock Input--This input should be asserted when using an
external clock or ceramic resonator.

CLKO

Output

Clock Output--This pin outputs a buffered clock signal. By programming
the CLKO Select Register CSLKOSR), the user can select between
outputting a version of the signal applied to XTAL and a version of the
device master clock at the output of the PLL. The clock frequency on this
pin can be disabled by programming the CLKO Select Register
(CLKOSR).

(GPIOE0)

Output

Input/Output

Address Bus--A0A7 specify the address for external program or data
memory accesses.

Port E GPIO--These eight General Purpose I/O (GPIO) pins can be
individually programmed as input or output pins.

After reset, the default state is Address Bus.

(GPIOE1)

(GPIOE2)

(GPIOE3)

(GPIOE4)

(GPIOE5)

(GPIOE6)

(GPIOE7)

Table 3. 56F826 Signal and Package Information for the 100 Pin LQFP

Signal

Name

Pin No.

Type

Description

56F826 Technical Data

MOTOROLA

Input/Output

Data Bus-- D0D15 specify the data for external program or data memory
accesses. D0D15 are tri-stated when the external bus is inactive.

D10

D11

D12

D13

D14

D15

Output

Program Memory Select--PS is asserted low for external program
memory access.

Output

Data Memory Select--DS is asserted low for external data memory
access.

Output

Read Enable--RD is asserted during external memory read cycles.
When RD is asserted low, pins D0D15 become inputs and an external
device is enabled onto the device data bus. When RD is deasserted high,
the external data is latched inside the device. When RD is asserted, it
qualifies the A0A15, PS, and DS pins. RD can be connected directly to
the OE pin of a Static RAM or ROM.

Output

Write Enable--WR is asserted during external memory write cycles.
When WR is asserted low, pins D0D15 become outputs and the device
puts data on the bus. When WR is deasserted high, the external data is
latched inside the external device. When WR is asserted, it qualifies the
A0A15, PS, and DS pins. WR can be connected directly to the WE pin of
a Static RAM.

Table 3. 56F826 Signal and Package Information for the 100 Pin LQFP

Signal

Name

Pin No.

Type

Description

Signals and Package Information

MOTOROLA

56F826 Technical Data

TA0-0

(GPIOF0)

Input/Output

TA03--Timer F Channels 0, 1, 2, and 3

Port F GPIO--These four General Purpose I/O (GPIO) pins can be
individually programmed as input or output.

After reset, the default state is Quad Timer.

TA0-1

(GPIOF1)

TA0-2

(GPIOF2)

TA0-3

(GPIOF3)

TCK

100

Input

(Schmitt)

Test Clock Input--This input pin provides a gated clock to synchronize
the test logic and shift serial data to the JTAG/OnCE port. The pin is
connected internally to a pull-down resistor.

TMS

Input

(Schmitt)

Test Mode Select Input--This input pin is used to sequence the JTAG
TAP controller's state machine. It is sampled on the rising edge of TCK
and has an on-chip pull-up resistor.

TDI

Input

(Schmitt)

Test Data Input--This input pin provides a serial input data stream to the
JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-
chip pull-up resistor.

TDO

Output

Test Data Output--This tri-statable output pin provides a serial output
data stream from the JTAG/OnCE port. It is driven in the Shift-IR and
Shift-DR controller states, and changes on the falling edge of TCK.

TRST

Input

(Schmitt)

Test Reset--As an input, a low signal on this pin provides a reset signal
to the JTAG TAP controller. To ensure complete hardware reset, TRST
should be asserted whenever RESET is asserted. The only exception
occurs in a debugging environment when a hardware device reset is
required and it is necessary not to reset the JTAG/OnCE module. In this
case, assert RESET, but do not assert TRST.

Output

Debug Event--DE provides a low pulse on recognized debug events.

TCS

Input/Output

(Schmitt)

TCS--This pin is reserved for factory use. It must be tied to V

for

normal use. In block diagrams, this pin is considered an additional V

SS.

Table 3. 56F826 Signal and Package Information for the 100 Pin LQFP

Signal

Name

Pin No.

Type

Description

56F826 Technical Data

MOTOROLA

GPIOB0

Input or

Output

Port B GPIO--These eight dedicated General Purpose I/O (GPIO) pins
can be individually programmed as input or output pins.

After reset, the default state is GPIO input.

GPIOB1

GPIOB2

GPIOB3

GPIOB4

GPIOB5

GPIOB6

GPIOB7

GPIOD0

Input or

Output

Port D GPIO--These eight dedicated GPIO pins can be individually
programmed as an input or output pins.

After reset, the default state is GPIO input.

GPIOD1

GPIOD2

GPIOD3

GPIOD4

GPIOD5

GPIOD6

GPIOD7

SRD

(GPIOC0)

Input/Output

SSI Receive Data (SRD)--This input pin receives serial data and
transfers the data to the SSI Receive Shift Receiver.

Port C GPIO--This is a General Purpose I/O (GPIO) pin with the
capability of being individually programmed as input or output.

After reset, the default state is GPIO input.

SRFS

(GPIOC1)

Input/ Output

Input/Output

SSI Serial Receive Frame Sync (SRFS)--This bidirectional pin is used
by the receive section of the SSI as frame sync I/O or flag I/O. The STFS
can be used only by the receiver. It is used to synchronize data transfer
and can be an input or an output.

Port C GPIO--This is a General Purpose I/O (GPIO) pin with the
capability of being individually programmed as input or output.

After reset, the default state is GPIO input.

Table 3. 56F826 Signal and Package Information for the 100 Pin LQFP

Signal

Name

Pin No.

Type

Description

Signals and Package Information

MOTOROLA

56F826 Technical Data

SRCK

(GPIOC2)

Input/Output

SSI Serial Receive Clock (SRCK)--This bidirectional pin provides the
serial bit rate clock for the Receive section of the SSI. The clock signal
can be continuous or gated and can be used by both the transmitter and
receiver in synchronous mode.

Port C GPIO--This is a General Purpose I/O (GPIO) pin with the
capability of being individually programmed as input or output.

After reset, the default state is GPIO input.

STD

(GPIOC3)

Output

Input/Output

SSI Transmit Data (STD)--This output pin transmits serial data from the
SSI Transmitter Shift Register.

Port C GPIO--This is a General Purpose I/O (GPIO) pin with the
capability of being individually programmed as input or output.

After reset, the default state is GPIO input.

STFS

(GPIOC4)

Input

Input/Output

SSI Serial Transmit Frame Sync (STFS)--This bidirectional pin is used
by the Transmit section of the SSI as frame sync I/O or flag I/O. The
STFS can be used by both the transmitter and receiver in synchronous
mode. It is used to synchronize data transfer and can be an input or
output pin.

Port C GPIO--This is a General Purpose I/O (GPIO) pin with the
capability of being individually programmed as input or output.

After reset, the default state is GPIO input.

STCK

(GPIOC5)

Input/ Output

Input/Output

SSI Serial Transmit Clock (STCK)--This bidirectional pin provides the
serial bit rate clock for the transmit section of the SSI. The clock signal
can be continuous or gated. It can be used by both the transmitter and
receiver in synchronous mode.

Port C GPIO--This is a General Purpose I/O (GPIO) pin with the
capability of being individually programmed as input or output.

After reset, the default state is GPIO input.

SCLK

(GPIOF4)

Input/Output

SPI Serial Clock--In master mode, this pin serves as an output, clocking
slaved listeners. In slave mode, this pin serves as the data clock input.

Port F GPIO--This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.

After reset, the default state is SCLK.

Table 3. 56F826 Signal and Package Information for the 100 Pin LQFP

Signal

Name

Pin No.

Type

Description

56F826 Technical Data

MOTOROLA

MOSI

(GPIOF5)

Input/Output

SPI Master Out/Slave In (MOSI)--This serial data pin is an output from a
master device and an input to a slave device. The master device places
data on the MOSI line a half-cycle before the clock edge that the slave
device uses to latch the data.

Port F GPIO--This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.

MISO

(GPIOF6)

Input/Output

SPI Master In/Slave Out (MISO)--This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device is
not selected.

Port F GPIO--This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.

After reset, the default state is MISO.

(GPIOF7)

Input

Input/Output

SPI Slave Select--In master mode, this pin is used to arbitrate multiple
masters. In slave mode, this pin is used to select the slave.

Port F GPIO--This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.

After reset, the default state is SS.

TXD0

(SCLK0)

Output

Input/Output

Transmit Data (TXD0)--transmit data output

SPI Serial Clock--In master mode, this pin serves as an output, clocking
slaved listeners. In slave mode, this pin serves as the data clock input.

After reset, the default state is SCI output.

RXD0

(MOSI0)

Input

Input/

Output

Receive Data (RXD0)-- receive data input

SPI Master Out/Slave In--This serial data pin is an output from a master
device, and an input to a slave device. The master device places data on
the MOSI line one half-cycle before the clock edge the slave device uses
to latch the data.

After reset, the default state is SCI input.

TXD1

(MISO0)

Output

Input/Output

Transmit Data (TXD1)--transmit data output

SPI Master In/Slave Out--This serial data pin is an input to a master
device and an output from a slave device. The MISO line of a slave
device is placed in the high-impedance state if hte slave device is not
selected.

After reset, the default state is SCI output.

Table 3. 56F826 Signal and Package Information for the 100 Pin LQFP

Signal

Name

Pin No.

Type

Description

Signals and Package Information

MOTOROLA

56F826 Technical Data

RXD1

(SS0)

Input

(Schmitt)

Input

Receive Data (RXD1)-- receive data input

SPI Slave Select--In master mode, this pin is used to arbitrate multiple
masters. In slave mode, this pin is used to select the slave.

After reset, the default state is SCI input.

IRQA

Input

(Schmitt)

External Interrupt Request A--The IRQA input is a synchronized
external interrupt request that indicates that an external device is
requesting service. It can be programmed to be level-sensitive or
negative-edge- triggered. If level-sensitive triggering is selected, an
external pull up resistor is required for wired-OR operation.

If the processor is in the Stop state and IRQA is asserted, the processor
will exit the Stop state.

IRQB

Input

(Schmitt)

External Interrupt Request B--The IRQB input is an external interrupt
request that indicates that an external device is requesting service. It can
be programmed to be level-sensitive or negative-edge-triggered. If level-
sensitive triggering is selected, an external pull up resistor is required for
wired-OR operation.

RESET

Input

(Schmitt)

Reset--This input is a direct hardware reset on the processor. When
RESET is asserted low, the device is initialized and placed in the Reset
state. A Schmitt trigger input is used for noise immunity. When the
RESET pin is deasserted, the initial chip operating mode is latched from
the external boot pin. The internal reset signal will be deasserted
synchronous with the internal clocks, after a fixed number of internal
clocks.

To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case, assert
RESET, but do not assert TRST.

EXTBOOT

Input

(Schmitt)

External Boot--This input is tied to V

to force device to boot from off-

chip memory. Otherwise, it is tied to ground.

Table 3. 56F826 Signal and Package Information for the 100 Pin LQFP

Signal

Name

Pin No.

Type

Description

56F826 Technical Data

MOTOROLA

Part 3 Specifications

3.1 General Characteristics

The 56F826 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term
"5V-tolerant" refers to the capability of an I/O pin, built on a 3.3V compatible process technology, to
withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V-compatible
I/O voltage levels. A standard 3.3V I/O is designed to receive a maximum voltage of 3.3V

± 10% during

normal operation without causing damage. This 5V-tolerant capability, therefore, offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.

Absolute maximum ratings given in

Table 4

are stress ratings only, and functional operation at the

maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.

The 56F826 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.

CAUTION

This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.

Table 4. Absolute Maximum Ratings

Characteristic

Symbol

Min

Max

Unit

Supply voltage, core

1. V

must not exceed V

DDIO

0.3

+ 3.0

Supply voltage, IO

Supply voltage, Analog

DDIO

DDA

2. V

DDIO

and V

DDA

must not differ by more that 0.5V

SSIO

0.3

SSA

0.3

SSIO

+ 4.0

SSA

+ 4.0

Digital input voltages

Analog input voltages - XTAL, EXTAL

INA

SSIO

0.3

SSA

0.3

SSIO

+ 5.5

DDA

+ 0.3

Current drain per pin excluding V

, V

SS,

DDA

, V

SSA,

DDIO

, V

SSIO

Junction temperature

150

°C

Storage temperature range

STG

150

°C

General Characteristics

MOTOROLA

56F826 Technical Data

Notes:

Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application.
Determined on 2s2p thermal test board.

Junction to ambient thermal resistance, Theta-JA (

) was simulated to be equivalent to the

JEDEC specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was
also simulated on a thermal test board with two internal planes (2s2p where "s" is the number of
signal layers and "p" is the number of planes) per JESD51-6 and JESD51-7. The correct name for
Theta-JA for forced convection or with the non-single layer boards is Theta-JMA.

Junction to case thermal resistance, Theta-JC (R

), was simulated to be equivalent to the

measured values using the cold plate technique with the cold plate temperature used as the "case"
temperature. The basic cold plate measurement technique is described by MIL-STD 883D, Method
1012.1. This is the correct thermal metric to use to calculate thermal performance when the package
is being used with a heat sink.

Thermal Characterization Parameter, Psi-JT (

), is the "resistance" from junction to reference

point thermocouple on top center of case as defined in JESD51-2.

is a useful value to use to

estimate junction temperature in steady state customer environments.

Table 5. Recommended Operating Conditions

Characteristic

Symbol

Min

Typ

Max

Unit

Supply voltage, core

2.4

2.5

2.75

Supply Voltage, IO and analog

DDIO,

DDA

3.0

3.3

3.6

Ambient operating temperature

°C

Table 6. Thermal Characteristics

Characteristic

Comments

Symbol

Value

Unit

Notes

100-pin LQFP

Junction to ambient
Natural convection

48.3

°C/W

Junction to ambient (@1m/sec)

JMA

43.9

°C/W

Junction to ambient
Natural convection

Four layer board (2s2p)

JMA

(2s2p)

40.7

°C/W

1.2

Junction to ambient (@1m/sec)

Four layer board (2s2p)

JMA

38.6

°C/W

1,2

Junction to case

13.5

°C/W

Junction to center of case

1.0

°C/W

4, 5

I/O pin power dissipation

I/O

User Determined

Power dissipation

= (I

x V

+ P

I/O

)

Junction to center of case

DMAX

(TJ - TA) /

°C

56F826 Technical Data

MOTOROLA

Junction temperature is a function of on-chip power dissipation, package thermal resistance,
mounting site (board) temperature, ambient temperature, air flow, power dissipation of other
components on the board, and board thermal resistance.

See Section 5.1 from more details on thermal design considerations.

3.2 DC Electrical Characteristics

Table 7. DC Electrical Characteristics

Operating Conditions:

SSIO

= V

SSA

= 0V, V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, T

= 40

° to +85°C, C

50pF, f

= 80MHz

Characteristic

Symbol

Min

Typ

Max

Unit

Input high voltage (XTAL/EXTAL)

IHC

2.25

3.6

Input low voltage (XTAL/EXTAL)

ILC

0.5

Input high voltage (Schmitt trigger inputs)

IHS

2.2

5.5

Input low voltage (Schmitt trigger inputs)

ILS

-0.3

0.8

Input high voltage (all other digital inputs)

2.0

5.5

Input low voltage (all other digital inputs)

-0.3

0.8

Input current high (pull-up/pull-down resistors disabled,
V

)

-1

Input current low (pull-up/pull-down resistors disabled,
V

)

-1

Input current high (with pull-up resistor, V

)

IHPU

-1

Input current low (with pull-up resistor, V

)

ILPU

-210

-50

Input current high (with pull-down resistor, V

)

IHPD

180

Input current low (with pull-down resistor, V

)

ILPD

-1

Nominal pull-up or pull-down resistor value

, R

Output tri-state current low

OZL

-10

Output tri-state current high

OZH

-10

Input current high (analog inputs, V

DDA

)

IHA

-15

Input current low (analog inputs, V

SSA

)

ILA

-15

Output High Voltage (at IOH)

0.7

Output Low Voltage (at IOL)

0.4

Output source current

Output sink current

PWM pin output source current

OHP

DC Electrical Characteristics

MOTOROLA

56F826 Technical Data

PWM pin output sink current

OLP

Input capacitance

Output capacitance

OUT

supply current

DDT

Run

Wait

Stop

Low Voltage Interrupt, V

DDIO

power supply

EIO

2.4

2.7

3.0

Low Voltage Interrupt, V

power supply

EIC

2.0

2.2

2.4

Power on Reset

POR

1.7

2.0

Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, TCS, TCK, TRST, TMS, TDI and RXD1

Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.

PWM pin output source current measured with 50% duty cycle.

PWM pin output sink current measured with 50% duty cycle.

5. I

DDT

= I

+ I

DDA

(Total supply current for V

+ V

DDA

)

6. Run (operating) I

measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports

configured as inputs; measured with all modules enabled.

7. Wait

measured using external square wave clock source (f

osc

= 8MHz) into XTAL; all inputs 0.2V from rail; no DC

loads; less than 50pF on all outputs. C

= 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects

wait I

; measured with PLL enabled.

8. This low-voltage interrupt monitors the V

DDIO

power supply. If V

DDIO

drops below V

EIO

, an interrupt is generated.

Functionality of the device is guaranteed under transient conditions when V

DDIO

EIO

(between the minimum specified

DDIO

and the point when the V

EIO

interrupt is generated).

9. This low-voltage interrupt monitors theV

power supply. If V

DDIO

drops below V

EIC

, an interrupt is generated.

Functionality of the device is guaranteed under transient conditions when V

EIC

(between the minimum specified V

and the point when the V

EIC

interrupt is generated).

10. Power

on reset occurs whenever the V

power supply drops below

POR

. While power is ramping up, this signal

remains active for as long as V

is below

POR

no matter how long the ramp-up rate is.

Table 7. DC Electrical Characteristics (Continued)

Operating Conditions:

SSIO

= V

SSA

= 0V, V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, T

= 40

° to +85°C, C

50pF, f

= 80MHz

Characteristic

Symbol

Min

Typ

Max

Unit

AC Electrical Characteristics

MOTOROLA

56F826 Technical Data

should not be allowed to rise early (1). This is usually avoided by running the regulator for the V

supply (2.5V) from the voltage generated by the 3.3V V

DDIO

supply, see

Figure 5

. This keeps V

from

rising faster than V

DDIO

should not rise so late that a large voltage difference is allowed between the two supplies (2). Typically

this situation is avoided by using external discrete diodes in series between supplies, as shown in

Figure 5

The series diodes forward bias when the difference between V

DDIO

and V

reaches approximately 1.4,

causing V

to rise as V

DDIO

ramps up. When the V

regulator begins proper operation, the difference

between supplies will typically be 0.8V and conduction through the diode chain reduces to essentially
leakage current. During supply sequencing, the following general relationship should be adhered to:
V

DDIO

> V

> (V

DDIO

- 1.4V)

In practice, V

DDA

is typically connected directly to V

DDIO

with some filtering.

Figure 5. Example Circuit to Control Supply Sequencing

3.4 AC Electrical Characteristics

Timing waveforms in

Section 3.4

are tested using the V

and V

levels specified in the DC Characteristics

table. In

Figure 6

the levels of V

and V

for an input signal are shown.

Figure 6. Input Signal Measurement References

Figure 7

shows the definitions of the following signal states:

Active state, when a bus or signal is driven, and enters a low impedance state.

Tri-stated, when a bus or signal is placed in a high impedance state.

Data Valid state, when a signal level has reached V

or V

OH.

Data Invalid state, when a signal level is in transition between V

and V

OH.

3.3V

Regulator

2.5V

Regulator

Supply

DDIO,

DDA

Fall Time

Input Signal

Note: The midpoint is V

+ (V

)/2.

Midpoint1

Low

High

Pulse Width

90%

50%

10%

Rise Time

56F826 Technical Data

MOTOROLA

3.5 Flash Memory Characteristics

Figure 7. Signal States

Table 8. Flash Memory Truth Table

Mode

X address enable, all rows are disabled when XE = 0

Y address enable, YMUX is disabled when YE = 0

3. Sense

amplifier

enable

Output enable, tri-state Flash data out bus when OE = 0

PROG

5. Defines

program

cycle

ERASE

6. Defines

erase

cycle

MAS1

Defines mass erase cycle, erase whole block

NVSTR

Defines non-volatile store cycle

Standby

Read

Word Program

Page Erase

Mass Erase

Table 9. IFREN Truth Table

Mode

IFREN = 1

IFREN = 0

Read

Read information block

Read main memory block

Word program

Program information block

Program main memory block

Page erase

Erase information block

Erase main memory block

Mass erase

Erase both block

Erase main memory block

Data Invalid State

Data1

Data2 Valid

Data

Tri-stated

Data3 Valid

Data2

Data3

Data1 Valid

Data Active

Flash Memory Characteristics

MOTOROLA

56F826 Technical Data

Table 10. Flash Timing Parameters

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6V, T

= 40

° to +85°C, C

50pF

Characteristic

Symbol

Min Typ

Max

Unit

Figure

Program time

prog*

Figure 8

Erase time

erase*

Figure 9

Mass erase time

me*

100

Figure 10

Endurance

One cycle is equal to an erase program and read.

CYC

10,000

20,000

cycles

Data Retention

@ 5000 cycles

RET

years

The following parameters should only be used in the Manual Word Programming Mode

PROG/ERASE to NVSTR set
up time

nvs*

Figure 8

Figure 9

Figure 10

NVSTR hold time

nvh*

Figure 8

Figure 9

NVSTR hold time (mass erase)

nvh1*

100

Figure 10

NVSTR to program set up time

pgs*

Figure 8

Recovery time

rcv*

Figure 8

Figure 9

Figure 10

Cumulative program

HV period

Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot

be programmed twice before next erase.

Figure 8

Program hold time

Parameters are guaranteed by design in smart programming mode and must be one cycle or greater.

*The Flash interface unit provides registers for the control of these parameters.

pgh

Figure 8

Address/data set up time

ads

Figure 8

Address/data hold time

adh

Figure 8

External Clock Operation

MOTOROLA

56F826 Technical Data

Figure 10. Flash Mass Erase Cycle

3.6 External Clock Operation

The 56F826 system clock can be derived from a crystal or an external system clock signal. To generate a
reference frequency using the internal oscillator, a reference crystal must be connected between the EXTAL
and XTAL pins.

3.6.1

Crystal Oscillator

The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the
frequency range specified for the external crystal in

Table 12

. In

Figure 11

a recommended crystal

oscillator circuit is shown. Follow the crystal supplier's recommendations when selecting a crystal,
because crystal parameters determine the component values required to provide maximum stability and
reliable start-up. The crystal and associated components should be mounted as close as possible to the
EXTAL and XTAL pins to minimize output distortion and start-up stabilization time.The internal 56F82x
oscillator circuitry is designed to have no external load capacitors present. As shown in

Figure 11

external load capacitors should be used.

The 56F82x components internally are modeled to provide a capacitive load on each of the oscillator pins
(XTAL and EXATL) of 10pF to 13pF over temperature and process variations. Using a typical value of
internal capacitance on these pins of 12pF and a value of 3pF as a typical circuit board trace capacitance
the parallel load capacitance presented to the crystal is 9pF. This is the value load capacitance that should
be used when selecting a crystal and determining the actual frequency of operation of the crystal oscillator
circuit.

XADR

YE=SE=OE=0

ERASE

NVSTR

Tnvs

Tnvh1

Trcv

Tme

MAS1

IFREN

56F826 Technical Data

MOTOROLA

Figure 11. Connecting to a Crystal Oscillator Circuit

3.6.2

Ceramic Resonator

It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system
design can tolerate the reduced signal integrity. In

Figure 12

, a typical ceramic resonator circuit is shown.

Refer to supplier's recommendations when selecting a ceramic resonator and associated components. The
resonator and components should be mounted as close as possible to the EXTAL and XTAL pins. The
internal 56F82x oscillator circuitry is designed to have no external load capacitors present. As shown in

Figure 12

no external load capacitors should be used.

Figure 12. Connecting a Ceramic Resonator

Note: Motorola recommends only two terminal ceramic resonators vs. three terminal
resonators (which contain an internal bypass capacitor to ground).

3.6.3

External Clock Source

The recommended method of connecting an external clock is given in

Figure 13

. The external clock

source is connected to XTAL and the EXTAL pin is held V

DDA

/2.

Figure 13. Connecting an External Clock Signal

Recommended External Crystal
Parameters:
R

= 1 to 3M

= 4Mhz (optimized for 4MHz)

EXTAL XTAL

Recommended Ceramic Resonator
Parameters:
R

= 1 to 3 M

= 4Mhz (optimized for 4MHz)

EXTAL XTAL

56F826

XTAL

EXTAL

External

DDA

Clock

External Clock Operation

MOTOROLA

56F826 Technical Data

Figure 14. External Clock Timing

3.6.4

Phase Locked Loop Timing

Table 11. External Clock Operation Timing Requirements

Operating Conditions:

SSIO

= V

SSA

= 0V, V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, T

= 40

° to +85°C, C

50pF, f

= 80MHz

Characteristic

Symbol

Min

Typ

Max

Unit

Frequency of operation (external clock driver)

1. See

Figure 13

for details on using the recommended connection of an external clock driver.

osc

When using Time of Day (TOD), maximum external frequency is 6MHz.

MHz

Clock Pulse Width

The high or low pulse width must be no smaller than 6.25ns or the chip will not function.

Parameters listed are guaranteed by design.

6.25

Table 12. PLL Timing

Operating Conditions:

SSIO

= V

SSA

= 0V, V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, T

= 40

° to +85°C, C

50pF, f

= 80MHz

Characteristic

Symbol

Min

Typ

Max

Unit

External reference crystal frequency for the PLL

An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work

correctly. The PLL is optimized for 4MHz input crystal.

osc

MHz

PLL output frequency

ZCLK may not exceed 80MHz. For additional information on ZCLK and

out

/2,

please refer to the OCCS chapter

in the User Manual. ZCLK = f

out

110

MHz

PLL stabilization time

-40

to +85

This is the minimum time required after the PLL set-up is changed to ensure reliable operation.

plls

External

Clock

Note: The midpoint is V

+ (V

)/2.

90%

50%

10%

90%

50%

10%

56F826 Technical Data

MOTOROLA

3.7 External Bus Asynchronous Timing

Table 13. External Bus Asynchronous Timing

1, 2

Operating Conditions:

SSIO

= V

SSA

= 0V, V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, T

= 40

° to +85°C, C

50pF, f

= 80MHz

Timing is both wait state- and frequency-dependent. In the formulas listed, WS = the number of wait states and

T = Clock Period. For 80MHz operation, T = 12.5ns.
2.

Parameters listed are guaranteed by design.

To calculate the required access time for an external memory for any frequency < 80Mhz, use this formula:
Top = Clock period @ desired operating frequency
WS = Number of wait states
Memory Access Time = (Top*WS) + (Top- 11.5)

Characteristic

Symbol

Min

Max

Unit

Address Valid to WR Asserted

AWR

6.5

WR Width Asserted
Wait states = 0
Wait states > 0

7.5

(T*WS) + 7.5

--
--

ns
ns

WR Asserted to D0D15 Out Valid

WRD

T + 4.2

Data Out Hold Time from WR Deasserted

DOH

4.8

Data Out Set Up Time to WR Deasserted
Wait states = 0
Wait states > 0

DOS

2.2

(T*WS) + 6.4

--
--

ns
ns

RD Deasserted to Address Not Valid

RDA

Address Valid to RD Deasserted
Wait states = 0
Wait states > 0

ARDD

18.7

(T*WS) + 18.7

ns
ns

Input Data Hold to RD Deasserted

DRD

RD Assertion Width
Wait states = 0
Wait states > 0

(T*WS) + 19

--
--

ns
ns

Address Valid to Input Data Valid
Wait states = 0
Wait states > 0

--
--

(T*WS) + 1

ns
ns

Address Valid to RD Asserted

ARDA

-4.4

RD Asserted to Input Data Valid
Wait states = 0
Wait states > 0

RDD

--
--

2.4

(T*WS) + 2.4

ns
ns

WR Deasserted to RD Asserted

WRRD

6.8

RD Deasserted to RD Asserted

RDRD

WR Deasserted to WR Asserted

WRWR

14.1

RD Deasserted to WR Asserted

RDWR

12.8

56F826 Technical Data

MOTOROLA

3.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Table 14. Reset, Stop, Wait, Mode Select, and Interrupt Timing

1, 5

Operating Conditions:

SSIO

= V

SSA

= 0V, V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, T

= 40

° to +85°C, C

50pF, f

= 80MHz

In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.

Characteristic

Symbol

Min

Max

Unit

See

Figure

RESET Assertion to Address, Data and Control
Signals High Impedance

RAZ

Figure 16

Minimum RESET Assertion Duration

OMR Bit 6 = 0
OMR Bit 6 = 1

Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
· After power-on reset
· When recovering from Stop state

275,000T

128T

--
--

ns
ns

Figure 16

RESET Deassertion to First External Address Output

RDA

33T

34T

Figure 16

Edge-sensitive Interrupt Request Width

IRW

1.5T

Figure 17

IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine

IDM

15T

Figure 18

IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine

16T

Figure 18

IRQA Low to First Valid Interrupt Vector Address Out

recovery from Wait State

The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state.

This is not the minimum required so that the IRQA interrupt is accepted.

IRI

13T

Figure 19

IRQA Width Assertion to Recover from Stop State

The interrupt instruction fetch is visible on the pins only in Mode 3.

Parameters listed are guaranteed by design.

Figure 20

Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1

--
--

275,000T

12T

ns
ns

Figure 20

Duration for Level Sensitive IRQA Assertion to Cause
the Fetch of First IRQA Interrupt Instruction (exiting
Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1

IRQ

--
--

275,000T

12T

ns
ns

Figure 21

Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1

--
--

275,000T

12T

ns
ns

Figure 21

Serial Peripheral Interface (SPI) Timing

MOTOROLA

56F826 Technical Data

3.9 Serial Peripheral Interface (SPI) Timing

1.Parameters listed are guaranteed by design.

Table 15. SPI Timing

Operating Conditions:

SSIO

= V

SSA

= 0V, V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, T

= 40

° to +85°C, C

50pF, f

= 80MHz

Characteristic

Symbol

Min

Max

Unit

See Figure

Cycle time
Master
Slave

50
25

--
--

ns
ns

Figures

Enable lead time
Master
Slave

ELD

--
--

ns
ns

Figure

Enable lag time
Master
Slave

ELG

100

--
--

ns
ns

Figure

Clock (SCLK) high time
Master
Slave

24
12

--
--

ns
ns

Figures

Clock (SCLK) low time
Master
Slave

24.1

--
--

ns
ns

Figures

Data set-up time required for inputs
Master
Slave

--
--

ns
ns

Figures

Data hold time required for inputs
Master
Slave

0
2

--
--

ns
ns

Figures

Access time (time to data active from high-impedance state)
Slave

4.8

Figure

Disable time (hold time to high-impedance state)
Slave

3.7

15.2

Figure

Data Valid for outputs
Master
Slave (after enable edge)

--
--

4.5

20.4

ns
ns

Figures

Data invalid
Master
Slave

0
0

--
--

ns
ns

Figures

Rise time
Master
Slave

--
--

11.5
10.0

ns
ns

Figures

Fall time
Master
Slave

--
--

9.7
9.0

ns
ns

Figures

56F826 Technical Data

MOTOROLA

3.10 Synchronous Serial Interface (SSI) Timing

Table 16. SSI Master Mode

Switching Characteristics

Operating Conditions:

SSIO

= V

SSA

= 0V, V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, T

= 40

° to +85°C, C

50pF, f

= 80MHz

Master mode is internally generated clocks and frame syncs

Parameter

Symbol

Min

Typ

Max

Units

STCK frequency

Max clock frequency is IP_clk/4 = 40MHz / 4 = 10MHz for an 80MHz part.

MHz

STCK period

All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in

SCSR) and a non-ionverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the
frame sync have been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame
sync STFS/SRFS in the tables and in the figures.

SCKW

100

STCK high time

SCKH

50% duty cycle

STCK low time

SCKL

Output clock rise/fall time (STCK, SRCK)

Delay from STCK high to STFS (bl) high - Master

bl = bit length; wl = word length

TFSBHM

0.1

0.5

Delay from STCK high to STFS (wl) high - Master

TFSWHM

0.1

0.5

Delay from SRCK high to SRFS (bl) high - Master

RFSBHM

0.6

1.3

Delay from SRCK high to SRFS (wl) high - Master

RFSWHM

0.6

1.3

Delay from STCK high to STFS (bl) low - Master

TFSBLM

-1.0

-0.1

Delay from STCK high to STFS (wl) low - Master

TFSWLM

-1.0

-0.1

Delay from SRCK high to SRFS (bl) low - Master

RFSBLM

-0.1

Delay from SRCK high to SRFS (wl) low - Master

RFSWLM

-0.1

STCK high to STXD enable from high impedance - Master

TXEM

STCK high to STXD valid - Master

TXVM

STCK high to STXD not valid - Master

TXNVM

0.1

0.2

STCK high to STXD high impedance - Master

TXHIM

25.5

SRXD Setup time before SRCK low - Master

SRXD Hold time after SRCK low - Master

Synchronous Operation (in addition to standard internal clock parameters)

SRXD Setup time before STCK low - Master

TSM

SRXD Hold time after STCK low - Master

THM

Synchronous Serial Interface (SSI) Timing

MOTOROLA

56F826 Technical Data

Figure 26. Master Mode Timing Diagram

Table 17. SSI Slave Mode

Switching Characteristics

Operating Conditions: V

SSIO

= V

SSA

= 0V, V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, T

= 40

° to +85°C, C

50pF, f

= 80MHz

Parameter

Symbol

Min

Typ

Max

Units

STCK frequency

MHz

STCK period

SCKW

100

STCK high time

SCKH

STCK low time

SCKL

Output clock rise/fall time

TBD

Delay from STCK high to STFS (bl) high - Slave

TFSBHS

0.1

Delay from STCK high to STFS (wl) high - Slave

TFSWHS

0.1

THM

TSM

RFSWLM

RFSWHM

RFBLM

RFSBHM

TXHIM

TXNVM

TXVM

TXEM

TFSWLM

TFSWHM

TFSBLM

TFSBHM

SCKL

SCKW

SCKH

First Bit

Last Bit

STCK output

STFS (bl) output

STFS (wl) output

STXD

SRCK output

SRFS (bl) output

SRFS (wl) output

SRXD

56F826 Technical Data

MOTOROLA

Delay from SRCK high to SRFS (bl) high - Slave

RFSBHS

0.1

Delay from SRCK high to SRFS (wl) high - Slave

RFSWHS

0.1

Delay from STCK high to STFS (bl) low - Slave

TFSBLS

-1

Delay from STCK high to STFS (wl) low - Slave

TFSWLS

-1

Delay from SRCK high to SRFS (bl) low - Slave

RFSBLS

-46

Delay from SRCK high to SRFS (wl) low - Slave

RFSWLS

-46

STCK high to STXD enable from high impedance - Slave

TXES

STCK high to STXD valid - Slave

TXVS

STFS high to STXD enable from high impedance (first bit) -
Slave

FTXES

5.5

STFS high to STXD valid (first bit) - Slave

FTXVS

STCK high to STXD not valid - Slave

TXNVS

STCK high to STXD high impedance - Slave

TXHIS

28.5

SRXD Setup time before SRCK low - Slave

SRXD Hold time after SRCK low - Slave

Synchronous Operation (in addition to standard external clock parameters)

SRXD Setup time before STCK low - Slave

TSS

SRXD Hold time after STCK low - Slave

THS

Slave mode is externally generated clocks and frame syncs

Max clock frequency is IP_clk/4 = 40MHz / 4 = 10MHz for an 80MHz part.

All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0

in SCSR) and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the
frame sync have been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame
sync STFS/SRFS in the tables and in the figures.

4. 50%

duty

cycle

bl = bit length; wl = word length

Table 17. SSI Slave Mode

Switching Characteristics (Continued)

Operating Conditions: V

SSIO

= V

SSA

= 0V, V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, T

= 40

° to +85°C, C

50pF, f

= 80MHz

Parameter

Symbol

Min

Typ

Max

Units

Quad Timer Timing

MOTOROLA

56F826 Technical Data

Figure 27. Slave Mode Clock Timing

3.11 Quad Timer Timing

Table 18. Timer Timing

1, 2

Operating Conditions:

SSIO

= V

SSA

= 0V, V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, T

= 40

° to +85°C, C

50pF, f

= 80MHz

In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns.

Parameters listed are guaranteed by design.

Characteristic

Symbol

Min

Max

Unit

Timer input period

4T+6

Timer input high/low period

INHL

2T+3

Timer output period

OUT

Timer output high/low period

OUTHL

THS

TSS

RFSWLS

RFSWHS

RFBLS

RFSBHS

TXHIS

TXNVS

FTXVS

TXVS

FTXES

TXES

TFSWLS

TFSWHS

TFSBLS

TFSBHS

SCKL

SCKW

SCKH

First Bit

Last Bit

STCK input

STFS (bl) input

STFS (wl) input

STXD

SRCK input

SRFS (bl) input

SRFS (wl) input

SRXD

56F826 Technical Data

MOTOROLA

3.12 Serial Communication Interface (SCI) Timing

Figure 29. RXD Pulse Width

Figure 30. TXD Pulse Width

Figure 28. Quad Timer Timing

Table 19. SCI Timing

Operating Conditions:

SSIO

= V

SSA

= 0V, V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, T

= 40

° to +85°C, C

50pF, f

= 80MHz

Characteristic

Symbol

Min

Max

Unit

Baud Rate

1. f

MAX

is the frequency of operation of the system clock in MHz.

MAX

*2.5)/(80)

Mbps

RXD

Pulse Width

The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.

RXD

0.965/BR

1.04/BR

TXD

Pulse Width

The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.

Parameters listed are guaranteed by design.

TXD

0.965/BR

1.04/BR

Timer Inputs

Timer Outputs

INHL

OUT

OUTHL

RXD

SCI receive

data pin

(Input)

RXD

TXD

SCI receive

data pin

(Input)

TXD

JTAG Timing

MOTOROLA

56F826 Technical Data

3.13 JTAG Timing

Table 20. JTAG Timing

1, 3

Operating Conditions:

SSIO

= V

SSA

= 0V, V

DDA

DDIO

=3.03.6V, V

= 2.252.75V, T

= 40

° to +85°C, C

50pF, f

= 80MHz

Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz

operation, T = 12.5ns.

Characteristic

Symbol

Min

Max

Unit

TCK frequency of operation

TCK frequency of operation must be less than 1/8 the processor rate.

Parameters listed are guaranteed by design.

MHz

TCK cycle time

100

TCK clock pulse width

TMS, TDI data set-up time

0.4

TMS, TDI data hold time

1.2

TCK low to TDO data valid

26.6

TCK low to TDO tri-state

23.5

TRST assertion time

TRST

DE assertion time

Figure 31. Test Clock Input Timing Diagram

TCK

(Input)

= V

+ (V

)/2

56F826 Technical Data

MOTOROLA

Part 4 Packaging

4.1 Package and Pin-Out Information 56F826

This section contains package and pin-out information for the 100-pin LQFP configuration of the 56F826.

Figure 35. Top View, 56F826 100-pin LQFP Package

PIN 1

PIN 26

PIN 51

PIN 76

TMS

TDI

TDO

TRST

VDDIO

VSSIO

A15
A14
A13
A12

A11

A10

A9
A8
A7
A6
A5
A4

VSS

VDD

A3
A2
A1
A0

EXTBOOT

ORIENTATION

MARK

VDDIO

VSSIO

IREQ

RESET

GPIOD1
GPIOD0
GPIOB7
GPIOB6
GPIOB5

GPIOB4
GPIOB3
GPIOB2
GPIOB1
GPIOB0
CLKO
VDD
VSS
XTAL
EXTAL
VSSA
VDDA
VSSIO

VDDIO
STCK
STFS
STD
SRCK
SRFS
SRD

TCK

TCS

TXD0

RXD0

VSS

VDD

TXD1

RXD1

SCLK

GPI

VSSIO

VDDIO

GPI

Motorola

56F826

56F826 Technical Data

MOTOROLA

Table 21. 56F826 Pin Identification by Pin Number

Pin No.

Signal

Name

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

Signal

Name

TMS

SRD

GPIOD2

TDI

SRFS

GPIOD3

TDO

SRCK

GPIOD4

TRST

STD

GPIOD5

DDIO

STFS

DDIO

SSIO

STCK

SSIO

A15

IRQA

DDIO

GPIOD6

A14

IRQB

SSIO

GPIOD7

A13

DDA

SCLK

A12

SSA

MOSI

A11

EXTAL

MISO

A10

XTAL

TA3

TA2

CLKO

TA1

GPIOB0

TA0

GPIOB1

RXD1

GPIOB2

TXD1

D10

GPIOB3

RESET

GPIOB4

D11

GPIOB5

RXD0

D12

GPIOB6

TXD0

D13

GPIOB7

D14

GPIOD0

TCS

EXTBOOT

D15

GPIOD1

100

TCK

Package and Pin-Out Information 56F826

MOTOROLA

56F826 Technical Data

Figure 36. 100-pin LQPF Mechanical Information

NOTES:
1.

DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

CONTROLLING DIMENSION: MILLIMETER.

DATUM PLANE -AB- IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING
LINE.

DATUMS -T-, -U-, AND -Z- TO BE DETERMINED
AT DATUM PLANE -AB-.

DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE -AC-.

DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT
DATUM PLANE -AB-.

DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.350 (0.014). DAMBAR CAN NOT BE LOCATED
ON THE LOWER RADIUS OR THE FOOT.
MINIMUM SPACE BETWEEN PROTRUSION
AND AN ADJACENT LEAD IS 0.070 (0.003).

MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.003).

EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.

SEATING

(24X PER SIDE)

GAUGE PLANE

DETAIL AD

SECTION AE-AE

96X

DIM

MIN

MAX

MIN

MAX

INCHES

MILLIMETERS

A 13.950 14.050

0.549

0.553

13.950 14.050

0.549

0.553

1.400

1.600

0.055

0.063

0.170

0.270

0.007

0.011

1.350

1.450

0.053

0.057

0.170

0.230

0.007

0.009

0.500 BSC

0.020 BSC

0.050

0.150

0.002

0.006

0.090

0.200

0.004

0.008

0.500

0.700

0.020

0.028

12 REF

0.090

0.160

0.004

0.006

0.150

0.250

0.006

0.010

15.950 16.050

0.628

0.632

V 15.950 16.050

0.628

0.632

0.200 REF

0.008 REF

1.000 REF

0.039 REF

CASE 842F-01

-T-

T-U

0.15(0.006)

T-

(0.

006

)

T-

(0.

)

-U-

T-U

0.15(0.006)

-Z-

-AC-

PLANE

-AB-

T-U

0.20(0.008)

0.100(0.004) AC

0.25 (0.010)

56F826 Technical Data

MOTOROLA

Part 5 Design Considerations

5.1 Thermal Design Considerations

An estimation of the chip junction temperature, T

, in

°C can be obtained from the equation:

Equation 1:

Where:

= ambient temperature °C

= package junction-to-ambient thermal resistance °C/W

= power dissipation in package

Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and
a case-to-ambient thermal resistance:

Equation 2:

Where:

= package junction-to-ambient thermal resistance °C/W

= package junction-to-case thermal resistance °C/W

= package case-to-ambient thermal resistance °C/W

is device-related and cannot be influenced by the user. The user controls the thermal environment to

change the case-to-ambient thermal resistance, R

. For example, the user can change the air flow around

the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the
heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device
thermal performance may need the additional modeling capability of a system level thermal simulation tool.

The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the
package is mounted. Again, if the estimations obtained from R

do not satisfactorily answer whether the

thermal performance is adequate, a system level model may be appropriate.

Definitions:

A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:

Measure the thermal resistance from the junction to the outside surface of the package (case) closest
to the chip mounting area when that surface has a proper heat sink. This is done to minimize
temperature variation across the surface.

Measure the thermal resistance from the junction to where the leads are attached to the case. This
definition is approximately equal to a junction to board thermal resistance.

(

)

Electrical Design Considerations

MOTOROLA

56F826 Technical Data

Use the value obtained by the equation (T

)/P

where T

is the temperature of the package

case determined by a thermocouple.

The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that
the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple
junction and over about 1mm of wire extending from the junction. The thermocouple wire is placed flat
against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.

When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface
between the case of the package and the interface material. A clearance slot or hole is normally required in
the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal
performance caused by removing part of the thermal interface to the heat sink. Because of the experimental
difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate
the case temperature using a separate measurement of the thermal resistance of the interface. From this case
temperature, the junction temperature is determined from the junction-to-case thermal resistance.

5.2 Electrical Design Considerations

Use the following list of considerations to assure correct operation:

Provide a low-impedance path from the board power supply to each V

DD,

DDIO,

and V

DDA

pin on

the hybrid controller, and from the board ground to each V

SS,

SSIO,

and V

SSA

(GND) pin.

The minimum bypass requirement is to place 0.1

µF capacitors positioned as close as possible to the

package supply pins. The recommended bypass configuration is to place one bypass capacitor on
each of the V

pairs, including V

DDA

SSA

and V

DDIO

SSIO.

Ceramic and tantalum

capacitors tend to provide better performance tolerances.

Ensure that capacitor leads and associated printed circuit traces that connect to the chip V

DD,

DDIO,

and V

DDA

and V

SS,

SSIO,

and V

SSA

(GND) pins are less than 0.5 inch per capacitor lead.

Bypass the V

and V

layers of the PCB with approximately 100

µF, preferably with a high-grade

capacitor such as a tantalum capacitor.

Because the controller's output signals have fast rise and fall times, PCB trace lengths should be
minimal.

CAUTION

This device contains protective circuitry to guard
against damage due to high static voltage or
electrical fields. However, normal precautions are
advised to avoid application of any voltages higher
than maximum rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate voltage level.

DSP56F826/D

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their

How to reach us:
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HOME PAGE: http://www.motorola.com/semiconductors/

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including
"Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the
rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc. Motorola,
Inc. is an Equal Opportunity/Affirmative Action Employer.

Consider all device loads as well as parasitic capacitance due to PCB traces when calculating
capacitance. This is especially critical in systems with higher capacitive loads that could create
higher transient currents in the V

and V

circuits.

Take special care to minimize noise levels on the VREF, V

DDA

and V

SSA

pins.

When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pull-
up device.

Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as
development or debugging systems) should allow a means to assert TRST whenever RESET is
asserted, as well as a means to assert TRST independently of RESET. TRST must be asserted at
power up for proper operation. Designs that do not require debugging functionality, such as
consumer products, TRST should be tied low.

Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide
an interface to this port to allow in-circuit Flash programming.

Part 6 Ordering Information

Table 22

lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales

office or authorized distributor to determine availability and to order parts.

Table 22. 56F826 Ordering Information

Part

Supply

Voltage

Package Type

Pin

Count

Frequency

(MHz)

Order Number

56F826

3.03.6 V

2.25-2.75 V

Plastic Quad Flat Pack (LQFP)

100

DSP56F826BU80

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