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MC68HC812A4EC/D

SEMICONDUCTOR

MOTOROLA

TECHNICAL DATA

PRELIMINARY

7/28/98

Technical Supplement

MC68C812A4 3.3V Electrical Characteristics

The MC68C812A4 is the low-voltage version of the standard MC68HC812A4 microcontroller unit
(MCU), a 16-bit device composed of standard on-chip peripheral modules connected by an intermodule
bus. Modules include a 16-bit central processing unit (CPU12), a Lite integration module (LIM), two
asynchronous serial communications interfaces (SCI0 and SCI1), a serial peripheral interface (SPI), a
timer and pulse accumulation module, an 8-bit analog-to-digital converter (ATD), 1-Kbyte RAM, 4-Kbyte
EEPROM, and memory expansion logic with chip selects, key wakeup ports, and a phase-locked loop
(PLL).

This supplement contains the most accurate electrical information for the MC68C812A4 microcontroller
available at the time of publication. The information should be considered preliminary and is subject to
change. The following characteristics are contained in this document:

Table 1 Maximum Ratings

Table 2 Thermal Characteristics

Table 3 DC Electrical Characteristics

Table 4 Supply Current

Table 5 ATD Maximum Ratings

Table 6 ATD DC Electrical Characteristics

Table 7 Analog Converter Characteristics (Operating)

Table 8 ATD AC Characteristics (Operating)

Table 9 EEPROM Characteristics

Table 10 Control Timing

Table 11 Peripheral Port Timing

Table 12 Non-Multiplexed Expansion Bus Timing

Table 13 SPI Timing

MOTOROLA

MC68C812A4

PRELIMINARY

NOTES:

1. Permanent damage can occur if maximum ratings are exceeded. Exposures to voltages or cur-

rents in excess of recommended values affects device reliability. Device modules may not operate
normally while being exposed to electrical extremes.

2. Refer to MC68HC812A4TS/D Technical Summary for complete part numbers.
3. One pin at a time, observing maximum power dissipation limits. Internal circuitry protects the in-

puts against damage caused by high static voltages or electric fields; however, normal precautions
are necessary to avoid application of any voltage higher than maximum-rated voltages to this high-
impedance circuit. Extended operation at the maximum ratings can adversely affect device reli-
ability. Tying unused inputs to an appropriate logic voltage level (either GND or V

) enhances

reliability of operation.

NOTES:

1. This is an approximate value, neglecting P

I/O

2. For most applications P

I/O

« P

INT

and can be neglected.

3. K is a constant pertaining to the device. Solve for K with a known T

and a measured P

(at equilibrium). Use

this value of K to solve for P

and T

iteratively for any value of T

Table 1 Maximum Ratings

Rating

Symbol

Value

Unit

Supply voltage

DDA

DDX

0.3 to

6.5

Input voltage

0.3 to

6.5

Operating temperature range

MC68C812A4PV5

to T

0 to

Storage temperature range

stg

55 to

150

Current drain per pin

Excluding V

and V

differential voltage

DDX

6.5

Table 2 Thermal Characteristics

Characteristic

Symbol

Value

Unit

Average junction temperature

)

Ambient temperature

User-determined

Package thermal resistance (junction-to-ambient)

112-pin thin quad flat pack (TQFP)

C/W

Total power dissipation

INT

I/O

Device internal power dissipation

INT

I/O pin power dissipation

I/O

User-determined

A constant

273

W ·

273

--------------------------

MC68C812A4

MOTOROLA

PRELIMINARY

NOTES:

1. Specification is for parts in the 0 to

C range. Higher temperature ranges will result in increased current

leakage.

Table 3 DC Electrical Characteristics

3.3 Vdc

0.3V, V

0 Vdc, T

to T

, unless otherwise noted

Characteristic

Symbol

Min

Max

Unit

Input high voltage, all inputs

0.7

0.3

Input low voltage, all inputs

0.3

0.2

Output high voltage

All I/O and output pins

Normal drive strength
I

10.0

0.8 mA

Reduced drive strength
I

4.0

0.3 mA

0.2

0.8

0.2

0.8

--
--

V
V

Output low voltage, All I/O and output pins, normal drive strength

10.0

1.6 mA

EXTAL, PAD[7:0], V

, V

, XIRQ, reduced drive strength

3.6

0.6 mA

--
--

0.2

0.4

0.2

0.4

V
V

Input leakage current

all inputs except IRQ, PAD7, and XFC

or V

IRQ, PAD7, XFC

--
--

Three-state leakage, I/O ports, BKGD, and RESET

2.5

Input capacitance

All input pins and ATD pins (non-sampling)
ATD pins (sampling)
All I/O pins

--
--
--

10
15
20

pF
pF
pF

Output load capacitance

All outputs except PS[7:4]
PS[7:4]

--
--

130

pF
pF

Active pull-up, pull-down current

IRQ, XIRQ, ECLK, LSTRB, R/W , BKGD, MODA, MODB, ARST
Ports A, B, C, D, F, G, H, J, S, T

APU

500

RAM standby voltage, power down

2.0

RAM standby current

MOTOROLA

MC68C812A4

PRELIMINARY

Note: I

is tested with a rail-to-rail square wave on EXTAL

NOTES:

1. Includes I

and I

DDA

Table 4 Supply Current

3.3 Vdc

0.3V, V

0 Vdc, T

to T

, unless otherwise noted

Characteristic

Symbol

4 MHz

5 MHz

Unit

Maximum total supply current

RUN:

Single-chip mode

Expanded mode

15
21

17
25

mA
mA

WAIT: (All peripheral functions shut down)

Single-chip mode

Expanded mode

IDD

3
3

3.5
3.5

mA
mA

STOP:
Single-chip mode, no clocks

IDD

250

Maximum power dissipation

Single-chip mode

Expanded mode

54
76

62
90

mW
mW

Table 5 ATD Maximum Ratings

Characteristic

Symbol

Value

Units

ATD reference voltage

DDA

SSA

0.3 to

6.5

0.3 to

6.5

V
V

differential voltage

SSA

0.1

differential voltage

DDA

DDX

6.5
6.5

V
V

REF

differential voltage

6.5

Reference to supply differential voltage

DDA

SSA

6.5
6.5

V
V

MC68C812A4

MOTOROLA

PRELIMINARY

NOTES:

1. Accuracy is guaranteed at V

3.3 Vdc

0.3V

2. To obtain full-scale, full-range results, V

SSA

INDC

DDA

3. Maximum leakage occurs at maximum operating temperature. Current decreases by ap-

proximately one-half for each 10

C decrease from maximum temperature.

Table 6 ATD DC Electrical Characteristics

3.3 Vdc

0.3V, V

0 Vdc, T

to T

, ATD Clock

2 MHz, unless

otherwise noted

Characteristic

Symbol Min

Max

Unit

Analog supply voltage

DDA

3.0

3.6

Analog supply current

Normal operation

DDA

1.0

Reference voltage, low

SSA

DDA

Reference voltage, high

DDA

REF

differential reference voltage

3.0

3.6

Input voltage

INDC

SSA

DDA

Input current, off channel

OFF

100

Reference supply current

REF

250

Input capacitance

Not Sampling

Sampling

INN

INS

10
15

pF
pF

MOTOROLA

MC68C812A4

PRELIMINARY

NOTES:

1. V

3.072V

2. At V

REF

3.072V, one 8-bit count = 12 mV.

3. Eight-bit absolute error of 2 counts (24 mV) includes 1/2 count (6 mV) inherent quantization error and 1 1/2

counts (18 mV) circuit (differential, integral, and offset) error.

4. Maximum source impedance is application-dependent. Error resulting from pin leakage depends on junction

leakage into the pin and on leakage due to charge-sharing with internal capacitance.
Error from junction leakage is a function of external source impedance and input leakage current. Expected error
in result value due to junction leakage is expressed in voltage (V

ERRJ

OFF

where I

OFF

is a function of operating temperature. Charge-sharing effects with internal capacitors are a function of

ATD clock speed, the number of channels being scanned, and source impedance. For 8-bit conversions, charge
pump leakage is computed as follows:

ERRJ

.25pF

DDA

ATDCLK/(8

number of channels)

Table 7 Analog Converter Characteristics (Operating)

3.3 Vdc

0.3V, V

0 Vdc, T

to T

, ATD Clock

2 MHz, unless otherwise noted

Characteristic

Symbol

Min

Typical

Max

Unit

8-bit resolution

2 counts

Differential non-linearity

DNL

0.5

count

Integral non-linearity

INL

count

Absolute error

2,3

2, 4, 8, and 16 ATD sample clocks

count

Maximum source impedance

See note

Table 8 ATD AC Characteristics (Operating)

3.3 Vdc

0.3V, V

0 Vdc, T

to T

, ATD Clock

2 MHz, unless

otherwise noted

Characteristic

Symbol Min

Max

Unit

ATD operating clock frequency

ATDCLK

0.5

2.0

MHz

Conversion time per channel

0.5 MHz

ATDCLK

2 MHz

18 ATD clocks
32 ATD clocks

CONV

9.0

16.0

32.0
60.0

Stop recovery time

DDA

3.3V

MC68C812A4

MOTOROLA

PRELIMINARY

NOTES:

1. RC oscillator must be enabled if programming is desired and f

SYS

PROG

Table 9 EEPROM Characteristics

3.3 Vdc

0.3V, V

0 Vdc, T

to T

, unless otherwise noted

Characteristic

Symbol Min

Typical

Max

Unit

Minimum programming clock frequency

PROG

3.0

MHz

Programming time

PROG

Clock recovery time following STOP, to continue programming

CRSTOP

PROG

Erase time

ERASE

Write/erase endurance

10,000

30,000

cycles

Data retention

years

Table 10 Control Timing

Characteristic

Symbol 5.0

MHz

Unit

Min

Max

Frequency of operation

5.0

MHz

E-clock period

cyc

200

Crystal frequency

XTAL

10.0

MHz

External oscillator frequency

10.0

MHz

Processor control setup time

PCSU

cyc

PCSU

130

Reset input pulse width

To guarantee external reset vector
Minimum input time (can be preempted by internal reset)

RSTL

--
--

cyc

Mode programming setup time

MPS

cyc

Mode programming hold time

MPH

Interrupt pulse width, IRQ, edge-sensitive mode, KWU

IRQ

cyc

IRQ

420

Wait recovery startup time

WRS

cyc

Timer pulse width, input capture pulse accumulator input

TIM

cyc

TIM

420

MOTOROLA

MC68C812A4

PRELIMINARY

Figure 3 STOP Recovery Timing Diagram

IRQ

STOPDELAY

IRQ

or XIRQ

ECLK

1ST

ADDRESS

SP-9

FREE

VECTOR

FREE

Resume program with instruction which follows the STOP instruction.

I
NTERNAL

ADDRESS

STOP RECOVERY TIM

CLOCKS

NOTES:

1. Edge Sensitive

IRQ

pin (IRQE bit = 1)

2. Level sensitive

IRQ

pin (IRQE bit = 0)

3. t

STOPDELAY

= 4098 t

cyc

if DLY bit = 1 or 2 t

cyc

if DLY = 0.

4. XIRQ

with X bit in CCR = 1.

5. IRQ

or (

XIRQ

with X bit in CCR = 0).

OPT

1ST

2ND

3RD

1ST

EXEC

PIPE

EXEC

SP-8

SP-6

FETCH

PIPE

SP-6

SP-8

SP-9

MC68C812A4

MOTOROLA

PRELIMINARY

Figure 6 Port Read Timing Diagram

Figure 7 Port Write Timing Diagram

Table 11 Peripheral Port Timing

Characteristic

Symbol 5.0

MHz

Unit

Min

Max

Frequency of operation (E-clock frequency)

5.0

MHz

E-clock period

cyc

200

Peripheral data setup time

MCU read of ports

PDSU

cyc

PDSU

130

Peripheral data hold time

MCU read of ports

PDH

Delay time, peripheral data write

MCU write to ports

PWD

PORT RD TIM

ECLK

MCU READ OF PORT

PORTS

PDSU

PDH

PORT WR TIM

ECLK

MCU WRITE TO PORT

PREVIOUS PORT DATA

NEW DATA VALID

PORT A

PWD

MOTOROLA

MC68C812A4

PRELIMINARY

NOTES:

1. All timings are calculated for normal port drives.
2. This characteristic is affected by clock stretch.

Add N

cyc

where N = 0, 1, 2, or 3, depending on the number of clock stretches.

Table 12 Non-Multiplexed Expansion Bus Timing

3.3 Vdc

0.3V, V

0 Vdc, T

to T

, unless otherwise noted

Num

Characteristic

Delay

Symbol

5 MHz

Unit

Min

Max

Frequency of operation (E-clock frequency)

5.0

MHz

Cycle time

cyc

200

Pulse width, E low

cyc

delay

Pulse width, E high

cyc

delay

Address delay time

cyc

delay

Address hold time

Address valid time to E rise

Read data setup time

DSR

Read data hold time

DHR

Write data delay time

DDW

cyc

delay

DDW

Write data hold time

DHW

Write data setup time

DSW

DDW

DSW

Read/write delay time

RWD

cyc

delay

RWD

Read/write valid time to E rise

RWV

RWD

RWV

Read/write hold time

RWH

Low strobe delay time

LSD

cyc

delay

LSD

Low strobe valid time to E rise

LSV

LSD

LSV

Low strobe hold time

LSH

Address access time

ACCA

cyc

DSR

ACCA

100

Access time from E rise

ACCE

DSR

ACCE

Chip select delay time

CSD

cyc

delay

CSD

Chip select access time

ACCS

cyc

CSD

DSR

ACCS

100

Chip select hold time

CSH

Chip select negated time

CSN

cyc

delay

CSN

MOTOROLA

MC68C812A4

PRELIMINARY

NOTES:

1. All AC timing is shown with respect to 20% V

and 70% V

levels unless otherwise noted.

Table 13 SPI Timing

3.3 Vdc

0.3V

, V

0 Vdc, T

to T

, 130 pF load on all SPI pins

Num

Function

Symbol

Min

Max

Unit

Operating Frequency

Master
Slave

DC
DC

E-clock

frequency

SCK Period

Master
Slave

sck

2
2

256

cyc

Enable Lead Time

Master
Slave

lead

--
--

sck

cyc

Enable Lag Time

Master
Slave

lag

--
--

sck

cyc

Clock (SCK) High or Low Time

Master
Slave

wsck

cyc

128 t

cyc

ns
ns

Sequential Transfer Delay

Master
Slave

--
--

sck

cyc

Data Setup Time (Inputs)

Master
Slave

30
30

--
--

ns
ns

Data Hold Time (Inputs)

Master
Slave

--
--

ns
ns

Slave Access Time

cyc

Slave MISO Disable Time

dis

cyc

Data Valid (after SCK Edge)

Master
Slave

--
--

50
50

ns
ns

Data Hold Time (Outputs)

Master
Slave

0
0

--
--

ns
ns

Rise Time

Input
Output

--
--

cyc

ns
ns

Fall Time

Input
Output

--
--

cyc

ns
ns

MC68C812A4

MOTOROLA

PRELIMINARY

A) SPI Master Timing (CPHA = 0)

B) SPI Master Timing (CPHA = 1)

Figure 9 SPI Timing Diagram (1 of 2)

SPI MASTER CPHA0

SCK

(OUTPUT)

SCK

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

MSB IN

BIT 6

. . .

LSB IN

MSB OUT

LSB OUT

BIT 6

. . .

(CPOL

output mode (DDS7 = 1, SSOE = 1).

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

SPI MASTER CPHA1

SCK

(OUTPUT)

SCK

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

MSB IN

BIT 6

. . .

LSB IN

MASTER MSB OUT

MASTER LSB OUT

BIT 6

. . .

PORT DATA

(CPOL

PORT DATA

(OUTPUT)

output mode (DDS7 = 1, SSOE = 1).

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

MOTOROLA

MC68C812A4

PRELIMINARY

A) SPI Slave Timing (CPHA

B) SPI Slave Timing (CPHA

Figure 10 SPI Timing Diagram (2 of 2)

SPI SLAVE CPHA0

SCK

(INPUT)

SCK

(INPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

(INPUT)

MSB IN

BIT 6

. . .

LSB IN

MSB OUT

SLAVE LSB OUT

BIT 6

. . .

(CPOL

NOTE: Not defined but normally MSB of character just received.

SLAVE

SEE

NOTE

SPI SLAVE CPHA1

SCK

(INPUT)

SCK

(INPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

MSB IN

BIT 6

. . .

LSB IN

MSB OUT

SLAVE LSB OUT

BIT 6

. . .

SEE

(CPOL

(INPUT)

NOTE: Not defined but normally LSB of character just received.

SLAVE

NOTE

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Document Outline

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