This document details all known silicon errata for the MPC755 and MPC745. Table 1 provides
a revision history for this chip errata document.
Table 2 describes the devices to which the errata in this document apply and provides a
cross-reference to match the revision code in the processor version register to the revision
level marked on the part.
Table 3 summarizes all known errata and lists the corresponding silicon revision level to
which it applies. A `Y' entry indicates the erratum applies to a particular revision level, while
a `--' entry means it does not apply.
Table 1. Document Revision History
Document Revision
Significant Changes
Revs. 01
Earlier releases of document
Rev. 2
Added Errors 6 and 7
Table 2. Revision Level to Part Marking Cross-Reference
MPC755
Revision
Part Marking
Processor Version
Register
1.0
0008 3100
1.1
0008 3101
2.0
0008 3200
2.7
D
0008 3202
2.8
E
0008 3203
Advance Information
MPC755CE/D
Rev. 2, 6/2002
MPC755 RISC
Microprocessor
Chip Errata
2
MPC755 RISC Microprocessor Chip Errata
MOTOROLA
T
a
b
le
3.
Summar
y of Silicon Errata and Applicab
le Re
vision
No.
Pr
ob
lem
Description
Impact
W
ork Ar
ound
Present in
V
e
r
sion:
1.0
1.1
2.
x
1
V
OL
TDET in 360 BGA
connected to
V
DD
The
V
O
L
TDET is connected to
V
DD
r
ather than L2O
V
DD
in the 360 BGA
pac
kage
.
Cannot use this signal to set
v
oltage ref
erence f
or SRAM
I/O
(if required).
Use alter
nativ
e ref
erence
.
Y
Y
N
2
L2ZZ pin incorrectly activ
e
lo
w
The L2ZZ pin in PB2 mode is
incorrectly made an activ
e lo
w signal.
Cannot use this f
eature to put
the SRAMs into a ZZ po
w
er
sa
ving mode
.
Do not connect the L2ZZ pin to
the SRAM.
YN
N
3
System b
us inoper
ab
le in
PLL b
ypass mode
.
In PLL b
ypass mode
, incorrect data
ma
y be sampled from the system b
us
interf
ace
.
Cannot r
un the processor at
system b
us speeds
.
None e
xists
.
Y
Y
N
4
Additional BA
T registers
non-functional
Hits in the added BA
T registers ma
y
not disab
le
TLB inter
actions
.
Ne
w
f
eature
.
Use the standard 4 IBA
T and 4
DBA
T registers only
.
YY
N
5
L2ZZ pin alw
a
ys lo
w
The L2ZZ pin w
as tied lo
w as a
w
o
r
karound f
or err
ata 2.
PB2:
Cannot use this f
eature
to put the SRAMs into a ZZ
po
w
er mode dur
ing sleep
.
PB3:
Cannot use as ADS
pin
f
or this type of SRAM.
PB2:
Use L2CR cloc
k stop bit
f
or same lo
w po
w
e
r
.
PB3:
None e
xists
.
NYN
6
L2 address par
ity does not
wo
r
k
.
Incorrect par
ity ma
y be gener
ated
when wr
iting a cache line to the L2,
causing a subsequent par
ity error
when the cache line is read.
L2 address par
ity cannot be
used.
None
Y
Y
Y
7
Single-beat,
cache-inhibited stores
discarded in L2 test mode
.
Single-beat, cache-inhibited stores
are discarded and do not propagate
to the system b
us when L2 test
suppor
t mode is enab
led.
Systems requir
ing the ability
to perf
or
m single-beat
cache-inhibited stores while
in L2 test mode ma
y
e
xper
ience memor
y
corr
uption or system hangs
.
1.
Use Pr
iv
ate Memor
y mode
to test L2 cache
.
OR
2.
Configure cache-inhibited
space as wr
ite-through
(WIMG=11xx) if tr
ansactions
m
ust propagate to system b
u
s
YYY
MOTOROLA
MPC755 RISC Microprocessor Chip Errata
3
Error No. 1:
VOLTDET in 360 BGA package connected to V
DD
Overview:
The VOLTDET signal is connected to V
DD
rather than L2OV
DD
in the 360 BGA package.
Detailed Description:
The VOLTDET signal of the MPC755 (360 BGA) is intended to indicate the voltage level present
at the L2 cache interface as a reference for SRAM I/O. In affected devices, however, this signal is
internally connected to V
DD
rather than L2OV
DD
.
Projected Impact:
This signal cannot be used to set the voltage reference for SRAM I/O (if required).
Work Arounds:
An alternative reference may be used.
Projected Solution:
Fixed in MPC755 Rev. 2.0
4
MPC755 RISC Microprocessor Chip Errata
MOTOROLA
Error No. 2:
L2ZZ pin incorrectly active low
Overview:
The L2ZZ pin in PB2 mode is incorrectly made an active low signal.
Detailed Description:
The L2ZZ pin should be an active high output used to enable low-power mode for L2 memory
devices supporting this feature. In affected devices, however, this signal is erroneously an active
low output.
Projected Impact:
Cannot use this feature to put the SRAMs into a power-saving mode.
Work Around:
Do not use low-power mode feature of SRAM.
Projected Solution:
Fixed in MPC755 Rev. 1.1
MOTOROLA
MPC755 RISC Microprocessor Chip Errata
5
Error No. 3:
System bus inoperable in PLL bypass mode.
Overview:
In PLL bypass mode, the system bus may be inoperable.
Detailed Description:
In PLL-bypass mode, incorrect data may be captured from 60x bus interface, causing
processor hangs and data corruption.
Projected Impact:
Cannot operate in PLL bypass mode.
Work Arounds:
None
Projected Solution:
Fixed in MPC755 Rev. 2.0
6
MPC755 RISC Microprocessor Chip Errata
MOTOROLA
Error No. 4:
Additional BAT registers non-functional
Overview:
Hits in the added BAT registers may not disable TLB interactions.
Detailed Description:
During address translation, BAT registers are checked first. If an effective address hits in a BAT,
the TLB should be ignored. In affected devices, however, an effective address that hits in one of
the additional BAT registers will still propagate to the TLB, causing incorrect device behavior.
Projected Impact:
Additional BAT registers cannot be used.
Work Arounds:
Use the standard 4 IBAT and 4 DBAT registers only.
Projected Solution:
Fixed in MPC755 Rev. 2.0
MOTOROLA
MPC755 RISC Microprocessor Chip Errata
7
Error No. 5:
L2ZZ pin always low
Overview:
The L2ZZ pin is internally tied low.
Detailed Description:
The L2ZZ pin should be an active high output used to enable low-power mode for L2 memory
devices supporting this feature. In affected devices, however, this signal is erroneously tied low.
Projected Impact:
PB2: Cannot use this feature to put the SRAMs into a low-power mode during sleep.
PB3: Cannot use as ADS pin for this type of SRAM.
Work Arounds:
None
Projected Solution:
Fixed in MPC755 Rev. 2.0
8
MPC755 RISC Microprocessor Chip Errata
MOTOROLA
Error No. 6:
L2 address parity does not work
Overview:
L2 address parity generation does not work correctly.
Detailed Description:
Incorrect parity may be generated when writing a cache line to the L2 cache. Because the correct
algorithm is used when checking parity for a read, a parity error occurs when the cache line is
subsequently read.
Projected Impact:
L2 address parity cannot be used.
Work Arounds:
None
Projected Solution:
Under review
MOTOROLA
MPC755 RISC Microprocessor Chip Errata
9
Error No. 7:
Single-beat, cache-inhibited stores discarded in L2 test
mode.
Overview:
Single-beat, cache-inhibited stores are discarded when L2CR[L2TS] is set.
Detailed Description:
Single-beat, cache-inhibited stores are discarded and do not propagate to the system bus when L2
test support mode is enabled.
Projected Impact:
Systems requiring the ability to perform single-beat cache-inhibited stores while in L2 test mode
may experience memory corruption or system hangs.
Work Around:
1. Use Private Memory mode to test the L2 cache.
OR
2. Configure cache-inhibited space as write-through (WIMG=11xx) if transactions must propagate
to system bus while in L2 test support mode. These settings are not defined in the architecture but
are useful to overcome this erratum.
Projected Solution:
Under review
10
MPC755 RISC Microprocessor Chip Errata
MOTOROLA
THIS PAGE INTENTIONALLY LEFT BLANK
MOTOROLA
MPC755 RISC Microprocessor Chip Errata
11
MPC755CE/D
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