MC68160A

MOTOROLA ANALOG IC DEVICE DATA

Enhanced Ethernet Serial Transceiver

Table 1. Pin Descriptions

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Controller Interface Pins

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AUI Interface Pins

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Twisted Pair Interface Pins

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Oscillator and Frequency Multiplier Pins

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Mode Select Pins

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Status Indicator Pins

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Power Supply and Ground Pins

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Table 2. Controller Interface Selection

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Table 3. Controller Independent Mode Selection

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Electrical Characteristics

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Maximum Ratings

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Recommended Operating Conditions

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ESD

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DC Characteristics

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Power Supply DC Characteristics

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TTL/CMOS Input and Output DC Characteristics

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Twisted Pair Input and Output DC Characteristics

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AUI Input and Output DC Characteristics

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AC Characteristics

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External Clock Input (X1) Switching Characteristics

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Receive Phase Locked Loop Switching Characteristics

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Controller Transmit Switching Characteristics (Motorola Mode)

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Controller Receive Switching Characteristics (Motorola Mode)

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Controller Transmit Switching Characteristics (Intel Mode)

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Controller Receive Switching Characteristics (Intel Mode)

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Controller Transmit Switching Characteristics (Fujitsu Mode)

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Controller Receive Switching Characteristics (Fujitsu Mode)

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Controller Transmit Switching Characteristics (National Mode)

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Controller Receive Switching Characteristics (National Mode)

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TP Transmit Switching Characteristics

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TP Transmit Jabber Switching Characteristics

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TP Transmit Signal Quality Error Test Switching Characteristics

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TP Receive Switching Characteristics

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TP Receive Link Integrity Switching Characteristics

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TP Collision Switching Characteristics

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TP Full Duplex Switching Characteristics

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AUI Transmit Switching Characteristics

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AUI Receive Switching Characteristics

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Functional Description

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Data Transmission

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Data Reception

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Collision

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Jabber

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Full Duplex

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Auto Port Selection

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Auto Polarity Selection

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Loop Back Mode

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Applications

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Selection of Crystal and External Components

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PLL Filter Components

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10BASET Filter and Transformer Choice

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AUI Transformer Choice

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MC68160A

MOTOROLA ANALOG IC DEVICE DATA

Table 1. Pin Function Descriptiont

Pin(s)

Symbol

Type

Name/Function

CONTROLLER INTERFACE

RENA

TTL/CMO

Receive Enable Output: Indication of the presence of network activity, synchronous to
RCLK. In the standby mode, RENA is driven to the high impedance state.

TTL/CMOS

Receive Data Output: Recovered data, synchronous to RCLK. Following a reset operation,
100 ms should be allowed before attempting to read data processed by the MC68160A, B
and C. This delay is needed to insure that the receive phase locked loop is properly
synchronized with incoming data. In the standby mode, RX is driven to the high impedance
state.

TCLK

TTL/CMOS

Transmit Clock Output CMOS/TTL Output: TCLK provides a symmetrical clock signal at
10 MHz for reference timing of data to be encoded. In the standby mode, TCLK is driven to
the high impedance state.

TENA

TTL

Transmit Enable Input: Input signal synchronous to TCLK which enables data transmission
on the active port. An internal pulldown resistor is provided so that the input is low under no
connect conditions. (This resistor is removed in the standby mode). If TENA is asserted at
the conclusion of a reset operation, it must first be deasserted and then reasserted before
data transmission can occur. In the standby mode, TENA is driven to the high impedance
state.

RCLK

TTL/CMOS

Receive Clock Output: Recovered clock. In the standby mode, RCLK is driven to the high
impedance state.

CLSN

TTL/CMOS

Collision Output: In the AUI mode, indicates the presence of signals at the ACX+ and
ACX terminals which meet threshold and pulse width requirements. In the TP mode,
indicates simultaneous transmit and receive activity, a heartbeat (SQE Test) signal was
generated, or the jabber timer has expired. In the standby mode, CLSN is driven to the high
impedance state.

TTL

Transmit Data Input: Input signal synchronous to TCLK which provides NRZ serial data to
be Manchester encoded. In the standby mode, TX is driven to the high impedance state.

AUI INTERFACE

21
22

ACX
ACX+

AUI Differential Collision Inputs: These inputs are connected to a pair of internally biased
line receivers consisting of a carrier detect receiver with offset threshold and noise filtering to
detect the line activity. Signals at ACX+/ have no effect on data path functions.

23
24

ARX
ARX+

AUI Differential Receiver Inputs: These inputs are connected to a pair of internally biased
line receivers consisting of a carrier detect receiver with offset threshold and noise filtering to
detect the line activity, and a data receiver with no offset for Manchester Data reception.

25
26

ATX
ATX+

AUI Differential Transmit Outputs : This line pair is intended to operate into terminated
transmission lines. For TX signals meeting setup and hold time to TCLK when TENA is
previously asserted, Manchester encoded data is outputted at ATX+/. When operating into a
78

terminated transmission line, signaling meets the required output levels and skew for

IEEE802.3 drop cables. When the 10BASET port is automatically or manually selected,
the AUI outputs are driven to a low power standby state in which the outputs deliver a
balanced high state voltage.

TWISTED PAIR INTERFACE

31
32

TPRX
TPRX+

Twisted Pair Differential Receiver Inputs: These inputs are connected to a receiver with
Smart Squelch capability which only allows differential receive data to pass as long as the
input amplitude is greater than a minimum signal threshold level and a specific pulse
sequence is received. This assures a good signal to noise ratio while the signal pair is active
by preventing crosstalk and impulse noise conditions from activating the receive function.

36
37

TPTX
TPTX+

Twisted Pair Differential Transmitter Outputs: These lines have predistortion drive
capability and are intended to drive terminated twisted pair transmission lines. When the AUI
port is manually selected, the 10BASET outputs are driven to a low power standby state in
which the outputs deliver a balanced high state voltage. However, when the AUI port is
automatically selected, the 10BASET outputs remain active.

NOTE:

The sense of the controller interface pins will change, depending on the controller selected.

MC68160A

MOTOROLA ANALOG IC DEVICE DATA

Table 1. Pin Function Description (continued)

Pin(s)

Symbol

Type

Name/Function

OSCILLATOR AND FREQUENCY MULTIPLIER

MFILT

Frequency Multiplier Filter Connection Point: An external resistor capacitor filter must be
attached to this pin.

I/C

CMOS

Oscillator Inverter Input and Crystal Connection Point: When connected for crystal
oscillator operation, the frequency of the clock which appears at TCLK is half that of the
crystal oscillator. As an option, instead of connecting to a crystal, X1 may be driven from an
external 20 MHz CMOS compatible clock generator.

O/C

CMOS

Oscillator Inverter Output and Crystal Connection Point: This pin is used only for the
connection of an external crystal and capacitor. It must be left unconnected if X1 is driven by
an external CMOS Clock generator.

MODE SELECT

3
4
5

CS0
CS1
CS2

TTL

Mode Select: The logic states applied to these pins select the appropriate interface for the
desired IEEE802.3 controller or enable the standby mode. When the standby mode is
selected, the MC68160A power supply current is greatly reduced. Additionally, in the standby
mode, all of the controller inputs and outputs are driven to the high impedance state.

LOOP

TTL

Diagnostic Loopback: Asserting this function causes serial NRZ data at the TX input to be
Manchester encoded and then looped back through the Manchester decoder, appearing at
the RX output. This diagnostic loopback function operates independent of Twisted Pair (TP)
or Access Unit Interface (AUI) port connectivity or activity. Neither the TP port nor the AUI
port transmits data from the controller while diagnostic loopback is selected. Likewise, the
controller interface receives data neither from the TP nor the AUI receivers while in this
mode. The polarity fault detection and link integrity functions are not inhibited by the
diagnostic loopback mode. If otherwise enabled, they continue to function. If the twisted pair
port is selected, and TPSQEL is driven to the low logic state, a collision detect pulse is
delivered following each transmission to simulate the twisted pair SQE test.

APORT

TTL

Automatic Port Selection Enable: When high, MC68160A will automatically select the TP
or AUI port based on the presence or absence of valid link beats or frames at the TP receive
input. If the AUI port is automatically selected, the MC68160A will continue to produce link
pulses for the TP port. Changing ports requires approximately 1.0 ms to allow the circuitry for
the new port to resume normal operation. The power consumption is minimized in the
circuitry associated with the unselected port.

TPSQEL

TTL

Twisted Pair Signal Quality Error Test Enable: Forcing this pin low enables testing of the
internal TP collision detect circuitry after each transmit operation to the TP media. This
function provides a simulated collision to as much of the MC68160A collision detect circuitry
as possible without affecting the attached twisted pair channel. A normal SQE test results in
a high logic state at the CLSN controller interface pin which begins 6 to 16bit times after the
last transition of a transmitted signal and continues for 5 to 15bit times. (When the AUI port
is selected, SQE test signals are generated by the coaxial cable transceiver and delivered to
the controller via the MC68160A ACX+/ receive inputs)

TPFULDL

TTL

Twisted Pair Full Duplex Mode Select: Forcing this pin low allows simultaneous transmit
and receive operation on the twisted pair port without an indicated collision. This pin is not to
be asserted with LOOP as a test mode is enabled that disrupts normal operation.

TPAPCE

TTL

Twisted Pair Automatic Polarity Correction Enable: When TPAPCE is high, automatic
polarity correction is enabled, and MC68160A will internally correct for a polarity fault on the
receive circuit. Additionally, when TPAPCE is high, the presence of a polarity fault is
indicated on TPPLR.

TPEN

I/O

TTL

(TTL/CMOS)

Twisted Pair Port Enable: If APORT is low, TPEN is an input which determines whether the
AUI port (TPEN low) or TP port (TPEN high) will be manually selected. If the AUI port is
manually selected, the MC68160A will not produce link pulses for the TP port.

If APORT is high, TPEN is an output which will indicate which port has been automatically
selected by driving TPEN low (for AUI) or high (for TP). In its output mode TPEN can sink
10 mA in the low output state and source 10 mA in the high output state. (See Pin 9
Description.)

Changing ports requires approximately 1.0 ms to allow the circuitry for the new port to
resume normal operation. The power consumption is minimized in the circuitry associated
with the unselected port. In the standby mode, this pin is driven to the high impedance state.

MC68160A

MOTOROLA ANALOG IC DEVICE DATA

Table 1. Pin Function Description (continued)

Pin(s)

Symbol

Type

Name/Function

STATUS INDICATOR

TXLED

TTL/CMOS

Transmit Status LED Driver Output: This pin indicates the transmit status of the currently
selected TP or AUI port. When there is no transmit activity detected, an internal pullup takes
this pin to its normal off (high) state. When transmit activity is detected, the LED driver turns
on. In its on state, TXLED flashes the LED by driving low at approximately 10 Hz at a 50%
duty cycle. In the standby mode, this output is driven to the high impedance state.

RXLED

TTL/CMOS

Receive Status LED Driver Output: This pin indicates the receive status of the currently
selected TP or AUI port. When there is no receive activity detected, an internal pullup takes
this pin to its normal off (high) state. When receive activity is detected, the LED driver turns
on. In its on state, RXLED flashes the LED by driving low at approximately 10 Hz at a 50%
duty cycle. In the standby mode, this output is driven to the high impedance state.

CLLED

TTL/CMOS

Collision Status LED Driver Output: This pin indicates the collision status of the currently
selected TP or AUI port. When there is no collision activity detected, an internal pullup takes
this pin to its normal off (high) state. When collision activity is detected, the LED driver turns
on. In its on state, CLLED flashes the LED by driving low at approximately 10 Hz at a 50%
duty cycle. In the standby mode, this output is driven to the high impedance state.

TPLIL

TTL/CMOS

Twisted Pair Link Integrity Output: This output is driven to the low output state to indicate
good link integrity on the TP port during TP mode. It is deasserted (high) when link integrity
fails in TP mode. The TPLIL output is driven to the high impedance state when the AUI port
is selected. In the standby mode, this output is also driven to the high impedance state.

TPPLR

TTL/CMOS

Twisted Pair Polarity Error Output: If TPAPCE is high and the wires connected to the
Twisted Pair Receiver Inputs (TPRX+, TPRX) are reversed, TPPLR will be driven to the low
logic state to indicate the fault. TPPLR remains low when the MC68160A, AB and AC has
automatically corrected for the reversed wires. If the twisted pair link integrity tests fail, this
output will be driven to the high logic state. When the AUI mode is selected this output is
driven to the high impedance state. In the standby mode, this output is also driven to the high
impedance state.

TPJABB

TTL/CMOS

Twisted Pair Jabber Output: This pin is driven high to indicate a jabber condition at the
TPTX+/ outputs. (Jabber condition also causes CLLED to be driven alternately to the high
and low output levels). TPJABB is driven to the low output state when no jabber condition is
present. When the AUI mode is selected this output is driven to the high impedance state. In
the standby mode, this output is also driven to the high impedance state.

POWER SUPPLY AND GROUND

VDDDIV

Frequency Divider Supply Pin

VDDFM

GNDFM

Frequency Multiplier Supply and Ground Pins

14
15

GNDVCO

VDDVCO

Voltage Controlled Oscillator Ground and Supply Pins

GNDSUB

Substrate Ground Pin

7
8

18
19

VDDDIG

GNDDIG

VDDDIG

GNDDIG

Digital Supply and Ground Pins

30
33

VDDANA

GNDANA

Analog Supply and Ground Pins

34
35
38
39

GNDPWR

VDDPWR
VDDPWR

GNDPWR

Power Supply and Ground Pins

GNDCTL

Controller Interface Ground Pin

NOTE:

Power and ground pins are not connected internally. Failure to connect externally may cause malfunction or damage to the IC.

MC68160A

MOTOROLA ANALOG IC DEVICE DATA

Table 2. Controller Interface Selection

Motorola

Transceiver

MC68160A

(EEST

)

Motorola

Controller2

MC68360

(QUICC

)

Intel4

Controllers

82586, 82590,

82593, 82596

Fujitsu4

Controllers

86950 (Etherstar

)

86960 (NICE

)

National4

Controllers

8390, 83C690,

83932B (SONIC

)

CS0
CS1
CS2

1
1
0

0
1
0

1
0
0

0
0
0

Pin

Sense

Pin

Sense

Pin

Sense

Pin

Sense

TCLK

High

TXC

Low

TCKN

Low

TXC

High

TXD

High

TXD

High

TXD

High

TENA

High

RTS

Low

TEN

High

TXE

High

RCLK

High

RXC

Low

RCN

Low

RXC

High

RXD

High

RXD

High

RXD

High

RENA

High

CRS

Low

XCD

High

CRS

High

CLSN

High

CDT

Low

XCOL

Low

COL

High

LOOP1

N.A.

High

LPBK

Low

LBC

High

LPBK

High

NOTES: 1. Although LOOP input is not ordinarily classifed as a controller pin, it is included in this table because its sense varies according to the controller used.

2. The Motorola controller interface contained in the MC68360 (QUICC

) is compatible with the AMD 7990 (LANCE

) and 79C900 (ILACC

) controllers.

3. The pin sense is shown from the perspective of the identified controller pin.
4. Supported only by MC68160A.

Table 3. Controller Independent Mode Selection

Pin

Standby Mode

Reserved

CS0
CS1
CS2

1
1
1

0
1
1

1
0
1

0
0
1

NOTE: In standby mode, the MC68160A consumes less power supply current than in any other

mode. Additionally, in the standby mode, all of the controller inputs and outputs are
driven to the high impedance state. When the standby mode is deasserted, an internal
reset pulse of approximately 6.0

s duration is generated.

Following a period of operation in the standby mode, the time required to insure stable
data reception is approximately 100 ms.

TPTX+

TPTX

TPRX+

TPRX

ATX+

ACX

ACX+

ATX

ARX+

ARX

TCLK

TENA

RCLK

RENA

CLSN

TPTX+

TPRX+

TPRX

TPTX

ACX

ACX+

ARX

ARX+

ATX

ATX+

Figure 2. Applications Block Diagram

Pulse

Transformers

DB15

Connector

Filters

and

Pulse

Transformers

RJ45

Connector

LAN

Controller

MC68160A

MC68160A

MOTOROLA ANALOG IC DEVICE DATA

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Characteristic

Symbol

Min

Max

Unit

Storage Temperature Range

Tstg

150

Power Supply Voltage Range

Analog
Digital

VDDA
VDDD

7.0
7.0

Voltage on any TTL compatible input pin with

respect to Ground

Voltage on TPRX, ARX, or ACX input pins with

respect to Ground

0.5

VDD + 0.5

6.0

Differential Voltage on TPRX, ARX, or ACX Input

Pins

VDIFF

6.0

NOTE:

Stresses in excess of the Absolute Maximum Ratings can cause permanent damage to the
device. Functional operation of the device is not implied at these or any other conditions in
excess of those indicated in the operation sections of this data sheet. Exposure to Absolute
Maximum Ratings conditions for extended periods can adversely affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Characteristic

Symbol

Min

Max

Unit

Power Supply Voltage Range

VDD

4.75

5.25

Power Supply Ripple (20 kHz to 100 kHz)

Power Supply Impulse Noise (Either Polarity)

100

Ambient Operating Temperature Range

ARX/ACX Input Differential Rise and Fall Time (see Figure 39)

t260

2.0

ARX Pair Idle Time after Transmission (see Figure 39)

t265

8.0

ESD

Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge
(ESD) during handling and mounting. Motorola employs a Human Body Model (HBM) and a Charged Device Model (CDM) for ESDsusceptibility
testing and protection design evaluation. ESD has been adopted for the CDM, however, a standard HBM (resistance = 1500

capacitance

100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using
the circuit parameters contained in this specification. ESD threshold voltage is designed to 700 V Human Body Model.

DC ELECTRICAL CHARACTERISTICS

(Unless otherwise noted, minimum and maximum limits apply over the recommended

ambient operating temperature and power supply voltage ranges.)

Characteristic

Symbol

Test Conditions

Min

Typ

Max

Unit

POWER SUPPLY

Undervoltage Shutdown Threshold

4.4

Power Supply Current

IDD

Standby Mode

145

200

5.0

MC68160A

MOTOROLA ANALOG IC DEVICE DATA

DC ELECTRICAL CHARACTERISTICS

(TA = 25

C, VCC = 5.0 V

5%. Unless otherwise noted, minimum and maximum

limits apply over the recommended ambient operating temperature and power supply voltage ranges for each MC68160A except where noted.)

Characteristic

Symbol

Test Conditions

Min

Max

Unit

TTL COMPATIBLE INPUTS

TTL Compatible Input Voltage

Low State
High State

VIL(TTL)

VIH(TTL)

2.0

0.8

Input Current TTL Compatible Input Pins (Note 1)
Input Current TENA TTL Compatible Input Pin:

with PullDown Resistor

IIH
IIL

with PullDown Resistor removed in Standby Mode

IIH

IIL

IIH & IIL

0 V < VI < VDD

+200

CMOS COMPATIBLE INPUTS

CMOS Compatible Input Voltage

Low State
High State

VIL(CMOS)

VIH(CMOS)

3.0

1.0

Input Current (Pin X1)

IIH & IIL

0 V < VI < VDD

100

TTL/CMOS COMPATIBLE OUTPUTS

TTL/CMOS Compatible Output Voltage

Low State (Note 2)
Low State (Note 3)

VOL

IOL = 4.0 mA

IOL = 10 mA

0.45
0.45

TTL/CMOS Compatible Output Voltage

High State (Note 4)
High State (Note 5)
High State (Note 2)

VOH

IOH = 500

IOH = 10 mA

IOH = 4.0 mA

3.9
3.9
2.4

Three State Output Leakage Current

IOZ

0 V

VOZ

VDD

Characteristic

Symbol

Test Conditions

Min

Max

Unit

TWISTED PAIR RECEIVER INPUTS

Input Voltage Range (DC + AC)

VITP

1.5

4.3

Differential Input Squelch Threshold Voltage

VITPSQ

Note 10

270

390

Common Mode Bias Generator Voltage

VBCMTP

Note 9

1.8

3.2

Common Mode Input Resistance

RCMTP

1000

Differential Input Resistance

RDIFFTP

2.5

TWISTED PAIR TRANSMITTER OUTPUTS

Differential Output Voltage

PreEmphasis Level
Signal Level

VODFTPP
VODFTPS

Note 7

2.2

1.56

2.8

1.98

Common Mode Output Voltage Range

VOCMTP

Note 6

4.0

Common Mode Output Voltage in Standby Mode

VOCMTPSB

IOH = 100

VDD 1.0

VDD

NOTES: 1. APORT, TPAPCE, CS0, CS1, CS2, TX, LOOP, TPFULDL, TPSQEL and TPEN (In Input Mode).

2. TCLK, RX, RCLK, RENA and CLSN.
3. TPPLR, TPLIL, TPJABB, TXLED, RXLED, CLLED and TPEN (In Output Mode).
4. TPPLR, TPLIL, CLLED, TXLED and RXLED.
5. TPJABB and TPEN (In Output Mode).
6. Measured with Test Load B1 (shown in Figure 3), applied directly to the TPTX+/ pins of the device.
7. Measured differentially with Test Load B2 (shown in Figure 4), applied directly to the TPTX+/ pins of the device.
8. Measured directly on the TPTX+/ pins of the device.
9. Measured with Test Load B3 (shown in Figure 5), applied directly to the TPRX+/ pins of the device.

10. The Common Mode Input Voltage is between 1.8 V and 3.2 V.

MC68160A

MOTOROLA ANALOG IC DEVICE DATA

DC ELECTRICAL CHARACTERISTICS

(continued) (TA = 25

C, VCC = 5.0 V

5%. Unless otherwise noted, minimum and maximum

limits apply over the recommended ambient operating temperature and power supply voltage ranges for each MC68160A except where noted.)

Characteristic

Symbol

Test Conditions

Min

Max

Unit

TWISTED PAIR TRANSMITTER OUTPUTS

Differential Output Voltage

IDLE Mode
Open Circuit

VODFTPI

VODFTPO

Note 6
Note 8

5.25

Differential Output Impedance

TRANSMISSION Mode
IDLE Mode

RODFTPT

RODFTPI

Note 8

8.0

28
29

Common Mode Output Impedance

TRANSMISSION Mode
IDLE Mode

ROCMTPT

ROCMTPI

Note 8

3.0
1.0

7.0

NOTES: 1. APORT, TPAPCE, CS0, CS1, CS2, TX, LOOP, TPFULDL, TPSQEL and TPEN (In Input Mode).

10. The Common Mode Input Voltage is between 1.8 V and 3.2 V.

DC ELECTRICAL CHARACTERISTICS

(Unless otherwise noted, minimum and maximum limits apply over the recommended

ambient operating temperature and power supply voltage ranges.)

Characteristic

Symbol

Test Conditions

Min

Max

Unit

AUI RECEIVER INPUTS

Input Voltage Range (DC + AC)

VIA

1.0

4.2

Differential Mode Input Voltage Range

VIDFA

318

1315

Differential Input Squelch Threshold Voltage

VIASQ

275

175

Common Mode Input Resistance

RICMA

1.0 V < VICMA < 4.2 V

1.5

Differential Input Resistance (ARX, ACX Inputs)

RIDFA

1.0 V < VICMA < 4.2 V

318 mV < VIDMA < 1315 mV

5.0

AUI TRANSMITTER OUTPUTS

Common Mode Output Voltage

IDLE Mode
ACTIVE Mode
STANDBY Mode

VOCMIA

VOCMAA
VOCMSA

Figure 6

IO = 100

1.0
1.0

VDD 2.0

4.2
4.2

VDD 1.2

Differential Output Voltage

IDLE Mode
ACTIVE Mode

VODFIA

VODFAA

Figure 6

600

1315

Differential Output Load Current

IDLE Mode

IODFIA

Figure 7

4.0

Output Short Circuit Current

IODSA

Output Short Circuited to

VDD or GND

150

MC68160A

MOTOROLA ANALOG IC DEVICE DATA

TP TRANSMIT SWITCHING

Characteristic

Symbol

Min

Typ

Max

Unit

TPTX Common Mode AC Output Voltage (Note 3)

VOCMTP

mVrms

TX to TPTX Steady State Propagation Delay (Note 2) (See Figure 24)

Bit Duration CentertoCenter
HalfBit Cell Duration CentertoBoundary

t130
t131
t132

98
48

200
102

TENA Assert to RENA Assert Delay (Note 7) (See Figure 24)

t133

400

Internal Loopback Delay from TX to RX (Note 7) (See Figure 24)

t134

650

TPTX End of Packet Hold Time from last positive TPTX Signal Edge to

+585 mV Differential Output Level (Note 5) (See Figure 25)

t135

250

400

TPTX Precompensation Pulse Width (Notes 2 and 6) (See Figure 25)

t136

4558

RENA Deassert Delay from TENA Deassert when Receiver is inactive

Motorola Mode
Fujitsu Mode
National Mode
Intel Mode (Note 4) (See Figure 26)

t137
t137
t137
t138

250
250
250
250

450
450
450
450

TPTX DatatoLink Test Pulse (Note 2) (See Figure 27)
TPTX Link Test Pulse Width (Note 2)
TPTX Link Test Pulse DecaytoIdle Condition (Note 1)
TPTX Link Test Pulse to next Link Test Pulse (Note 2)

t139
t140
t141
t142

8.0

80
80

8.0

240
240

ns
ns

NOTES: 1. Measured differentially across the output of Test Load A which is connected directly to the TPTX+/ pins of the device.

2. Measured differentially across the output of Test Load D shown in Figure 23 which is connected directly to the TPTX+/ pins of the device.
3. Measured across the output of Test Load C which is connected directly to the TPTX+/ pins of the device.
4. Same as t137 except the logic states for TENA and RENA are inverted.

5. Measured across the output of Test Load B shown in Figure 21.
6. Measured at the +/90% points of the precompensation voltage feature of the waveform. (The 0% reference is 0 V differential.)
7. Load on specified output is 20 pF to ground.

100

Device

1.0

100pF

VOUT

100

200

47.5

49.9

VCM

200

100

VOUT

NOTE:

A total of 50

per driver output is required for proper series line termination.

This is realized with the 39

external resistors shown in Figures 20 to 23,

together with the internal driver output resistance.

Vout

Figure 20. Test Load A

Figure 21. Test Load B

Figure 22. Test Load C

Figure 23. Test Load D

MC68160A

MOTOROLA ANALOG IC DEVICE DATA

AUI TRANSMIT SWITCHING

Characteristic

Symbol

Min

Typ

Max

Unit

TCLK to ATX Pair Steady State Propagation Delay

t240

100

Output Differential Rise and Fall Times (Measured directly at device pins)

t241

1.0

5.0

ATX Bit Cell Duration centertocenter (Measured directly at device pins)

t242

99.5100.5

ATX HalfBit Cell Duration centertoboundary (Measured directly at device pins)

t243

49.550.5

ATX Pair Held at Positive Differential at start of Idle (Measured through

transformer)

t244

200

NOTE:

Load on specified output is a shunt 27

H inductor and 83

resistor.

Figure 38. ATX Transmit Timings

TCLK

TENA

ATX+/

Differential

(Logic Levels)

t240

t242

t243

t241

t244

90%

10%

90%

10%

1.5V

70%

AUI RECEIVE SWITCHING

Characteristic

Symbol

Min

Max

Unit

ARX/ACX Differential Input Voltage Range

318

1315

ARX/ACX Differential Input Pulse Width to:

Initiate Data Reception
Inhibit Data Reception

t261
t262

RENA Assertion Delay
RENA Deassertion Delay

t266
t267

100
450

Squelching Characteristics
The receive data pairs and the collision pairs should have the following squelch characteristics:
1. The squelch circuits are on at idle (with input voltage at approximately 0 V differential).
2. If an input is in squelch, pulse is rejected if the peak differential voltage is more positive than 175 mV, regardless of pulse width.
3. A pulse is considered valid if its peak differential voltage is more negative than 300 mV and its width, measured at 285 mV, is > 25 ns.
4. The squelch circuits are disabled by the first valid negative differential pulse on either the AUI receive data or collision pair.
5. If a positive differential pulse occurs on either the AUI receive data or collision pair > 175 ns, end of frame is assumed and squelch circuitry is turned on.

t261/ t262

175mV

+175mV

ARX+/
ACX+/

Differential

Input Voltage

Figure 39. ARX/ACX Timing

MC68160A

MOTOROLA ANALOG IC DEVICE DATA

RENA/CLSN

1.5V

300mV

10%

90%

10%

275mV

+300mV

Bit U

Bit V

Bit W

Bit X

Bit Z

Bit X

Bit Y

Bit Z

Bit U

RCLK

Bit Y

Bit Q

Bit V

Bit U

Bit Q

Figure 40. ARX/ACX Timing

ARX+//

ACX+/

Differential

Input Voltage

t261

t260

t266

t267

40mV

t260

FUNCTIONAL DESCRIPTION

Introduction

The MC68160A was designed to perform the physical

connection to the Ethernet media. This is done through two
separate media dependent interfaces and a SIA interface.
The media dependent interfaces are the Attachment Unit
Interface(AUI) and the 10BASET Twisted Pair(TP) port. The
MC68160A's SIA interface is compatible with most industry
controllers and selected by three mode control pins. Chip
status is supported indicated by the condition of 6 status
indicator pins. All but one are open collector outputs.

If the EEST isn't receiving data, the controller may initiate

transmission. NRZ data from the communications controller
SIA interface is encoded by the MC68160A into Manchester
Code in preparation for transmission on the media. The data
is then applied to either the AUI or TP port. If the data was
transmitted using the 10BASET port, this data is also
looped back to the receive data interface SIA pins
connected to the controller. This allows detection of a
collision condition in the event that another station on the
media attempted transmission at the same time. After the
entire data frame has been transmitted, the EEST must
force the media idle signal. The idle signal frees the media
for other stations that have deferred transmission. If no
other transmissions are required the link enters an idle
state. During this idle state the 10BASET transmitter
issues idle pulses which communicates to the receiver
connected to the other side that the link is valid. If the

transmitter connected at the other end begins transmission,
the EEST will assert a receive enable signal, and forward
the received data to the controller.

Upon reception of data at the 10BASET port, the data is

screened for proper sequence and pulse width requirements.
If the preamble of the received frame meets the
requirements, the PLL locks onto the 64bit preamble and
begins to decode the Manchester Code to NRZ code. This
code is then presented to the communications controller at
the receive data pins at the SIA interface. If data is received
at the AUI port, it is sent directly to the communications
controller via the SIA interface.

Data Transmission

To have properly encoded transmit data, the com

munications controller must be synchronized to TCLK.
Transmission to the 10BASET or AUI media occurs when
TENA is asserted and data is applied to the TX pin. Finally, to
signify transmission, the TXLED in will cycle on and off at a
100 ms period. Data transmission for EEST is accomplished
either over the 10BASET port or the AUI port. Both
connections to the media are made with industry standard
media interface components. The 10BASET interface
requires a filter and transformer, the AUI interface requires
only a transformer. The filter for the 10BASET transmit
circuit will have to be chosen for each application.

MC68160A

MOTOROLA ANALOG IC DEVICE DATA

If after approximately 40 ms after a TP or AUI transmission

has begun, the EEST is still transmitting, the TPJABB pin will
assert to signify a jabber condition. Also, the CLLED pin will
transition high and low alternately with a 100 ms period. The
transmit circuitry is, however, unaffected by the jabber
condition, so the communications controller has the
responsibility of monitoring and stopping transmission.

When transmission is complete, the transmit circuitry will

begin the end of transmit and decay to idle responses
necessary to meet requirements of the 802.3 standard for the
TP and AUI port.

Data Reception

Other than the case of being in Loop Back mode, data

reception to the RX pin of the EEST is initiated by signaling at
the RX+/ or AUI ARX+/ pins. If at the TP port, the data is
screened for validity by checking for sequence and pulse
width requirements, then passed to the decode and receive
circuitry. The RENA pin asserts and the data and
corresponding clock is passed to the communications
controller. After the frame has been transmitted, the
MC68160A detects the ending transmission and negates
RENA. If at the AUI port, the data is checked for proper pulse
width requirements before being passed to the decode
circuitry. If the data pulses are longer than at least 20 ns,
RENA gets asserted and the frame is decoded to RX with
and accompanying RCLK output.

Collision

Collision is the occurrence of simultaneous transmit

activity by two or more stations on the network. In the event of
collision, the data transfer paths are unaffected. If the
MC68160A is in the twisted pair mode, collision is detect by
simultaneous receive and transmit activity. If in the AUI
mode, collision is detected by activity on the ACX+/ pins. In
either case, if collision is detected, the CLSN pin will assert to
notify the communications controller.

Jabber

The EEST has a jabber timer to detect the jabber condition.

In the event that the transmitting station continues to transmit
beyond the allowable transmit time, a jabber timer (40 ms) will

expire and assert the TPJABB pin to alert the communications
controller of the situation. The TPJABB pin can source or sink
up to 10 mA, and so, is capable of driving a status LED. In the
AUI mode, the pin is driven to high impedance since the
transceiver connected to the AUI port must alert the
communications controller of the jabber condition.

Full Duplex

A feature unique to the MC68160A is the Full Duplex

mode. In this mode the EEST is capable of transmitting and
receiving simultaneously. Collision conditions are not
announced and internal loop back is disabled. The remainder
of the EEST functionality remains unchanged from the
nonFull Duplex mode. Full Duplex mode is enabled by
asserting the TPFULDL pin.

Auto Port Selection

If the APORT pin is asserted, the MC68160A will

automatically select the TP or AUI port depending on the
presence of valid link beats or frames at the TP RX+/ pins. If
the AUI port is automatically selected by another transmitting
station or by setting TPEN low, the TP transmit port of the
EEST continues to transmit link beats to keep the link active.

Auto Polarity Selection

If the RX+ and the RX wires happen to get reversed, the

MC68160A has the ability to automatically reverse the pins
internally so that the received data is valid. In addition, an open
collector status pin (TPPLR) is driven low to indicate the fault.
In the AUI or reset mode this pin presents a high impedance.

Loop Back Mode

To test the transmit and receive circuitry without disturbing

the connected network, the EEST has a Loop Back mode.
Loop Back mode routes transmit data and clock to the
receive data and clock pins using as much of the transmit and
receive circuitry as possible. This gives a test of the
MC68160A Manchester encode and decode function. LOOP
must not be asserted when TPFULDL pin is asserted. This
causes the MC68160A to enter a test mode. This test mode
is used during final test and is not intended to be entered
under normal operation (see Application Notes section).

MC68160A

MOTOROLA ANALOG IC DEVICE DATA

APPLICATIONS INFORMATION

Selection of Crystal and External Components

Accuracy of frequency and stability over temperature are

the main determinants of crystal choice. Specifications for a
suitable crystal are tabulated below.

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Frequency

ÁÁÁÁÁ

20.000 MHz

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode

ÁÁÁÁÁ

Fundamental

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Tolerance

ÁÁÁÁÁ

100 ppm

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Stability

ÁÁÁÁÁ

100 ppm

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Aging

ÁÁÁÁÁ

5 ppm/yr

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Shunt Capacitance

ÁÁÁÁÁ

7.0 pF

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Load Capacitance

ÁÁÁÁÁ

1820 pF

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Series Fundamental Resistance (ESR)

ÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Drive Level

ÁÁÁÁÁ

500

A suitable crystal is the MTRON
HC49 MP1, 20.000 MHz crystal.
20 pF for C4 and C5 have been
shown to work reliably.

PLL Filter Components

The filter components at Pin 12 were chosen to assure

adequate pullrange but with a emphasis on stability. It is not
foreseeable that a design would need to change the
components, but for the sake of completeness, relevant
values are provided here.

VCO Gain

MHz

Volt

sec

and,

Phase Detector Gain

100

rad

and the

filter impedance function is;

Z(j

)

[

w )

1 C6)

w )

1 C5)

(for C6

C5)

10BASET Filter and Transformer Choice

The MC68160A differential outputs are low impedance

voltage sources. Therefore, external series resistors must be
used in order to match the characteristic impedance of
twisted pair. Since the output resistance of each leg of the
transmitter is about 10

, a 39

resistor is used in series as

shown in the applications schematic. So the impedance
presented from the source to the isolation transformer is then
very nearly 100

. The following is a list of some 10BASET

filter module vendors and their products.

Vendor

Part #

FEE FilMag

78Z1120B01, 78Z1122B/D01,
78Z1122 F01

Valor Electronics

78Z1122 F01

PT3877, FL1012, FL1066

a o

ec o cs

Pulse Engineering

066

PE65434, PE65424, PE65433

TOKO

PM0100, PM0200, PM0500

AUI Transformer Choice

Like the 10BASET outputs, the AUI differential outputs

are low impedance sources and capable of meeting the IEEE
802.3 waveform requirements when a coupling transformer
is used. Some AUI transformer vendors and their products
are provided below.

Vendor

Part #

Coilcraft

LAXET304

FEE FilMag

23Z90, 23Z91/ 23Z92

Valor Electronics

LT6032, LT6033

Pulse Engineering

PE64502, PE6103

TOKO

Q30ALQ81AA3, Q30ALQ91AA3

Application Notes:

Resetting the MC68160A after power up.
In some applications, after initial power up, the MC68160A

may not be able to transmit or receive data. This is usually
caused by the LOOP and TPFULDL control lines being active
at the same time. This is an illegal condition during normal
operation, it places the MC68160A into the production test
mode.

To exit the test mode and return to normal: Set LOOP low,

TPFULDL high and TPSQEL low. Then, while keeping
TPSQEL low, raise LOOP after 300 ms lower TPFULDL. This
will put the MC68160A into test mode but also resets the
MC68160A. After 500 ms lower LOOP to get out of the test
mode. TPFULDL may then be deasserted if desired.

The MC68160A is now ready for operation.
A hardware implementation of this fix would be to place a

pull down resistor on the TPSQEL pin. Even if test mode is
entered by accident, this ensures that zero's will be written to
the test register. The hardware implementation will solve the
problem if the test mode is entered because of noise on the
TPSQEL pin. If the controller is toggling the MC68160A lines
while it is booting up, the reset procedure must be followed.

MC68160A

MOTOROLA ANALOG IC DEVICE DATA

1. For Suitable Crystal (X ) see applications text on previous page.

0.01 F

ÎÎÎÎÎÎ

TPEN

TCLK

TENA

CLSN

RCLK

RENA

LOOP

APOR

LED6

LED5

LED4

LED3

LED2

LED1

TD +

RD +

CS0

CS1

CS2

802.3 Communication Controller

Motorola

MC68360,

AMD 7990 & 79C900

Intel 82586, 82590, 82593, 82596

Fujitsu MB86950, MB86960

National 8390, 83C690, 83932B

Standby Low Current Mode

Communications Controller Selection

AUI XFMR

(Example of PE-65424)

RCLK

TENA

CLSN

GNDCTL

TPEN

TCLK

TPLIL

CLLED

TPPLR

TXLED

GNDVCO

RXLED

VDDDIG

GNDSUB

ACX

GNDDIG

TPJABB

VDDVCO

ACX+

ARX+

ATX

ARX

ATX+

Figure 41. T

ypical

Application Diagram

Enable

ransmit Clock

ransmit Enable

ransmit Data

Collision Int

Receive Clock

Receive Enable

Receive Data

LoopBack

AutoPort En

+5.0V

Power Supply

Bypassing

COMMUNICA

TIONS

CONTROLLER

MC68360

AMD (7990/79C900)

Intel (825** 86/90/93/96)

Fujitsu (869** 50/60)

National (8390/83C90/83932B)

10 F

0.1 F

TPSQEL

TPFULDL

APCE

300

0.039 F

CTP2

20pF

20MHz

RENA

CS0

CS1

CS2

LOOP

VDDDIG

GNDDIG

APORT

VDDDIV

VDDFM

MFIL

GNDFM

GNDPWR

VDDPWR

TPTX+

TPTX

VDDPWR

GNDPWR

GNDANA

TPRX+

VDDANA

APCE

TPFULDL

TPSQEL

TPRX

0.1 F

330

100

Coilcraft (LAXET30*)

Pulse Engineering (PE64***)

alor (L

T600*/L

T603*)

OKO (Q30ALQ*1AA3)

0.01 F

CTP3

alor (PT3877, PT3882, FL1012, FL1066)

OKO (PM01, PM02, PM05)

Pulse Engineering (PE65433, PE65434, PE65424)

RJ45

+12V

AUI

Figure 41.

MC68160AFB

3900pF

2. Decoupling capacitors should be placed as close to supply pins as possible.

10 K

MC68160A

MOTOROLA ANALOG IC DEVICE DATA

FB SUFFIX

PLASTIC PACKAGE

CASE 848D-03

(LQFP52)

ISSUE C

OUTLINE DIMENSIONS

NOTES:

1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION: MILLIMETER.
3 DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD AND

IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS
THE PLASTIC BODY AT THE BOTTOM OF THE PARTING
LINE.

4 DATUMS L, M AND N TO BE DETERMINED AT DATUM

PLANE H.

5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING

PLANE T.

6 DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010)
PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-.

7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION.

DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD
WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN
PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07
(0.003).

ÉÉÉÉ

ÇÇÇ

VIEW AA

VIEW AA

2 X R

VIEW Y

SECTION ABAB

ROTATED 90

CLOCKWISE

DIM

MIN

MAX

MIN

MAX

INCHES

10.00 BSC

0.394 BSC

MILLIMETERS

5.00 BSC

0.197 BSC

10.00 BSC

0.394 BSC

5.00 BSC

0.197 BSC

1.70

0.067

0.05

0.20

0.002

0.008

1.30

1.50

0.051

0.059

0.20

0.40

0.008

0.016

0.45

0.030

0.22

0.35

0.009

0.014

0.65 BSC

0.75

0.018

0.026 BSC

0.07

0.20

0.003

0.008

0.50 REF

0.020 REF

0.08

0.20

0.003

0.008

12.00 BSC

0.472 BSC

6.00 BSC

0.236 BSC

0.09

0.16

0.004

0.006

12.00 BSC

0.472 BSC

6.00 BSC

0.236 BSC

0.20 REF

0.008 REF

1.00 REF

0.039 REF

X

X=L, M, N

4X TIPS

0.20 (0.008) H LM

0.20 (0.008) T LM

VIEW Y

SEATING
PLANE

0.10 (0.004) T

0.05 (0.002)

0.25 (0.010)

GAGE PLANE

0.13 (0.005)

PLATING

BASE METAL

L

N

M

H

T

REF

MC68160A

MOTOROLA ANALOG IC DEVICE DATA

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals"
must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

Mfax is a trademark of Motorola, Inc.

How to reach us:
USA / EUROPE / Locations Not Listed: Motorola Literature Distribution;

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3142 Tatsumi KotoKu, Tokyo 135, Japan. 81335218315

Mfax

: RMFAX0@email.sps.mot.com TOUCHTONE 6022446609

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US & Canada ONLY 18007741848

51 Ting Kok Road, Tai Po, N.T., Hong Kong. 85226629298

INTERNET: http://www.mot.com/SPS/

MC68160A/D

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