18
MPV3 Series
9x14 mm, 3.3 Volt, LVPECL/LVDS, VCXO
Pin Connections
LVDS and PECL Output Logic With
Good Integrated Jitter Performance
(5 ps)
Phase-Locked Loops (PLL's),
Clock Recovery, Reference Signal
Tracking, Synthesizers, Frequency
Modulation/Demodulation
19
V
C
X
O
1. Stability given for deviation over temperature.
2. PECL load - see load circuit diagram #5 on page 149. LVDS load - see load circuit diagram #9 on page 149.
3. APR specification inclusive of initial tolerance, deviation over temperature, shock, vibration, supply voltage, and aging.
MPV3 Series
9x14 mm, 3.3 Volt, PECL/LVDS, VCXO
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