A D D R E SS

/C M

D Q (150)

(16 )

I/O

C O N T R O L

C A M A R R A Y

W O R D S

X 64 B IT S

C O M PA R A N D

M A SK 1

M A SK 2

I
O

NCO

C O M M A N D S & ST A T U S

M U X

D A T A (16)

D EM U X

SO U R C E A N D
D EST IN A T IO N

SEG M EN T

C O U N T ER S

VC C

G N D

IN ST R U C T IO N (W /O )*

N EXT F R EE A D D R ESS (R /O )

C O N T R O L

SEG M EN T C O N T R O L

A D D R E SS

ST A T U S (150 ) (R /O )*

ST A T U S (3 116) (R / O )

R EG IST ER S ET

M A T C H A D D R , /M F

/M M , /F F

D A T A (16)

(16 )

D A T A (64)

ADDRE

/R ESE T

/M F

/M M

N + 1

/FF

LIST-XL Family

13 June 2001 Rev

13 June 2001 Rev. 2

. 2

Block Diagram

DISTINCTIVE CHARACTERISTICS

Data Sheet

256 word and 512 word by 64-bit content-

256 word and 512 word by 64-bit content-
addressable memory (CAM)

addressable memory (CAM)

Compare any data with all the entries stored in the

Compare any data with all the entries stored in the
memory array in a single 70 ns cycle

memory array in a single 70 ns cycle

Add or delete data in the CAM in a single cycle

Match and Multiple match signals

Immediate access to associated data translations,

Immediate access to associated data translations,
attributes, or pointers

attributes, or pointers

Flexible patented CAM/RAM partitioning

Two selectable mask registers with bit by bit

wo selectable mask registers with bit by bit

capability

Powerful and flexible instruction set

Proximate match capability

16-bit I/O; 32-Pin LQFP; 3.3 volt operation

APPLICA

APPLICATION BENEFITS

TION BENEFITS

Accelerate table search and data translation

Accelerate table search and data translation
operations such as those found in:

operations such as those found in:

LAN Address processing

Cache tag buffers

Hash collision resolution

Branch tables

Data decoders

Other processes or algorithms that require

table searches

LANCAM, the MUSIC logo, and the phrase "MUSIC Semiconductors" are registered trademarks of MUSIC Semiconductors. MUSIC is
a trademark of MUSIC Semiconductors. Certain features of this device are patented under US Patent 5,383,146.

LIST-XL

Rev

Rev. 2

. 2

Skip Bit

Empty Bit

Validity T

alidity T

alidity Type

ype

Valid

Empty

Skip

RAM

Table 1: V

able 1: V

able 1: Validity Bits vs. V

alidity Bits vs. V

alidity Bits vs. Validity T

alidity T

alidity Types

ypes

Pinout Diagram

Table 2: I/O Cycles

able 2: I/O Cycles

LOW

HIGH

/CM

LOW

HIGH

LOW

HIGH

Cycle T

Cycle Type

ype

Command Write Cycle

Data Write Cycle

Command Read Cycle

Data Read Cycle

The MUSIC LIST-XL family consists of 256 word and 512
word by 64-bit content-addressable memory (CAM), ideal
for time critical applications requiring intensive list processing
where space and cost are important.

Content-addressable memories, also known as associative
memories, operate in the converse way to random access
memories (RAM). In a RAM, the input to the device is an
address and the output is the data stored at that address. In a
CAM, the input is a data sample and the output is a flag to
indicate a match and the address of the matching data. As a
result, a CAM searches large databases for matching data in a
short, constant time period, no matter how many entries are in

GENERAL DESCRIPTION

the database. The ability to search data words up to 64 bits
wide allows large address spaces to be searched rapidly and
efficiently. A patented architecture links each CAM entry to
associated data and makes this data available for use after a
successful compare operation.

The MUSIC LIST-XL is an inexpensive powerful solution for
any application having to retrieve or translate data in a fast,
time deterministic manner. It is well suited to handle and speed
up functions usually done in software, such as data caches,
branch tables, LAN address processing, data translations, high
speed data filters, and algorithms having to search, recognize,
and make decisions on data or a data subset.

OPERA

OPERATIONAL

TIONAL

TIONAL OVER

OVER

OVERVIEW

VIEW

To use the LIST-XL, the user loads the data into the
Comparand register, which is automatically compared to all
valid CAM locations. The device then indicates whether or
not one or more of the valid CAM locations contains data
that matches the target data. Two validity bits at each memory
location determines the status of each CAM location. The
two bits are encoded to render four validity conditions: Valid,
Skip, Empty, and Random Access, as shown in Table 1. The
memory can be partitioned into CAM and associated RAM
segments on 16-bit boundaries, but by using one of the two
available mask registers, the CAM/RAM partitioning can be
set at any arbitrary size between zero and 64 bits.

The LIST-XL's internal data path is 64 bits wide for rapid
internal comparison and data movement. Loading data to the
Control, Comparand, and Mask registers automatically triggers

a compare. Compares may also be initiated by a command to
the device. Associated RAM data is available immediately
after a successful compare operation. The Status register reports
the results of compares including all flags and addresses. Two
Mask registers are available and can be used in two different
ways, to mask comparisons or to mask data writes. The random
access validity type (see Table 1) allows additional masks to
be stored in the CAM array where they may be retrieved rapidly.

A simple three-wire control interface and commands
loaded into the Instruction decoder control the device.
A powerful instruction set increases the control flexibility
and minimizes software overhead. These and other
features make the LIST-XL a powerful associative
memory that drastically reduces search delays.

D Q 4

D Q 5

V CC

G ND

D Q 6

D Q 7

G ND

/ R E S E T

V CC

/ E

/F
F

3 2 -p in

6
7

/ M M

/ M F

V CC

/ W

2 4

2 3

2 2

2 1

2 0

1 9
1 8
1 7

32-pin LQFP

(Top V

op V

op View)

iew)

LIST-XL

Rev

Rev. 2

. 2

/E (Chip Enable, Input, TTL)

The /E input enables the device while LOW. The falling
edge registers the control signals /W and /CM. The rising
edge turns off the DQ pins and clocks the Destination and
Source Segment counters. The four cycle types enabled
by /E are shown in Table 2 on page 2.

/W (Write Enable, Input, TTL)

The /W input selects the direction of data flow during a
device cycle. /W LOW selects a Write cycle and /W HIGH
selects a Read cycle.

/CM (Data/Command Select, Input, TTL)

The /CM input selects whether the input signals on
DQ150 are data or commands. /CM LOW selects Command
cycles and /CM HIGH selects Data cycles.

DQ150 (Data Bus, I/O, TTL)

The DQ150 lines convey data, commands, and status to
and from the LIST-XL. /W and /CM controls the direction
and nature of the information that flows to or from the
device. When /E is HIGH, DQ150 go to Hi-Z.

/MF (Match Flag, Output, TTL)

The /MF output goes LOW when one or more valid
matches occur during the current or most recent compare
cycle. /MF is HIGH if there is no match. /MF will be reset
when the active configuration register set is changed.

/MM (Device Multiple Match Flag, Output, TTL)

The /MM output is LOW when more than one valid
match occurs during the current or the most recent
compare cycle. /MM will be reset when the active register
set is changed.

/FF (Full Flag, Output, TTL)

The /FF output goes LOW when no empty memory
locations exist within the device.

/RESET (Reset, Input, TTL)

/RESET must be driven LOW to place the device in a known
state before operation, which will reset the device to the
conditions shown in Table 4 on page 8. The /RESET pin
should be driven by TTL levels, not directly by an RC time-
out. /E must be kept HIGH during /RESET.

VCC, GND (Positive Power Supply

VCC, GND (Positive Power Supply, Ground)

, Ground)

These pins are the power supply connections to the LIST-
XL. VCC must meet the voltage supply requirements in
the Operating Conditions section relative to the GND
pins, which are at 0 Volts (system reference potential),
for correct operation of the device. All the ground and
power pins must be connected to their respective planes
with adequate bulk and high frequency bypassing
capacitors in close proximity to the device.

PIN DESCRIPTIONS

All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash ("/") are active
LOW. Inputs should never be left floating. The CAM architecture draws large currents during compare operations,
mandating the use of good layout and bypassing techniques. Refer to the Electrical Characteristics section for more
information.

LIST-XL

Rev

Rev. 2

. 2

FUNCTIONAL DESCRIPTION

The LIST-XL is a content-addressable memory (CAM)
with 16-bit I/O for network address filtering and
translation, virtual memory, data compression, caching,
and table lookup applications. The memory consists of
static CAM, organized in 64-bit data fields. Each data
field can be partitioned into a CAM and a RAM subfield
on 16-bit boundaries. The contents of the memory can
be randomly accessed or associatively accessed by the
use of a compare. During automatic comparison cycles,
data in the Comparand register is automatically compared
with the "Valid" entries in the memory array. The Device
ID can be read using a TCO PS instruction (see Table 11
on page 16).

The data inputs and outputs of the LIST-XL are
multiplexed for data and instructions over a 16-bit
I/O bus. Internally, data is handled on a 64-bit basis,
since the Comparand register, the mask registers, and
each memory entry are 64 bits wide. Memory entries are
globally configurable into CAM and RAM segments on
16-bit boundaries, as described in US Patent 5,383,146
assigned to MUSIC Semiconductors. Seven different
CAM/RAM splits are possible, with the CAM width
going from one to four segments, and the remaining RAM
width going from three to zero segments. Finer resolution
on compare width is possible by invoking a mask register
during a compare, which does global masking on a bit
basis. The CAM subfield contains the associative data,
which enters into compares, while the RAM subfield
contains the associated data, which is not compared. In
LAN bridges, the RAM subfield could hold, for example,
port-address and aging information related to the
destination or source address information held in the
CAM subfield of a given location. In a translation
application, the CAM field could hold the dictionary
entries, while the RAM field holds the translations, with
almost instantaneous response.

Each entry has two validity bits (known as Skip bit and
Empty bit) associated with it to define its particular type:
empty, valid, skip, or RAM. When data is written to the
active Comparand register, and the active Segment
Control register reaches its terminal count, the contents
of the Comparand register are automatically compared
with the CAM portion of all the valid entries in the
memory array. For added versatility, the Comparand
register can be barrel-shifted right or left one bit at a
time. A Compare instruction can then be used to force
another compare between the Comparand register and
the CAM portion of memory entries of any one of the
four validity types. After a Read or Move from Memory

operation, the validity bits of the location read or moved
will be copied into the Status register, where they can be
read from the Status register using Command Read cycles.

Data can be moved from one of the data registers (CR,
MR1, or MR2) to a memory location that is based on the
results of the last comparison (Highest-Priority Match
or Next Free), or to an absolute address, or to the location
pointed to by the active Address register. Data also can
be written directly to the memory from the DQ bus using
any of the above addressing modes. The Address
register may be directly loaded and may be set to
increment or decrement, allowing DMA-type reading or
writing from memory.

Two sets of configuration registers (Control, Segment
Control, Address, Mask Register 1, and Persistent Source
and Destination) are provided to permit rapid context
switching between foreground and background
activities. Writes, reads, moves, and compares are
controlled by the currently active set of configuration
registers. The foreground set would typically be pre-
loaded with values useful for comparing input data, often
called filtering, while the background set would be pre-
loaded with values useful for housekeeping activities
such as purging old entries. Moving from the foreground
task of filtering to the background task of purging can
be done by issuing a single instruction to change the
current set of configuration registers. The match
condition of the device is reset whenever the active
register set is changed.

The active Control register determines the operating
conditions within the device. Conditions set by this
register's contents are reset, CAM/RAM partitioning,
disable or select masking conditions, and disable or select
auto-incrementing or -decrementing the Address register.
The active Segment Control register contains separate
counters to control the writing of 16-bit data segments
to the selected persistent destination, and to control the
reading of 16-bit data segments from the selected
persistent source.

There are two active mask registers at any one time,
which can be selected to mask comparisons or data
writes. Mask Register 1 has both a foreground and
background mode to support rapid context switching.
Mask Register 2 does not have this mode, but can be
shifted left or right one bit at a time. For masking
comparisons, data stored in the active selected mask
register determines which bits of the comparand are

LIST-XL

Rev

Rev. 2

. 2

compared against the valid contents of the memory. If a
bit is set HIGH in the mask register, the same bit position
in the Comparand register becomes a "don't care" for
the purpose of the comparison with all the memory
locations. During a Data Write cycle or a MOV instruction,
data in the specified active mask register can also
determine which bits in the destination will be updated.
If a bit is HIGH in the mask register, the corresponding
bit of the destination is unchanged.

The match line associated with each memory address is
fed into a priority encoder where multiple responses are
resolved, and the address of the highest-priority
responder (the lowest numerical match address) is
generated. In LAN applications, a multiple response might
indicate an error. In other applications the existence of
multiple responders may be valid.

Three input control signals and commands loaded into an
instruction decoder control the LIST-XL. Two of the three
input control signals determine the cycle type. The control
signals tell the device whether the data on the I/O bus
represents data or a command, and is input or output.
Commands are decoded by instruction logic and control
moves, forced compares, validity bit manipulations, and
the data path within the device. Registers (Control, Segment
Control, Address, Next Free Address, etc.) are accessed
using Temporary Command Override instructions. The data
path from the DQ bus to/from data resources (comparand,
masks, and memory) within the device are set until changed
by Select Persistent Source and Destination instructions.

After a Compare cycle (caused by either a data write to the
Comparand or mask registers, a write to the Control register, or
a forced compare), the Status register contains the address of
the Highest-Priority Matching location, along with flags
indicating match, multiple match, and full. The /MF, /MM, and
/FF flags also are available directly on output pins.

FUNCTIONAL DESCRIPTION

Continued

OPERA

OPERATIONAL

TIONAL

TIONAL CHARACTERISTICS

CHARACTERISTICS

Throughout the following, "aaaH" represents a three-digit
hexadecimal number "aaa," while "bbB" represents a
two-digit binary number "bb." All memory locations are
written to or read from in 16-bit segments. Segment 0
corresponds to the lowest order bits (bits 150) and
Segment 3 corresponds to the highest order bits (bits
6348).

THE CONTROL BUS

Refer to the Block Diagram on page 1 for the following
discussion. The inputs Chip Enable (/E), Write Enable (/W),
and Command Enable (/CM) are the primary control
mechanism for the LIST-XL. Instructions are the secondary
control mechanism. Logical combinations of the Control
Bus inputs, coupled with the execution of Select Persistent
Source (SPS), Select Persistent Destination (SPD), and
Temporary Command Override (TCO) instructions allow the
I/O operations to and from the DQ150 lines to the internal
resources, as shown in Table 3 on page 7.

The Comparand register is the default source and
destination for Data Read and Write cycles. This default
state can be overridden independently by executing a Select
Persistent Source or Select Persistent Destination
instruction, selecting a different source or destination for
data. Subsequent Data Read or Data Write cycles will

access that source or destination until another SPS or SPD
instruction is executed. The currently selected persistent
source or destination can be read back through a TCO PS
or PD instruction. The sources and destinations available
for persistent access are those resources on the 64-bit bus:
Comparand register, Mask Register 1, Mask Register 2, and
the Memory array.

The default destination for Command Write cycles is the
Instruction decoder, while the default source for Command
Read cycles is the Status register.

Temporary Command Override (TCO) instructions provide
access to the Control register, the Segment Control register,
the Address register, and the Next Free Address register.
TCO instructions are active only for one Command Read or
Write cycle after being loaded into the Instruction decoder.

The data and control interfaces to the LIST-XL are
synchronous. During a Write cycle, the Control and Data
inputs are registered by the falling edge of /E. When writing
to the persistently selected data destination, the Destination
Segment counter is clocked by the rising edge of /E. During
a Read cycle, the Control inputs are registered by the falling
edge of /E, and the Data outputs are enabled while /E is
LOW. When reading from the persistently selected data
source, the Source Segment counter is clocked by the rising
edge of /E.

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