Preliminary Data Sheet
MUSIC Semiconductors, the MUSIC logo, and the phrase "MUSIC Semiconductors" are
October 10, 2000 Rev. 2.7 Draft
Registered trademarks of MUSIC Semiconductors. MUSIC and Epoch are trademarks of
MUSIC Semiconductors.
APPLICATIONS
WAN edge routers
MultiService platforms
RAS platforms
Group Switch/Router
DSLAMs
LAN PBX core
FEATURES AND BENEFITS
MultiMedia-ready integrated switch on a chip
Process Layer 3 and Layer 4 of the IP stack
1.4 Million packets/flow classifications per second; full Layer 4 flow recognition
Up to 16 ports supported with powerful flexible built-in parsing function
QoS Support for VoIP and other MultiMedia flows
Differentiated Services per port (DS)
Eight queues per output port enabling efficient MultiMedia integration of voice (VoIP), video, and data
Two scheduling algorithms selectable on a per port basis.
IPv6 and other protocols supported through processor interface
No Head-of-line blocking
Layer 2 switch-through support at wire speed
Firewall assist on a per packet or per flow basis
Flow aging support
DISTINCTIVE CHARACTERISTICS
Wire speed Layer 3/Layer 4 switching for IPv4, IP Multicast, and IPX
Header manipulation and checksum recalculation at wire speeds
Support for Layer 3 CIDR (best prefix match)
Per Flow and per IP or IPX address filtering options
Behavior Aggregate Classification (BAC) and Microflow static/dynamic flow classification
64K default priority assignments with processor override for specific flows
Eight levels of Weighted RR or eight levels of priority
L3 to L2 support for IP to MAC address translation
Destination and/or Source Port monitoring
Generic 32 bit processor interface
66 MHz clock
3.3 Volt power with 5 Volt tolerant I/O pins
IEEE 1149.1 (JTAG) boundary scan logic
456 PBGA Package
Related MUSIC Documentation:
Epoch Host Processor Software Development Manual
MUAC Routing CoProcessor (RCP) Family Data Sheet
AN-N25 Fast IPv4 and IPv4 CIDR Address Translation and Filtering Using the MUAC Routing CoProcessor (RCP)
Application Note
AN-N27 Using MUSIC Devices and RCPs for IP Flow Recognition Application Note
Epoch MultiLayer Switch Chipset
Epoch MultiLayer Switch Chipset
Epoch MultiLayer Switch Chipset
Epoch MultiLayer Switch Chipset
Epoch MultiLayer Switch Chipset
Operational Overview
2
Rev. 2.7 Draft
OPERATIONAL OVERVIEW
The MUSIC Epoch MultiLayer Switch Chip for a Layer
3/4 switch performs all of the functions necessary to route
IPv4, IPX and IP Multicast packets at wire-speed; to
recognize and categorize traffic flows, optionally using
IETF Differentiated Services (DS); and to queue each flow
independently in an associated SDRAM. Upon
transmission, DS information may be remarked. The
Epoch handles up to 16 ports; one port is required for the
processor to allow it to act as a packet source or
destination.
The Epoch chip fits into a system as shown in Figure 1.
The Epoch chip itself is the heart of the system and forms
the basis of a Layer 3/4 switch with up to 16 ports, one of
which is used for the processor to send and receive
packets. Each port has eight queues and a queue scheduler
determines queue service order for each output port. Layer
3 and Layer 4 information are stored in a Routing
CoProcessor (RCP) database. The RCP provides the
packet header processing performance necessary to do true
wire-speed packet-by-packet routing and real-time flow
recognition. The Epoch has a multicast switch fabric that
also can be used for Layer 2 switches and xDSL
multiplexers.
Various SRAM and SDRAM devices are required to store
packet data and internal Epoch control information.
A processor provides non-real-time initialization and
housekeeping functions. A processor also is used to handle
packets destined to the switch and packets not supported
by the Epoch. One processor may be used to handle both
of these functions or separate processors may be used.
The Arbiter controls access to the bidirectional data bus
among the Layer 2 ports, including the processor interface
to the data bus. These components are detailed later.
Figure 1: EPOCH MultiLayer Switch in a System
MUSIC Semiconductors
EPOCH MultiLayer Switch
MUSIC
Semiconductors
MUAC Routing
CoProcessor
4K-32K x 64
MUAC Bus
Arbiter
Processor or
Processors
SDRAM Bus
Arbiter Bus
Data Bus
Control Bus
Processor
Interface
Processor Bus
Processor Bus
Layer 2
Interface(s)
SDRAM Bus
Packet Data
SDRAM
1M x 16 (2x)
Packet
Control
SDRAM
1M x 16
SRAM Bus
Packet
Pointer
SRAM
64K x 32
SRAM Bus
L3/L4
Database
SRAM
128K x 16
Note: Solid boxes denote MUSIC standard products; dashed boxes denote either standard products; dashed boxes denote standard products from other
manufacturers or customer ASICs/FPGAs/PLDs.
Ball Descriptions
Epoch MultiLayer Switch Chipset
Rev. 2.7 Draft
3
BALL DESCRIPTIONS
This section contains ball descriptions. Refer to Figure 2 below and Table 1, Ball Descriptions, on page 4.
Figure 2: PBGA Ball Diagram (Underside View)
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Epoch MultiLayer Switch Chipset
Ball Descriptions
4
Rev. 2.7 Draft
Table 1: Ball Descriptions
Functional
Group
Ball Name(s)
(Appended b
indicates
active low signal)
Function
Type
PBGA Ball(s)
I/O TDM Bus
L2DATA[31:0]
Interface to Layer 2
Devices.
TDM Data Bus.
Transmit and receive data bursts in 64 byte blocks.
Bidir
TTL
5V Tol.
b0:D14, b1:A13, b2:B13,
b3:C13, b4:D13, b5:B12,
b6:C12, b7:D12, b8:A11,
b9:B11, b10:C11, b11:D11,
b12:A10, b13:B10, b14:C10,
b15:D10, b16:A9, b17:B9,
b18:C9, b19:D9, b20:A8,
b21:B8, b22:C8, b23:D8,
b24:A7, b25:B7, b26:C7,
b27:D7, b28:A6, b29:B6,
b30:C6, b31:D6
L2CNTL[7:0]
TDM Control Bus.
Transmit and receive control information.
Bidir
TTL
5V Tol.
b0:D16, b1:A15, b2:B15,
b3:C15, b4:D15, b5:A14,
b6:B14, b7:C14
SYNC
TDM Timeslot. Synchronization Signal. Position is
programmable.
Output
TTL
B17
ABORT
Aborts the current receive packet indication. Assert
for one CLK. May be asserted from the first word of a
receive packet data burst, CLK 4 to CLK 47 of a bus
cycle. Overrides or replaces LASTWORD and
LASTBYTE[1:0].
Input
TTL
D19
L2RXREADYIN
Asserted by L2 device when it has data next slot.
Sampled by Epoch in CLK4.
Input
TTL
5V Tol.
B16
L2TXREADYIN
Asserted by L2 device when it can accept data next
slot.
Sampled by Epoch in CLK4.
Input
TTL
5V Tol.
A16
L2TXREADYOUT
Asserted to L2 device indicating data is available this
slot. Asserted by Epoch in CLK11, de-asserted
CLK30.
Output
TTL
C16
L2LASTWORD
Asserted for one CLK at the CLK of the last word of a
packet in the last buffer of a packet for both TX and
RX packets.
Bidir
TTL
5V Tol.
A17
L2LASTBYTE[1:0]
Indicates the last byte of the last word of a packet for
both TX and RX packets. Encoding is as follows:
Bidir
TTL
5V Tol.
b0:C17, b1:D17
Arbiter Bus
L2NEXTPORT[3:0]
Inputs number of next active port.
Sampled a TDM cycle ahead in CLK2.
Input
TTL
5V Tol.
b0:A18, b1:B18, b2:C18,
b3:D18
31
L2DATA
0
Byte 0
Byte 1
Byte 2
Byte 3
L2LASTBYTE[1:0]
Valid
Invalid
Invalid Invalid
00
Valid
Valid
Invalid Invalid
01
Valid
Valid
Valid
Invalid
10
Valid
Valid
Valid
Valid
11
Ball Descriptions
Epoch MultiLayer Switch Chipset
Rev. 2.7 Draft
5
BFM Data
SDRAM.
Buffer Manager
interface to data
buffer RAM.
BSDRAMD[31:0]
Buffer Data SDRAM
Data Bus
Bidir
TTL
3.3V
Only
b0:F24, b1:F23, b2:E26,
b3:E25, b4:E24, b5:E23,
b6:D26, b7:D25, b8:D24,
b9:C26, b10:C25, b11:A25
b12:A24, b13:B24, b14:A23,
b15:B23, b16:C23, b17:A22,
b18:B22, b19:C22, b20:D22,
b21:A21, b22:B21, b23:C21,
b24:D21, b25:A20, b26:B20,
b27:C20, b28:D20, b29:A19,
b30:B19, b31:C19
BSDRAMA[10:0]
Buffer Data SDRAM
Address Bus
Output
TTL
b0:J23, b1:H26, b2:H25,
b3:H24, b4:H23, b5:G26,
b6:G25, b7:G24, b8:G23,
b9:F26, b10:F25
BSDRAMBS
Buffer Data SDRAM
Bank Select
Output
TTL
J24
BSDRAMRASb
Buffer Data SDRAM
Row Address Strobe
Output
TTL
J26
BSDRAMCASb
Buffer Data SDRAM
Column Address Strobe
Output
TTL
J25
BSDRAMWEb
Buffer Data SDRAM
Write Enable Strobe
Output
TTL
K23
BSDRAMDQM
Buffer Data SDRAM
Data Mask
Output
TTL
K24
BFM Pointer
SDRAM.
Buffer Manager
interface to
pointer RAM.
PSDRAMD[15:0]
Control SDRAM
Data Bus
Bidir
TTL
3.3V
Only
b0:P24, b1:P23, b2:N26,
b3:N25, b4:N24, b5:N23,
b6:M26, b7:M25, b8:M24,
b9:M23, b10:L26, b11:L25,
b12:L24, b13:L23, b14:K26,
b15:K25
PSDRAMA[10:0]
Control SDRAM
Address Bus
Output
TTL
b0:U23, b1:T26, b2:T25,
b3:T24, b4:T23, b5:R26,
b6:R25, b7:R24, b8:R23,
b9:P26, b10:P25
PSDRAMBS
Control SDRAM
Bank Select
Output
TTL
U26
PSDRAMRASb
Control SDRAM
Row Address Strobe
Output
TTL
U24
PSDRAMCASb
Control SDRAM
Column Address Strobe
Output
TTL
U25
PSDRAMWEb
Control SDRAM
Write Enable Strobe
Output
TTL
V24
PSDRAMDQM
ica
Control SDRAM
Data Mask
Output
TTL
V23
Table 1: Ball Descriptions (continued)
Functional
Group
Ball Name(s)
(Appended b
indicates
active low signal)
Function
Type
PBGA Ball(s)
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