CS6220
Preliminary
Sales@myson.com.tw
www.myson.com.tw
Rev.0.1 October 2003
page 1 of 277
Myson Century, Inc.
No. 2, Industry East Rd. III,
Science-Based Industrial Park, Hsin-Chu, Taiwan
Tel: 886-3-578-4866 Fax: 886-3-578-4349
32-Bit SoC MCU for VoIP
1.0
I
NTRODUCTION
The CS6220 processor is a high performance system-on-a-chip (SoC) that combines a unified RISC/DSP
processor with a high-speed 32-channel DMA controller, on-chip SRAM, two Ethernet 10/100 Base-T
MACs and an ATM UTOPIA interface. The CS6220 is ideal for low-cost packet-based audio terminal and
gateway solutions since it provides maximum flexibility and requires minimal external components. Its pri-
mary design feature is lowest cost bill of materials (BOM) for both VoIP/VoDSL gateway applications and
Ethernet PBX applications, but in addition it features low power to facilitate primary service capabilities and
minimize thermal system issues, C-based programmability to improve programmer efficiency, and low EMI
to simplify packaging and qualification of systems.The CS6220 processor is currently available in a 196-
pin PBGA package. All I/Os are 3.3V CMOS levels, with all inputs and 3-states having 5V tolerance.
1.1
Feature Summary
MIPS-X5 unified RISC and DSP core (up to 180 DSP MIPS)
384KBytes on-chip RAM, 16-way interleaved with single cycle access
Two 10/100 Base-T Ethernet MACs with MII interface for external PHY
ATM UTOPIA interface, level 2, single status, 8-bit databus, 2 ports.
Memory Controller with crosspoint switch and non-blocking memory accesses
32 channel DMA engine integrated with peripherals
Hardware acceleration for DES/3DES/CRC-10/CRC-16/CRC-32 and HDLC operations.
16-KByte, 2-way set associative unified cache for external Flash/SRAM memory
Hardware support for cache profiling and application performance analysis.
External memory-mapped bus supporting 8-bit and 16-bit asynchronous devices
Low power, 1.8V core voltage, 3.3V I/O voltage, typical core dissipation of <0.4W
16K bytes of internal boot ROM
Four external chip selects for glueless memory-mapped bus interfacing
External ISA/SRAM-like device support via memory-mapped bus
H.100/H.110, MVIP, SCSA and GCI/IOM-2compatibility via TDM port
Multimedia codec compatibility via TDM port
Glueless multiple SLAC support via TDM port
Mastering Host port for scalable multi-chip systems.
Serial and parallel debug interface via Serial and Host Interfaces
Up to 43 GPIO pins, with 8 capable of generating edge or level based IRQ's
Glueless support of SLIC/SLAC ringing and on/off hook features via GPIO functions
Glueless support of character LCD displays via GPIO functions
Telephone-style keypad and LED support via GPIO functions
GCC-based IDE/compiler support with assembler and debugger
Software chip and system simulators for software development and debug
196-pin PBGA package with 15mm x 15mm bodysize and 1mm ball pitch.
JTAG board-level test interface
*This datasheet is the confidential information of MYSON CENTURY, INC. and is subject to various privileges
against unauthorized disclosure. Recipient shall not disclose this confidential information to any other person,
nor shall one use the confidential information for the purpose of competing with MYSON CENTURY, INC.
CONFIDENTIAL
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CS6220
Preliminary
1.2
Terms Used in this Document
Any reference to kodiac is a reference to the CS6220 processor. Kodiac is an internal
engineering name for the CS6220 hardware architecture and is used extensively in all
source code.
Extensive examples using the format kodiac[tdm1_length] are contained in this docu-
ment. It is used exclusively in all source code.
All programing registers described in this document should match exactly with all source
codes with the sole exception that registers are expressed in lower case (tdm1_length) in
C source code as opposed to the upper case (TDM1_LENGTH) used here to highlight
them.
All register bits belong to one of four types: RW (Read/Write), RO (Read-Only), WO
(Write-Only), and RS (Readable and Write-a-one to Clear).
Registers named, for example, MACx_DMA_RX_STAT, refer to multiple identical periph-
erals where x is the peripheral identifying number.
Registers are named as follows: TDM1_SLOT_CONTROL[0:31] refer to an array of iden-
tically functional registers with only different names and addresses.
The acronyms TRE and DW refer to "Transmit Register Empty" and "Data Waiting." They
are used in status registers to indicate data must be read or writ-
ten.
MACx_DMA_RX_STAT Register
1.3
Related Publications
Veracity VoIP Software Stacks API Manual
CONFIDENTIAL
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CS6220
Preliminary
1.4
Example Applications
This section provides example applications that utilize the CS6220 processor.
1.4.1
Ethernet PBX Terminal
The CS6220 processor can be used to build a PBX-style business phone that interfaces
via Ethernet to other phones or the PSTN. Such a phone requires the addition of a small
external Flash memory, analog codecs, and PHY. The CS6220 processor has enough
GPIO pins to drive a basic keypad and nibble interface LCD directly.
FIGURE 1. Example Ethernet PBX Application
Stereo CODEC
CS6220
TDM1
1Mx16
Flash
70ns
Ethernet
100 BASE-T
PHY
Speaker/
Handset
MIC/
Handset
1 2 3
4 5 6
7 8 9
Keypad
GPIO
GP
IO
MII
EXT BUS
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CS6220
Preliminary
1.4.2
xDSL Residential Gateway
The CS6220 processor can be used for multi-channel residential gateway applications,
interfacing with a broadband xDSL modem in a variety of ways. As an integrated unit, an
CS6220 processor can interface with an xDSL modem using the UTOPIA interface for
data and the SRAM style bus for control. Ethernet can also be used either externally to
work with a standalone modem, or internally within a system via a concealed hub/switch.
The CS6220 device also adds additional value in this application--it provides hardware
acceleration for VPN tunneling using the on-chip DES hardware and the dual MACs or
UTOPIA/MAC combination to provide both "internal" and "external" network ports.
FIGURE 2. Example Residential xDSL Modem Application
SLIC
DUAL SLAC
CS6220
TDM
xDSL Modem
Flash
SRAM Bus
"Internal" Ethernet Port
SLIC
SRAM
UTOPIA
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CS6220
Preliminary
1.4.3
Higher Density Gateway
Multiple instances of CS6220 processors can be used very efficiently to build multi-port
telephone gateways. One CS6220 processor is used as the master device, running proto-
col stacks and providing the network interface, while one or more slave CS6220 devices
are connected via the host interface (HI) to the master's mastering host interface
(MHI).The telephony interfaces can be dynamically mapped to slave CS6220 devices via
the programmable TDM ports, which can be connected together with the master handling
time-slot assignment. Such an arrangement can provide arbitrary combinations of incom-
ing or outgoing analog line interfaces, as well as dividing the multiple calls of a digital T1/
E1-style trunk among multiple devices. Such a configuration allows the master CS6220
device to be the only device with an external Flash memory, while all the slaves boot via
the internal ROM and host interface from the master. Line interfaces can communicate
with the master either directly or via an arbitrary slave using GPIO pins to implement sim-
ple ring indicators or two-wire serial interfaces.
FIGURE 3. Multi-Instance Gateway
CS6220
10/10
0 MBit Eth
e
rnet
Flash
Memory-Mapped SRAM Bus
TD
M Bus with Programmabl
e T
i
me-slot Assi
gment
Analog Line
Interface
Digital Trunk
Interface
SRAM
CS6220
CS6220
Mastering Host
Bus
CONFIDENTIAL
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