5-Port 10M/100M Ethernet Switch
MTD505
BLOCK DIAGRAM
GENERAL DESCRIPTION
FEATURES
Myson-Century Technology
USA:
4020 Moorpark Avenue Suite 115
San Jose, CA, 95117
Tel: 408-243-8388 Fax: 408-243-3188
Sales@myson.com.tw
www.myson.com.tw
www.century-semi.com
Rev.1.3 December 2001
page 1 of 19
Myson-Century Technology, Inc.
Taiwan:
No. 2, Industry East Rd. III,
Science-Based Industrial Park, Hsin-Chu, Taiwan
Tel: 886-3-5784866 Fax: 886-3-5784349
The MTD505 complies fully with the IEEE802.3,
802.3u and 802.3x specifications and is a non-
blocking 5-port 10M/100M Ethernet switch device.
The MTD505 supports 4 RMII and 1 MII/RMII
ports for 10M/100M operation. 1MBytes/2MBytes
memory interface provides maximum 1365 packet
buffers for Ethernet packet buffering. Up to 8192
address entries are provided by the MTD505, and
the MTD505 uses full Ethernet address to compare
algorithm for minimizing hashing collision events.
The MTD505 provides EEPROM interface to
configure port trunking, port VLAN, static entry,
802.3x flow control threshold, flooding port,
broadcast control threshold. Each MTD505 port
supports 10M/100M auto-negotiation by MDC/MDIO
interface for connecting external PHY devices.
The MTD505 also provides 10 pins for Link/RX
activities, packet butter utilization LED display
functoin.
IEEE802.3 and IEEE802.3u compliant.
Provides 4 RMII and 1 MII/RMII ports.
Programmable 1K/8K MAC addresses filtering.
Store and forward switching function and bad
packet filtering function.
Optional back-pressure/802.3x flow control/
flooding control/broadcast control.
Optional EEPROM interface for advanced switch
configurations.
1MB/2MB SGRAM/SDRAM flexible memory
interface.
Port VLAN/trunking.
Link/Rx activities, packet buffer utilization LED
display.
50MHz for non-blocking for 5-port switch
operation.
Built-in interna/external memory test function.
128-pin PQFP package, 3.3V operating voltage.
SDRAM/
SGRAM
Interface
Memory
Controller
Memory
Port
Switch
Logic
DMA0
DMA1
DMA2
DMA3
DMA4
MAC0
MAC1
MAC2
MAC3
MAC4
RMII0
RMII1
RMII2
RMII3
RMII4
Arbiter
MTD505
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Myson-Century Technology
SYSTEM DIAGRAM
SGRAM
(256k32x1)
SGRAM
(512k32x1)
SDRAM
(256k32x2)
(**Programmable)
(**Optional)
EEPROM
MTD505
LEDs
RMII0-3
MII4
QUAD
PHYsceiver
QUAD
Transformer
RJ45
MII management
Single
PHYsceiver
Single
Transformer
RJ45
MTD505
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Myson-Century Technology
PIN CONNECTION
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
10
2
10
1
10
0
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
RXD1
_
0
RXD1
_
1
CRSDV2
TX
D
2
_1
TX
D
2
_0
T
XEN2
GND0
VCCO
RXD2
_
0
RXD2
_
1
CRSDV3
RXD3
_
0
RXD3
_
1
T
XEN3
RXD3
_
0
RXD3
_
1
CRSDV4
CO
L
4
TX
D
4
_3
TX
D
4
_2
TX
D
4
_1
TXD
_
0
T
XEN4
TX
C
4
RXC4
RXDV4
GNDI
VCCI
RXD4
_
3
RXD4
_
2
RXD4
_
1
RXD4
_
0
GNDI
VCCI
GNDI
S
YSCL
K
VCCI
DQ
3
1
L
E
DDA
T
A
5
L
E
DDA
T
A
6
L
E
DDA
T
A
7
VC
C
O
GNDO
L
E
DCL
K2
L
E
DCL
K1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ1
6
DQ1
7
DQ1
8
DQ1
9
DQ2
0
VC
C
O
GNDO
DQ2
1
DQ2
2
DQ2
3
WE
B
CA
SB
RA
SB
CS
0
B
BA
VC
C
I
GNDI
CS
1
B
AD
0
AD
1
AD
2
AD
3
AD
4
LEDDATA4
LEDDATA3
LEDDATA2
LEDDATA1
LEDDATA0
GNDI
CLK25M
VCCI
SDC
SDIO
EECLK
EEDATA
RESETB
REFCLK
MDIO
MDC
CRSDV0
TXD0_1
TXD0_0
TXEN0
RXD0_0
RXD0_1
CRSDV1
TXD1_1
TXD1_0
TXEN1
VCCO
GNDO
AD5
AD6
AD7
AD8
VCCI
MEMCLK
GNDI
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ24
DQ25
DQ26
VCCO
GNDO
DO27
DO28
DO29
DO30
MTD505
128-pin PQFP
MTD505
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Myson-Century Technology
PIN DESCRIPTION
RMII/MII Port Interface Pins
Name
I/O
Pin
Description
CRSDV0
I
119
Port0 RMII receive interface signal, CRSDV0 is asserted high when port0
media is non-idle.
RXD0_0
I
123
Port0 RMII receive data bit0.
RXD0_1
I
124
Port0 RMII receive data bit1.
TXEN0
O
122
Port0 RMII transmit enable signal.
TXD0_0
O
121
Port0 RMII transmit data bit0.
TXD0_1
O
120
Port0 RMII transmit data bit1.
CRSDV1
I
125
Port1 RMII receive interface signal, CRSDV1 is asserted high when port1
media is non-idle.
RXD1_0
I
1
Port1 RMII receive data bit0.
RXD1_1
I
2
Port1 RMII receive data bit1.
TXEN1
O
128
Port1 RMII transmit enable signal.
TXD1_0
O
127
Port1 RMII transmit data bit0.
TXD1_1
O
126
Port1 RMII transmit data bit1.
CRSDV2
I
3
Port2 RMII receive interface signal, CRSDV2 is asserted high when port2
media is non-idle.
RXD2_0
I
9
Port2 RMII receive data bit0.
RXD2_1
I
10
Port2 RMII receive data bit1.
TXEN_2
O
6
Port2 RMII transmit enable signal.
TXD2_0
O
5
Port2 RMII transmit data bit0.
TXD2_1
O
4
Port2 RMII transmit data bit1.
CRSDV3
I
11
Port3 RMII receive interface signal, CRSDV3 is asserted high when port3
media is non-idle.
RXD3_0
I
15
Port3 RMII receive data bit0.
RXD3_1
I
16
Port3 RMII receive data bit1.
TXEN3
O
14
Port3 RMII transmit enable signal.
TXD3_0
O
13
Port3 RMII transmit data bit0.
TXD3_1
O
12
Port3 RMII transmit data bit1.
CRSDV4
I
17
Port4 RMII receive interface signal, CRSDV2 is asserted high when port4
media is non-idle.
RXDV4
I
26
Port4 MII receive data valid. In RMII mode, this pin is not used.
RXCLK4
I
25
Port4 MII receive clock signal. In RMII mode, this pin is not used.
RXD4_3
I
32
Port MII receive data bit3. In RMII mode, this pin is not used.
RXD4_2
I
31
Port MII receive data bit2. In RMII mode, this pin is not used.
RXD4_0
I
29
Port MII receive data bit0.
RXD4_1
I
30
Port MII receive data bit1.
TXEN4
O
23
Port4 RMII transmit enable signal.
MTD505
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Myson-Century Technology
TXCLK4
I
24
Port4 RMII transmit clock signal. In RMII mode, this pin is not used.
TXD4_3
O
19
Port4 MII transmit data bit3. In RMII mode, this pin is not used.
TXD4_2
O
20
Port4 MII transmit data bit2. In RMII mode, this pin is not used.
TXD4_0
O
22
Port4 RMII/MII transmit data bit0.
TXD4_1
O
21
Port4 RMII/MII transmit data bit1.
COL4
I
18
Port4 MII collision input. In RMII mode, this pin is not used.
CLK25M
O
109
Port4 MII 25MHz clock output.
SGRAM/SDRAM Interface Pins
Name
I/O
Pin
Description
AD[8:0]
O
59-62, 65-69 Memory row/column address bus outputs.
AD[7:0] are row/column address[7:0].
AD[8]: This pin should connect to SGRAM/SDRAM MSB address bit.
DQ[31:0]
I/O
38-42, 45-55,
78-80, 83-95
Memory data bus.
RASB
O
75
SGRAM/SDRAM row address select.
CASB
O
76
SGRAM/SDRAM column address select.
WEB
O
77
SGRAM/SDRAM write enable.
BA
O
73
SGRAM/SDRAM bank select.
CS0B
O
74
Memory chip select 0.
CS1B
O
70
Memory chip select 1.
MEMCLK
O
57
Memory clock output.
LED Interface Pins
Name
I/O
Pin
Description
LEDDATA[7:0]
I/O
100-107
LED data output.
These LED pins report ports0`7 Link/Rx activities using LEDCLK1 strobe, and
report packet buffer utilization status using LEDCLK2 strobe.
LEDDATA [0] [1] [2] [3] [4] [5] [6] [7]
LEDCLK1 LR0 LR1 LR2 LR3 LR4 - - -
LEDCLK2 Uti0 Uti1 Uti2 Uti3 Uti4 - BFull MFail
Note: LRn: per port's Link_RxAct status;
Uti0: 5%, Uti1: 10%, Uti: 20%, Uti3: 35%, Uti4: 50% and above;
BFull: buffer almost full alarm signal;
MFail: external memory poer on test failure.
LEDCLK1
I/O
96
LED strobe 1.
LEDCLK2
I/O
97
LED strobe 2.
RMII/MII Port Interface Pins
Name
I/O
Pin
Description
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