This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of the product.

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MTV018 Revision 3.0 06/01/1999

MTV018

MYSON
TECHNOLOGY

FEATURES

GENERAL DESCRIPTION

BLOCK DIAGRAM

· Horizontal sync input may be up to 120 KHz.
· On-chip PLL circuitry up to 96 MHz.
· Programmable horizontal resolutions up to 1524 dots per dis-

play row.

· 942 bytes display registers to control full screen display.
· Full screen display consists of 15 (rows) by 30 (columns) char-

acters.

· 12 x 18 dot matrix per character.
· Total 256 characters and graphic fonts including 248 mask

ROM fonts and 8 programmable RAM fonts.

· 8 color selectable maximum per display character.
· Double character height and/or width control.
· Programmable positioning for display screen center.
· Bordering, shadowing and blinking effect.
· Programmable vertical character height (18 to 71 lines) control.
· Row to row spacing register to manipulate the constant display

height.

· 4 programmable background windows with multi-level operation
· Software clears for display frame.
· Polarity selectable to Hsync and Vsync inputs.
· Auto detection for input edge bounce distortion between Hsync

and Vsync inputs.

· Half tone and fast blanking output.
· Software force blank function for external display.
· 8 channels 8 bits PWM D/A converters output.
· Provide a clock output synchronous to the incoming Hsync for

external PWM D/A.

· Compatible to SPI bus or I

C interface.

· I

C interface with address 7AH (Slave address is mask option).

· 16 pins or 24 pins PDIP package.

Super On-Screen-Display

MTV018 is designed for monitor applications to dis-
play the built-in characters or fonts onto monitor
screen. The display operation is by transferring data
and control information from micro controller to RAM
through a serial data interface. It can execute full
screen display automatically and specific functions
such as character bordering, shadowing, blinking,
double height and width, font by font color control,
frame positioning, frame size control by character
height and horizontal display resolution, and window-
ing effect. Moreover, MTV018 also provide 8 PWM
DAC channels with 8 bits resolution and a PWM
clock output for external digital to analog control.

SERIAL DATA

INTERFACE

ADDRESS BUS

ADMINISTRATOR

VERTICAL

DISPLAY

CONTROL

DISPLAY & ROW

CONTROL

REGISTERS

COLOUR

ENCODER

WINDOWS &

FRAME

CONTROL

FBKGC

BLANK

LUMAR
LUMAG
LUMAB

BLINK

VCLKX

DATA

VERTD

HORD

8
8
7

BSEN
SHADOW
OSDENB
HSP
VSP

HORIZONTAL

DISPLAY CONTROL

PHASE LOCK LOOP

DATA

LPN

CWS

VCLKS

DATA

CWS

CHS

LUMAR
LUMAG
LUMAB
BLINK
CRADDR

LUMA

BORDER

ARWDB

HDREN

VCLKX

HORD 8

CHS

VERTD

LPN

NROW

VDREN

RCADDR
DADDR
FONTADDR
WINADDR
PWMADDR

5
9
9
5
5

ARWDB

HDREN
VDREN

NROW

DATA

ROW, COL

ACK

CHARACTER ROM

USER FONT RAM

LUMINANCE &

BORDGER

GENERATOR

VDD

VSS

VDDA

VSSA

ROUT

GOUT

BOUT

FBKG

HTONE

HFLB

VCO

VFLB

SSB

SCK

SDA

VSP

HSP

PWM D/A

CONVERTER

PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7

DATA

POWER ON

RESET

PRB

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MTV018

MYSON
TECHNOLOGY

1.0 PIN CONNECTION

2.0 PIN DESCRIPTIONS

Name

I/O

Pin No.

Descriptions

N16

N24

VSSA

Analog ground. This ground pin is used to internal analog circuitry.

VCO

I/O

Voltage Control Oscillator. This pin is used to control the internal oscil-
lator frequency by DC voltage input from external low pass filter.

I/O

Bias Resistor. The bias resistor is used to regulate the appropriate bias
current for internal oscillator to resonate at specific dot frequency.

VDDA

Analog power supply. Positive 5 V DC supply for internal analog cir-
cuitry. And a 0.1uF decoupling capacitor should be connected across to
VDDA and VSSA.

HFLB

Horizontal input. This pin is used to input the horizontal synchronizing
signal. It is a leading edge triggered and has an internal pull-up resistor.

SSB

Serial interface enable. It is used to enable the serial data and is also
used to select the operation of I

C or SPI bus. If this pin is left floating, I

bus is enabled, otherwise the SPI bus is enabled.

SDA

Serial data input. The external data transfer through this pin to internal
display registers and control registers. It has an internal pull-up resistor.

SCK

Serial clock input. The clock-input pin is used to synchronize the data
transfer. It has an internal pull-up resistor.

PWM0

Open-Drain PWM D/A converter 0. The output pulse width is program-
mable by the register of Row 15, Column 19.

PWM1

Open-Drain PWM D/A converter 1. The output pulse width is program-
mable by the register of Row 15, Column 20.

PWM2

Open-Drain PWM D/A converter 2. The output pulse width is program-
mable by the register of Row 15, Column 21.

PWM3

Open-Drain PWM D/A converter 3. The output pulse width is program-
mable by the register of Row 15, Column 22.

VSSA

VCO

VDDA

HFLB

SSB

SDA

SCK

VSS

ROUT

GOUT

BOUT

FBKG

HTONE/PWMCK

VFLB

VDD

MTV018

VSSA

VCO

VDDA

HFLB

SSB

SDA

SCK

PWM0

PWM1

PWM2

PWM3

VSS

ROUT

GOUT

BOUT

FBKG

HTONE/PWMCK

VFLB

VDD

PWM7

PWM6

PWM5

PWM4

MTV018N24

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MTV018

MYSON
TECHNOLOGY

3.0 FUNCTIONAL DESCRIPTIONS

3.1 SERIAL DATA INTERFACE

The serial data interface receives data transmitted from an external controller. And there are 2 types of bus
can be accessed through the serial data interface, one is SPI bus and other is I

C bus.

3.1.1 SPI bus
While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a valid transmission
should be starting from pulling SSB to "low" level, enabling MTV018 to receiving mode, and retain "low" level
until the last cycle for a complete data packet transfer. The protocol is shown in Figure 1.

PWM4

Open-Drain PWM D/A converter 4. The output pulse width is program-
mable by the register of Row 15, Column 23.

PWM5

Open-Drain PWM D/A converter 5. The output pulse width is program-
mable by the register of Row 15, Column 24.

PWM6

Open-Drain PWM D/A converter 6. The output pulse width is program-
mable by the register of Row 15, Column 25.

PWM7

Open-Drain PWM D/A converter 7. The output pulse width is program-
mable by the register of Row 15, Column 26.

VDD

Digital power supply. Positive 5 V DC supply for internal digital circuitry
and a 0.1uF decoupling capacitor should be connected across to VDD
and VSS.

VFLB

Vertical input. This pin is used to input the vertical synchronizing signal.
It is leading triggered and has an internal pull-up resistor.

HTONE /

PWMCK

Half tone output / PWM clock output. This is a multiplexed pin selected
by PWMCK bit. This pin can be a PWM clock or used to attenuate R, G, B
gain of VGA for the transparent windowing effect.

FBKG

Fast Blanking output. It is used to cut off external R, G, B signals of
VGA while this chip is displaying characters or windows.

BOUT

Blue color output. It is a blue color video signal output.

GOUT

Green color output. It is a green color video signal output.

ROUT

Red color output. It is a red color video signal output.

VSS

Digital ground. This ground pin is used to internal digital circuitry.

Name

I/O

Pin No.

Descriptions

N16

N24

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TECHNOLOGY

There are three transmission formats shown as below:
Format (a) R - C - D

R - C - D

Format (b) R - C - D

C - D

Format (c) R - C - D

Where R=Row address, C=Column address, D=Display data

3.1.2 I

C bus

C bus operation is only selected when SSB pin is left floating. And a valid transmission should be starting

from writing the slave address 7AH, which is mask option, to MTV018. The protocol is shown in Figure 2.

There are three transmission formats shown as below:
Format (a) S - R - C - D

R - C - D

Format (b) S - R - C - D

C - D

Format (c) S - R - C - D

Where S=Slave address, R=Row address, C=Column address, D=Display data

Each arbitrary length of data packet consists of 3 portions viz, Row address (R), Column address (C), and
Display data (D). Format (a) is suitable for updating small amount of data which will be allocated with different
row address and column address. Format (b) is recommended for updating data that has same row address
but different column address. Massive data updating or full screen data change should use format (c) to
increase transmission efficiency. The row and column address will be incremented automatically when the for-
mat (c) is applied. Furthermore, the undefined locations in display or fonts RAM should be filled with dummy
data.

There are 3 types of data should be accessed through the serial data interface, one is ADDRESS bytes of dis-
play registers, second is ATTRIBUTE bytes of display registers and other is user fonts RAM data, the protocol
are same for all except the bit6 and bit5 of row address. The MSB(b7) is used to distinguish row and column
addresses when transferring data from external controller. The bit6 of row address is used to distinguish dis-
play registers and user fonts RAM data and the bit6 of column address is used to differentiate the column
address for format (a), (b) and format (c) respectively. Bit5 of row address for display register is used to distin-
guish ADDRESS byte when it is set to "0" and ATTRIBUTE byte when it is set to "1". See Table 1.

MS
B

LSB

SSB

SCK

SDA

first byte

last byte

FIGURE 1. Data transmission protocol

FIGURE 2. Data transmission protocol (I

SCK

SDA

first byte

START

ACK

second byte

last byte

ACK

STOP

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MYSON
TECHNOLOGY

The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format
(a), but not from format (c) back to format (a) and (b). The alternation between transmission formats is config-
ured as the state diagram shown in Figure 3 on page 5.

3.2 Address bus administrator

The administrator manages bus address arbitration of internal registers or user fonts RAM during external
data write in. The external data write through serial data interface to registers must be synchronized by inter-
nal display timing. In addition, the administrator also provides automatic increment to address bus when exter-
nal write using format (c).

3.3 Vertical display control

The vertical display control can generates different vertical display sizes for most display standards in current
monitors. The vertical display size is calculated with the information of double character height bit(CHS), verti-

TABLE 1. The configuration of transmission formats.

Address

Format

Address Bytes

of Display Reg.

Row

a,b,c

Column

a,b

Column

Attribute Bytes

of Display Reg.

Row

a,b,c

Column

a,b

Column

User Fonts

RAM

Row

a,b,c

Column

a,b

Column

Initiate

ROW

COL

1, X

0, 1

0, 0

X, X

0, 1

1, X

format (a)

format (b)

format (c)

X, X

0, X

Input = b7, b6

0, 0

FIGURE 3. Transmission state diagram

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