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Электронный компонент: N01L1618N1AT-70I

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NanoAmp Solutions, Inc.
670 North McCarthy Blvd. Suite 220, Milpitas, CA 95035
ph: 408-935-7777, FAX: 408-935-7770
www.nanoamp.com
N01L1618N1A
(DOC# 14-02-009 REV F ECN# 01-0995)
1
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
1Mb Ultra-Low Power Asynchronous CMOS SRAM
64K 16 bit
Overview
The N01L1618N1A is an integrated memory
device containing a 1 Mbit Static Random Access
Memory organized as 65,536 words by 16 bits. The
device is designed and fabricated using
NanoAmp's advanced CMOS technology to
provide both high-speed performance and ultra-low
power. The device operates with a single chip
enable (CE) control and output enable (OE) to
allow for easy memory expansion. Byte controls
(UB and LB) allow the upper and lower bytes to be
accessed independently. The N01L1618N1A is
optimal for various applications where low-power is
critical such as battery backup and hand-held
devices. The device can operate over a very wide
temperature range of -40
o
C to +85
o
C and is
available in JEDEC standard packages compatible
with other standard 64Kb x 16 SRAMs.
Features
Single Wide Power Supply Range
1.65 to 2.2 Volts
Very low standby current
0.5A at 1.8V (Typical)
Very low operating current
0.7mA at 1.8V and 1s (Typical)
Very low Page Mode operating current
0.5mA at 1.8V and 1s (Typical)
Simple memory control
Single Chip Enable (CE)
Byte control for independent byte operation
Output Enable (OE) for memory expansion
Low voltage data retention
Vcc = 1.2V
Very fast output enable access time
30ns OE access time
Automatic power down to standby mode
TTL compatible three-state output driver
Compact space saving BGA package avail-
able
Pin Configurations
Product Family
Part Number
Package Type
Operating
Temperature
Power
Supply (Vcc)
Speed
Standby
Current (I
SB
),
Typical
Operating
Current (Icc),
Typical
N01L1618N1AB
48 - BGA
-40
o
C to +85
o
C 1.65V - 2.2V
70ns @ 1.8V
85ns @ 1.65V
0.5
A
0.7 mA @
1MHz
N01L1618N1AT
44 - TSOP II
N01L1618N1AB2
48 - BGA Green
N01L1618N1AT2 44 - TSOP II Green
PIN
ONE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A
4
A
3
A
2
A
1
A
0
CE
I/O
0
I/O
1
I/O
2
I/O
3
VCC
VSS
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
15
A
14
A
13
A
12
NC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
5
A
6
A
7
OE
UB
LB
I/O
15
I/O
14
I/O
13
I/O
12
VSS
VCC
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
8
A
9
A
10
A
11
NC
N01
L
16
18N1
A
T
S
OP
1
2
3
4
5
6
A
LB
OE
A
0
A
1
A
2
NC
B
I/O
8
UB
A
3
A
4
CE
I/O
0
C
I/O
9
I/O
10
A
5
A
6
I/O
1
I/O
2
D
V
SS
I/O
11
NC
A
7
I/O
3
V
CC
E
V
CC
I/O
12
NC
NC
I/O
4
V
SS
F
I/O
14
I/O
13
A
14
A
15
I/O
5
I/O
6
G
I/O
15
NC
A
12
A
13
WE
I/O
7
H
NC
A
8
A
9
A
10
A
11
NC
48 Pin BGA (top)
6 x 8 mm
Pin Descriptions
Pin Name
Pin Function
A
0
-A
15
Address Inputs
WE
Write Enable Input
CE
Chip Enable Input
OE
Output Enable Input
LB
Lower Byte Enable Input
UB
Upper Byte Enable Input
I/O
0
-I/O
15
Data Inputs/Outputs
NC
Not Connected
V
CC
Power
V
SS
Ground
(DOC# 14-02-009 REV F ECN# 01-0995)
2
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N01L1618N1A
Functional Block Diagram
Functional Description
CE
WE
OE
UB
LB
I/O
0
- I/O
15
1
1. When UB and LB are in select mode (low), I/O
0
- I/O
15
are affected as shown. When LB only is in the select mode only I/O
0
- I/O
7
are affected as shown. When UB is in the select mode only I/O
8
- I/O
15
are affected as shown.
MODE
POWER
H
X
X
X
X
High Z
Standby
2
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
Standby
L
X
X
H
H
High Z
Active
Active
L
L
X
3
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
L
1
L
1
Data In
Write
3
Active -> Standby
4
L
H
L
L
1
L
1
Data Out
Read
Active -> Standby
4
L
H
H
L
1
L
1
High Z
Active
Standby
4
4. The device will consume active power in this mode whenever addresses are changed. Data inputs are internally isolated from any
external influence.
Capacitance
1
1. These parameters are verified in device characterization and are not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input Capacitance
C
IN
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
8
pF
I/O Capacitance
C
I/O
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
8
pF
Address
Inputs
A0 - A3
Address
Inputs
A4 - A15
Word
Address
Decode
Logic
4K Page
x 16 word
x 16 bit
RAM Array
W
o
rd Mux
Input/
Output
Mux
and
Buffers
Page
Address
Decode
Logic
Control
Logic
CE
WE
OE
UB
LB
I/O0 - I/O7
I/O8 - I/O15
(DOC# 14-02-009 REV F ECN# 01-0995)
3
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N01L1618N1A
Absolute Maximum Ratings
1
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Symbol
Rating
Unit
Voltage on any pin relative to V
SS
V
IN,OUT
0.3 to V
CC
+0.3
V
Voltage on V
CC
Supply Relative to V
SS
V
CC
0.3 to 3.0
V
Power Dissipation
P
D
500
mW
Storage Temperature
T
STG
40 to 125
o
C
Operating Temperature
T
A
-40 to +85
o
C
Soldering Temperature and Time
T
SOLDER
260
o
C, 10sec
o
C
Operating Characteristics (Over Specified Temperature Range)
Item
Symbol
Test Conditions
Min.
Typ
1
1. Typical values are measured at Vcc=Vcc Typ., T
A
=25C and are not 100% tested.
Max
Unit
Supply Voltage
V
CC
1.65
1.8
2.2
V
Data Retention Voltage
V
DR
Chip Disabled
3
1.2
V
Input High Voltage
V
IH
0.7V
CC
V
CC
+0.3
V
Input Low Voltage
V
IL
0.3
0.3V
CC
V
Output High Voltage
V
OH
I
OH
= 0.2mA
V
CC
0.3
V
Output Low Voltage
V
OL
I
OL
= -0.2mA
0.3
V
Input Leakage Current
I
LI
V
IN
= 0 to V
CC
0.5
A
Output Leakage Current
I
LO
OE = V
IH
or Chip Disabled
0.5
A
Read/Write Operating Supply Current
@ 1
s Cycle Time
2
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive
output capacitance expected in the actual system.
I
CC1
V
CC
=2.2 V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0
0.7
3.0
mA
Read/Write Operating Supply Current
@ 85 ns Cycle Time
2
I
CC2
V
CC
=2.2 V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0
8
16
mA
Page Mode Operating Supply Current
@ 85ns Cycle Time
2
(Refer to Power
Savings with Page Mode Operation
diagram)
I
CC3
V
CC
=2.2 V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0,
3
mA
Read/Write Quiescent Operating Sup-
ply Current
3
3. This device assumes a standby mode if the chip is disabled (CE high). In order to achieve low standby current all inputs must be
within 0.2 volts of either VCC or VSS
I
CC4
V
CC
=2.2 V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0,
f = 0
20
A
Maximum Standby Current
3
I
SB1
V
IN
= V
CC
or 0V
Chip Disabled
t
A
= 85
o
C, V
CC
= 2.2 V
0.5
10
A
Maximum Data Retention Current
3
I
DR
V
CC
= 1.2V, V
IN
= V
CC
or 0
Chip Disabled, t
A
= 85
o
C
5
A
(DOC# 14-02-009 REV F ECN# 01-0995)
4
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N01L1618N1A
Power Savings with Page Mode Operation (WE = V
IH
)
Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal
organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power
saving feature.
The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open
and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant
bits and addressing the 16 words within the open page, power is reduced to the page mode value which is
considerably lower than standard operating currents for low power SRAMs.
Page Address (A4 - A15 )
LB, UB
OE
CE
Word Address (A0 - A3)
Open page
Word 1
Word 2
Word 16
...
(DOC# 14-02-009 REV F ECN# 01-0995)
5
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N01L1618N1A
Timing Test Conditions
Item
Input Pulse Level
0.1V
CC
to 0.9 V
CC
Input Rise and Fall Time
5ns
Input and Output Timing Reference Levels
0.5 V
CC
Output Load
CL = 30pF
Operating Temperature
-40 to +85
o
C
Timing
Item
Symbol
1.65 - 2.2 V
1.8 - 2.2 V
Units
Min.
Max.
Min.
Max.
Read Cycle Time
t
RC
85
70
ns
Address Access Time
t
AA
85
70
ns
Chip Enable to Valid Output
t
CO
85
70
ns
Output Enable to Valid Output
t
OE
35
30
ns
Byte Select to Valid Output
t
LB
, t
UB
30
25
ns
Chip Enable to Low-Z output
t
LZ
10
10
ns
Output Enable to Low-Z Output
t
OLZ
5
5
ns
Byte Select to Low-Z Output
t
LBZ
, t
UBZ
10
10
ns
Chip Disable to High-Z Output
t
HZ
30
25
ns
Output Disable to High-Z Output
t
OHZ
30
25
ns
Byte Select Disable to High-Z Output
t
LBHZ
, t
UBHZ
30
25
ns
Output Hold from Address Change
t
OH
5
5
ns
Write Cycle Time
t
WC
85
70
ns
Chip Enable to End of Write
t
CW
50
40
ns
Address Valid to End of Write
t
AW
50
40
ns
Byte Select to End of Write
t
LBW
, t
UBW
50
40
ns
Write Pulse Width
t
WP
50
40
ns
Address Setup Time
t
AS
0
0
ns
Write Recovery Time
t
WR
0
0
ns
Write to High-Z Output
t
WHZ
25
20
ns
Data to Write Time Overlap
t
DW
40
35
ns
Data Hold from Write Time
t
DH
0
0
ns
End Write to Low-Z Output
t
OW
10
10
ns