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Электронный компонент: N04C1630E3AM-7BI

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NanoAmp Solutions, Inc.
1982 Zanker Road, San Jose, CA 95112
ph: 408-573-8878, FAX: 408-573-8877
www.nanoamp.com
Preliminary
N04C1630E3AM
Stock No. 23154-E 1/03
1
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
32x04 Combination Memory Multi-Chip Package (MCP)
32Mb (2Mbx16) Dual Bank Flash Memory plus 4Mb (256Kbx16) SRAM
3.0V, 70ns Access Time, 66-Ball FBGA, Industrial Temperature Range
OVERVIEW & FEATURES
Flexible dual-bank architecture
Support for true concurrent operations with
zero latency:
Read bank a during program bank b and vice
versa
Read bank a during erase bank b and vice
versa
Basic configuration:
32Mb Flash memory (2,048Kb x 16)
Bank a (8Mb Flash for data storage)
- Eight 4K-word parameter blocks
- Fifteen 32K-word blocks
Bank b (24Mb Flash for program storage)
- Forty-eight 32K-word main blocks
4Mb SRAM (256Kb x 16)
F_V
CC
, V
CC
Q, F_V
PP
, S_V
CC
voltages
2.7V (MIN)/3.3V (MAX) F_V
CC
read voltage
2.7V (MIN)/3.3V (MAX) S_V
CC
read voltage
2.7V (MIN)/3.3V (MAX) F_V
CC
Q
3.0V (TYP) F_V
PP
(in-system PROGRAM/
ERASE)
12V 5% (HV) F_V
PP
(production
programming compatibility)
Asynchronous random access time
Flash access time: 70ns @ 2.7V F_V
CC
(-7)
SRAM access time: 70ns @ 2.7V S_V
CC
Page mode read access time
Interpage read: 70ns @ 2.7V F_V
CC
(-7)
Intrapage read: 30ns @ 2.7V F_V
CC
Low power consumption
Asynchronous read < 16mA
Page mode read < 7mA
Combined standby < 20
A (typ), 70
A (max)
Enhanced suspend options
ERASE-SUSPEND-to-READ within the same
bank
PROGRAM-SUSPEND-to-READ within the
same bank
ERASE-SUSPEND-to-PROGRAM within the
same bank
Read/Write SRAM during program/erase of
Flash
Dual 64-bit chip protection registers for
security purposes
PROGRAM/ERASE cycles
100,000 WRITE/ERASE cycles per block
Cross-compatible command set support
Extended command set
Common Flash interface (CFI) compliant
Operating Temperature Range
Industrial Temperature Range ("I" marking)
-40
C to +85
C
Access Time Options
Flash Memory Access Time
Marking
70ns
-7
80ns
-8
Boot/Parameter Block Location Options
Location & Address
Marking
Top: FFFFFh
T
Bottom: 00000h
B
Ball Assignment 66-Ball FBGA
(Top View)
B
NC
F_WE#
NC
A20
A16
S_Vss
F_WP#
S_LB#
A18
A11
A15
A14
A13
A12
F_Vss F_VccQ
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
A
C
D
E
F
G
H
A8
A10
A9
NC
F_RST#
F_Vpp
S_UB#
A17
A5
NC
NC
NC
NC
NC
S_OE#
A7
A4
A19
DQ15
DQ13
DQ12
S_WE#
DQ11
DQ9
A6
A0
A3
F_CE#
DQ6
S_CE2
DQ10
DQ8
A2
F_Vss
DQ14
DQ4
S_Vcc
DQ2
DQ0
A1
F_OE#
DQ7
DQ5
F_Vcc
DQ3
DQ1
S_CE1#
NC
NanoAmp Solutions, Inc.
N04C1630E3AM
Preliminary
Stock No. 23154-E 1/03
2
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
GENERAL DESCRIPTION
The N04C1630E3AM combination Flash and
SRAM memory device provides a compact, low-
power solution for systems where PCB real estate
is at a premium. The dual-bank Flash is a high-
performance, high-density, nonvolatile memory
device with a revolutionary architecture that can
significantly improve system performance.
This new architecture features:
A two-memory-bank configuration supporting
background operation with no latency
A high-performance bus interface providing
fast page mode read operations
A conventional asynchronous bus interface.
The device also provides soft protection for blocks,
as read only, by configuring soft protection
registers with dedicated command sequences. For
security purposes, dual 64-bit chip protection
registers are provided.
The embedded WORD WRITE and BLOCK
ERASE functions are fully automated by an on-
chip write state machine (WSM). The WSM
simplifies these operations and relieves the system
processor of secondary tasks. Two on-chip status
registers, one for each bank, can be used to
monitor the WSM status to determine the progress
of a PROGRAM/ERASE command.
The erase/program suspend functionality allows
compatibility with existing EEPROM emulation
software packages.
The device takes advantage of a dedicated power
source for the Flash device (F_V
CC
) and a
dedicated power source for the SRAM device
(S_V
CC
), both at 2.7V3.3V for optimized power
consumption and improved noise immunity. The
N04C1630E3AM device supports two V
PP
voltage
ranges; an in-circuit voltage of 1.8V3.3V and
production compatibility voltage of 12V 5%. The
12V 5% V
PP
2
is supported for a maximum of 100
cycles and 10 cumulative hours.
The flash device in the N04C1630E3AM contains
two separate banks of memory (bank a and bank
b) for simultaneous READ and WRITE operations.
Bank a is one-fourth of the memory and
contains 8x4K-word parameter blocks and
15x32K-word blocks
Bank b represents three-fourths of the
memory, is equally sectored and contains
48x32K-word blocks
See Figure 2 and Figure 3 for the bottom and
top memory organizations.
The N04C1630E3AM device also contains an
asynchronous 4Mb SRAM organized as 256K-
words by 16 bits. These devices are fabricated
using an advanced CMOS process and high-
speed/ultra-low-power circuit technology.
The N04C1630E3AM device is packaged in a 66-
ball FBGA package with 0.80mm pitch.
Part Numbering Information
NanoAmp's low-power devices are available with
several different combinations of features (see
Figure 1). Valid combinations of features and their
corresponding part numbers are listed in Table 1.
Figure 1: Part Number Chart
N 04 C 16 30 E3 A M 7T
-
I
NanoAmp Solutions
SRAM Density
Flash/SRAM Combo
I/O Organization
Operating Voltage
Operating Temperature
Performance & Boot Block
Package Type
Die Revision
Flash Density
N 04 C 16 30 E3 A M 7T
-
I
NanoAmp Solutions
SRAM Density
Flash/SRAM Combo
I/O Organization
Operating Voltage
Operating Temperature
Performance & Boot Block
Package Type
Die Revision
Flash Density
Table 1: Valid Part Number Combinations & Product Selection Guide
Part Number
Access Time (ns)
Boot/Parameter
Block Location
Operating Temperature Range
N04C1630E3AM-7BI
70
Bottom
-40
C to +85
C
N04C1630E3AM-7TI
70
Top
-40
C to +85
C
N04C1630E3AM-8BI
80
Bottom
-40
C to +85
C
N04C1630E3AM-8TI
80
Top
-40
C to +85
C
NanoAmp Solutions, Inc.
N04C1630E3AM
Preliminary
Stock No. 23154-E 1/03
3
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
Block Diagram
FLASH Functional Block Diagram
A18- 20
F_CE#
F_WE#
F_OE#
F_RST#
A0 -17
S_CE1#
S_CE2
S_OE#
S_WE#
F_Vcc
F_Vpp
F_Vss
DQ0 -15
F_WP#
FLASH
2,048Kb x 16
SRAM
256Kb x 16
F_VccQ
S_Vcc
S_Vss
S_UB#
S_LB#
Data Input
Buffer
A/0-A20
DQ0-DQ15
Data
Register
Address
CNT/W/5M
Address
Multiplexer
CSM
I/O Logic
Address
Input
Buffer
WSM
Address
Latch
Y/Z DEC
X DEC
X DEC
Y/Z DEC
Y/Z
Gating/Sensing
Bank 2 Blocks
Bank 1 Blocks
Query/OTP
PR Lock
Y/Z
Gating/Sensing
Status
Reg.
PR Lock
Query
OTP
Manufacturer's ID
Device ID
Block Lock
RCR
ID Reg.
DQ0-DQ15
Output
Multiplexer
Output
Buffer
F_RST#
F_CE#
F_WE#
F_OE#
Program
Erase
Pump
Voltage
Generators
NanoAmp Solutions, Inc.
N04C1630E3AM
Preliminary
Stock No. 23154-E 1/03
4
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
Ball Descriptions
66-Ball FBGA
Numbers
Symbol
Type
Description
A3, A4, A5, A6, A7, A8,
B3, B4, B5, B6, E5, G3,
G4, G5, G6, G7, G8,
G9, H4, H5, H6
A0A20
Input Address Inputs: Inputs for the addresses during READ and WRITE
operations. The Flash memory uses address lines: A0A20. The SRAM
uses address lines: A0A17.
H7
F_CE#
Input Flash Chip Enable: Activates the flash device when LOW. When CE# is
HIGH, the flash device is disabled and goes into standby power mode.
H9
F_OE#
Input Flash Output Enable: Enables flash output buffers when LOW. When
F_OE# is HIGH, the output buffers are disabled.
C3
F_WE#
Input Flash Write Enable: Determines if a given cycle is a Flash WRITE cycle.
F_WE# is active LOW.
D4
F_RST#
Input
Reset. When F_RST# is a logic LOW, the flash device is in reset, which
drives the outputs to High-Z and resets the WSM. When F_RST# is a
logic HIGH, the flash device is in standard operation. When F_RST#
transitions from logic LOW to logic HIGH, the flash device resets all
blocks to locked and defaults to the read array mode.
E3
F_WP#
Input Flash Write Protect. Controls the lock down function of the flexible
locking feature.
G10
S_CE1#
Input SRAM Chip Enable1: Activates the SRAM when it is LOW. HIGH level
deselects the SRAM and reduces the power consumption to standby
levels.
D8
S_CE2
Input SRAM Chip Enable2: Activates the SRAM when it is HIGH. LOW level
deselects the SRAM and reduces the power consumption to standby
levels.
F5
S_OE#
Input SRAM Output Enable: Enables SRAM output buffers when LOW. When
S_OE# is HIGH, the output buffers are disabled.
B8
S_WE#
Input SRAM Write Enable: Determines if a given cycle is an SRAM WRITE
cycle. S_WE# is active LOW.
F3
S_LB#
Input SRAM Lower Byte: When LOW, it selects the SRAM address lower byte
(DQ0DQ7).
F4
S_UB#
Input SRAM Upper Byte: When LOW, it selects the SRAM address upper byte
(DQ8DQ15).
B7, B9, B10, C7, C8,
C9, C10, D7, E6, E8,
E9, E10, F7, F8, F9,
F10
DQ0DQ15 Input/
Output
Data Inputs/Outputs: Input array data on the second CE# and WE# cycle
during PROGRAM command. Input commands to the command user
interface when CE# and WE# are active. Output data when CE# and
OE# are active.
E4
F_VPP
Input/
Supply
Flash Program/Erase Power Supply: [1.8V3.3V or 11.4V12.6V].
Operates as input at logic levels to control complete device protection.
Provides backward compatibility for factory programming when driven
D10
F_VCC
Supply Flash Power Supply: [2.7V3.3V]. Supplies power for device operation.
A9, H8
F_VSS
Supply Flash Specific Ground: Do not float any ground pin.
D9
S_VCC
Supply SRAM Power Supply: [2.7V3.3V]. Supplies power for device operation.
D3
S_VSS
Supply SRAM Specific Ground: Do not float any ground pin.
A10
F_VCCQ Supply Flash I/O Power Supply: [2.7V3.3V].
A1, A2, A11, A12, C4,
H1, H2, H3, H10, H11,
H12
NC
No Connect: Lead is not internally connected; it may be driven or
floated.
NanoAmp Solutions, Inc.
N04C1630E3AM
Preliminary
Stock No. 23154-E 1/03
5
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NOTE:
1. Two devices may not drive the memory bus at the same
time.
2. Allowable flash read modes include read array, read query,
read configuration, and read status.
3. Outputs are dependent on a separate device controlling
bus outputs.
4. Only one device can output to the shared bus at a time.
5. SRAM is enabled and/or disabled with the logical function:
S_CE1# or S_CE2.
6. Simultaneous operations can exist, as long as the opera-
tions are interleaved such that only one device attempts to
control the bus outputs at a time.
7. Data output on lower byte only; upper byte High-Z.
8. Data output on upper byte only; lower byte High-Z.
9. Data input on lower byte only.
10. Data input on upper byte only.
Truth Table FLASH
Modes
FLASH Signals
SRAM Signals
Memory Output
Notes
F_RST# F_CE# F_OE# F_WE# S_CE1# S_CE2 S_OE# S_WE# S_UB# S_LB#
Memory
Bus
Control
DQ0
DQ15
Read
H
L
L
H
SRAM must be High-Z
Flash
D
OUT
1, 2, 3
Write
H
L
H
L
Flash
D
IN
1
Standby
H
H
X
X
SRAM any mode allowable
Other
High-Z
4
Output
Disable
H
L
H
H
Other
High-Z
4, 5
Reset
L
X
X
X
Other
High-Z
4, 6
Truth Table SRAM
Modes
FLASH Signals
SRAM Signals
Memory Output
Notes
F_RST# F_CE# F_OE# F_WE# S_CE1# S_CE2 S_OE# S_WE# S_UB# S_LB#
Memory
Bus
Control
DQ0
DQ15
Read
Flash must be High-Z
DQ0
DQ15
L
H
L
H
L
L
SRAM
D
OUT
1, 3
DQ0
DQ7
L
H
L
H
H
L
SRAM D
OUT
LB
7
DQ8
DQ15
L
H
L
H
L
H
SRAM D
OUT
UB
8
Write
DQ0
DQ15
L
H
H
L
L
L
SRAM
D
IN
1, 3
DQ0
DQ7
L
H
H
L
H
L
SRAM
D
IN
LB
9
DQ8
DQ15
L
H
H
L
L
H
SRAM
D
IN
UB
10
Standby
Flash any mode allowable
H
X
X
X
X
X
Other
High-Z
4
X
L
X
X
X
X
Other
High-Z
4
Output
Disable
L
H
X
X
X
X
Other
High-Z
4