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Электронный компонент: N04L1618C2AX-XXX

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NanoAmp Solutions, Inc.
1982 Zanker Road, San Jose, CA 95112
ph: 408-573-8878, FAX: 408-573-8877
www.nanoamp.com
N04L1618C2A
Stock No. 23127-06 5/03
1
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
4Mb Ultra-Low Power Asynchronous CMOS SRAM
256Kx16 bit
Overview
The N04L1618C2A is an integrated memory
device containing a 4 Mbit Static Random Access
Memory organized as 262,144 words by 16 bits.
The device is designed and fabricated using
NanoAmp's advanced CMOS technology to
provide both high-speed performance and ultra-low
power. The base design is the same as
NanoAmp's N04L163WC1A, which is processed to
operate at higher voltages. The device operates
with two chip enable (CE1 and CE2) controls and
output enable (OE) to allow for easy memory
expansion. Byte controls (UB and LB) allow the
upper and lower bytes to be accessed
independently and can also be used to deselect
the device. The N04L1618C2A is optimal for
various applications where low-power is critical
such as battery backup and hand-held devices.
The device can operate over a very wide
temperature range of -40
o
C to +85
o
C and is
available in JEDEC standard packages compatible
with other standard 256Kb x 16 SRAMs
Features
Single Wide Power Supply Range
1.65 to 2.2 Volts
Very low standby current
0.5A at 1.8V (Typical)
Very low operating current
0.7mA at 1.8V and 1s (Typical)
Low Page Mode operating current
0.5mA at 1.8V and 1s (Typical)
Simple memory control
Dual Chip Enables (CE1 and CE2)
Byte control for independent byte operation
Output Enable (OE) for memory expansion
Low voltage data retention
Vcc = 1.2V
Very fast output enable access time
25ns OE access time
Automatic power down to standby mode
TTL compatible three-state output driver
Compact space saving BGA package avail-
able
Pin Configuration
Product Family
Part Number
Package
Type
Operating
Temperature
Power
Supply (Vcc)
Speed
Standby
Current (I
SB
),
Typical
Operating
Current (Icc),
Typical
N04L1618C2AB
48 - BGA
-40
o
C to +85
o
C
1.65V - 2.2V
70ns @ 1.8V
0.5
A
0.7 mA @
1MHz
85ns @ 1.65V
1
2
3
4
5
6
A
LB
OE
A
0
A
1
A
2
CE2
B
I/O
8
UB
A
3
A
4
CE1
I/O
0
C
I/O
9
I/O
10
A
5
A
6
I/O
1
I/O
2
D
V
SS
I/O
11
A
17
A
7
I/O
3
V
CC
E
V
CC
I/O
12
NC
A
16
I/O
4
V
SS
F
I/O
14
I/O
13
A
14
A
15
I/O
5
I/O
6
G
I/O
15
NC
A
12
A
13
WE
I/O
7
H
NC
A
8
A
9
A
10
A
11
NC
48 Pin BGA (top)
6 x 8 mm
Pin Descriptions
Pin Name
Pin Function
A
0
-A
17
Address Inputs
WE
Write Enable Input
CE1, CE2
Chip Enable Input
OE
Output Enable Input
LB
Lower Byte Enable Input
UB
Upper Byte Enable Input
I/O
0
-I/O
15
Data Inputs/Outputs
V
CC
Power
V
SS
Ground
NC
Not Connected
Stock No. 23127-06 5/03
2
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N04L1618C2A
Functional Block Diagram
Functional Description
CE1
CE2
WE
OE
UB
LB
I/O
0
- I/O
15
1
1. When UB and LB are in select mode (low), I/O
0
- I/O
15
are affected as shown. When LB only is in the select mode only I/O
0
- I/O
7
are affected as shown. When UB is in the select mode only I/O
8
- I/O
15
are affected as shown.
MODE
POWER
H
X
X
X
X
X
High Z
Standby
2
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
Standby
X
L
X
X
X
X
High Z
Standby
2
Standby
X
X
X
X
H
H
High Z
Standby
2
Standby
L
H
L
X
3
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
L
1
L
1
Data In
Write
3
Active -> Standby
4
4. The device will consume active power in this mode whenever addresses are changed. Data inputs are internally isolated from
any expernal influence.
L
H
H
L
L
1
L
1
Data Out
Read
Active -> Standby
4
L
H
H
H
L
1
L
1
High Z
Active
Standby
4
Capacitance
1
1. These parameters are verified in device characterization and are not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input Capacitance
C
IN
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
8
pF
I/O Capacitance
C
I/O
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
8
pF
Address
Inputs
A0 - A3
Address
Inputs
A4 - A17
Word
Address
Decode
Logic
16K Page
x 16 word
x 16 bit
RAM Array
W
o
rd Mux
Input/
Output
Mux
and
Buffers
Page
Address
Decode
Logic
Control
Logic
CE1
CE2
WE
OE
UB
LB
I/O0 - I/O7
I/O8 - I/O15
Stock No. 23127-06 5/03
3
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N04L1618C2A
Absolute Maximum Ratings
1
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Symbol
Rating
Unit
Voltage on any pin relative to V
SS
V
IN,OUT
0.3 to V
CC
+0.3
V
Voltage on V
CC
Supply Relative to V
SS
V
CC
0.3 to 3.0
V
Power Dissipation
P
D
500
mW
Storage Temperature
T
STG
40 to 125
o
C
Operating Temperature
T
A
-40 to +85
o
C
Soldering Temperature and Time
T
SOLDER
240
o
C, 10sec(Lead only)
o
C
Operating Characteristics (Over Specified Temperature Range)
Item
Symbol
Test Conditions
Min.
Typ
1
1. Typical values are measured at Vcc=Vcc Typ., T
A
=25C and not 100% tested.
Max
Unit
Supply Voltage
V
CC
1.65
1.8
2.2
V
Data Retention Voltage
V
DR
Chip Disabled
3
1.2
2.2
V
Input High Voltage
V
IH
0.7V
CC
V
CC
+0.3
V
Input Low Voltage
V
IL
0.3
0.3V
CC
V
Output High Voltage
V
OH
I
OH
= 0.2mA
V
CC
0.2
V
Output Low Voltage
V
OL
I
OL
= -0.2mA
0.3
V
Input Leakage Current
I
LI
V
IN
= 0 to V
CC
0.5
A
Output Leakage Current
I
LO
OE = V
IH
or Chip Disabled
0.5
A
Read/Write Operating Supply Current
@ 1
s Cycle Time
2
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive
output capacitance expected in the actual system.
I
CC1
VCC=2.2V, V
IN
=V
IH
or V
IL
Chip Enabled, IOUT = 0
0.7
3.0
mA
Read/Write Operating Supply Current
@ 70 ns Cycle Time
2
I
CC2
VCC=2.2V, V
IN
=V
IH
or V
IL
Chip Enabled, IOUT = 0
8.0
17.0
mA
Page Mode Operating Supply Current
@ 70ns Cycle Time
2
(Refer to Power
Savings with Page Mode Operation
diagram)
I
CC3
VCC=2.2V, V
IN
=V
IH
or V
IL
Chip Enabled, IOUT = 0
4.0
mA
Read/Write Quiescent Operating Sup-
ply Current
3
3. This device assumes a standby mode if the chip is disabled (CE1 high or CE2 low). In order to achieve low standby current all
inputs must be within 0.2 volts of either V
CC
or V
SS
.
I
CC4
V
CC
=2.2V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0,
f = 0
10
A
Maximum Standby Current
3
I
SB1
V
IN
= V
CC
or 0V
Chip Disabled
t
A
= 85
o
C, V
CC
= 2.2V
0.5
10.0
A
Maximum Data Retention Current
3
I
DR
V
CC
= 1.2V, V
IN
= V
CC
or 0
Chip Disabled, t
A
= 85
o
C
10
A
Stock No. 23127-06 5/03
4
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N04L1618C2A
Power Savings with Page Mode Operation (WE = V
IH
)
Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal
organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power
saving feature.
The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open
and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant
bits and addressing the 16 words within the open page, power is reduced to the page mode value which is
considerably lower than standard operating currents for low power SRAMs.
Page Address (A4 - A17)
LB, UB
OE
CE1
CE2
Word Address (A0 - A3)
Open page
Word 1
Word 2
Word 16
...
Stock No. 23127-06 5/03
5
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N04L1618C2A
Timing Test Conditions
Item
Input Pulse Level
0.1V
CC
to 0.9 V
CC
Input Rise and Fall Time
5ns
Input and Output Timing Reference Levels
0.5 V
CC
Output Load
30pF
Operating Temperature
-40 to +85
o
C
Timing
Item
Symbol
1.65 - 2.2 V
1.8 - 2.2 V
Units
Min.
Max.
Min.
Max.
Read Cycle Time
t
RC
85
70
ns
Address Access Time
t
AA
85
70
ns
Chip Enable to Valid Output
t
CO
85
70
ns
Output Enable to Valid Output
t
OE
30
25
ns
Byte Select to Valid Output
t
LB
, t
UB
85
70
ns
Chip Enable to Low-Z output
t
LZ
10
10
ns
Output Enable to Low-Z Output
t
OLZ
5
5
ns
Byte Select to Low-Z Output
t
LBZ
, t
UBZ
10
10
ns
Chip Disable to High-Z Output
t
HZ
10
30
10
25
ns
Output Disable to High-Z Output
t
OHZ
10
30
10
25
ns
Byte Select Disable to High-Z Output
t
LBHZ
, t
UBHZ
10
30
10
25
ns
Output Hold from Address Change
t
OH
5
5
ns
Write Cycle Time
t
WC
85
70
ns
Chip Enable to End of Write
t
CW
50
40
ns
Address Valid to End of Write
t
AW
50
40
ns
Byte Select to End of Write
t
LBW
, t
UBW
50
40
ns
Write Pulse Width
t
WP
50
40
ns
Address Setup Time
t
AS
0
0
ns
Write Recovery Time
t
WR
0
0
ns
Write to High-Z Output
t
WHZ
25
20
ns
Data to Write Time Overlap
t
DW
40
40
ns
Data Hold from Write Time
t
DH
0
0
ns
End Write to Low-Z Output
t
OW
10
10
ns