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Электронный компонент: N16L163WC2CT1

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NanoAmp Solutions, Inc.
670 North McCarthy Blvd. Suite 220, Milpitas, CA 95035
ph: 408-935-7777, FAX: 408-935-7770
www.nanoamp.com
N16L163WC2C
Stock No. 23383-C
1
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
Advance Information
16Mb Ultra-Low Power Asynchronous CMOS SRAM
1024K 16 bit
Overview
The N16L163WC2C is an integrated memory
device containing a 8Mbit Static Random Access
Memory organized as 1,048,576 words by 16 bits.
The device is designed and fabricated using
NanoAmp's advanced CMOS technology to
provide both high-speed performance and ultra-low
power. The device operates with two chip enable
(CE1 and CE2) controls and output enable (OE) to
allow for easy memory expansion. Byte controls
(UB and LB) allow the upper and lower bytes to be
accessed independently and can also be used to
deselect the device. The N16L163WC2C is optimal
for various applications where low-power is critical
such as battery backup and hand-held devices.
The device can operate over a very wide
temperature range of -40
o
C to +85
o
C and is
available in JEDEC standard packages compatible
with other standard 1024Kb x 16 SRAMs
Features
Single Wide Power Supply Range
2.2 to 3.6 Volts
Very low standby current
2.5A at 3.0V (Typical)
Very low operating current
2.0mA at 3.0V and 1s(Typical)
Simple memory control
Dual Chip Enables (CE1 and CE2)
Byte control for independent byte operation
Output Enable (OE) for memory expansion
Low voltage data retention
Vcc = 1.5V
Very fast output enable access time
25ns OE access time
Automatic power down to standby mode
TTL compatible three-state output driver
Ultra Low Power Sort Available
Product Family
Part Number
Package Type
Operating
Temperature
Power
Supply (Vcc)
Speed
Standby
Current
(I
SB
),
Typical
Operating Current
(Icc), Typical
N16L163WC2CT1
48 TSOP I Pb-Free
-40
o
C to +85
o
C
2.2V - 3.6V
55ns
2.5
A
2 mA @ 1MHz
N16L163WC2CZ1
VFBGA Pb-Free
Stock No. 23383-C
2
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N16L163WC2C
Advance Information
Pin Configuration
Note: Pin#47 on the TSOP-I Package must be tied to Vcc.
Pin Descriptions
Pin Name
Pin Function
A
0
-A
19
Address Inputs
WE
Write Enable Input
CE1, CE2
Chip Enable Input
OE
Output Enable Input
LB
Lower Byte Enable Input
UB
Upper Byte Enable Input
I/O
0
-I/O
15
Data Inputs/Outputs
V
CC
Power
V
SS
Ground
NC
Not Connected
DNU
Do Not Use
1
2
3
4
5
6
A
LB
OE
A
0
A
1
A
2
CE2
B
I/O
8
UB
A
3
A
4
CE1
I/O
0
C
I/O
9
I/O
10
A
5
A
6
I/O
1
I/O
2
D
V
SS
I/O
11
A
17
A
7
I/O
3
V
CC
E
V
CC
I/O
12
DNU
A
16
I/O
4
V
SS
F
I/O
14
I/O
13
A
14
A
15
I/O
5
I/O
6
G
I/O
15
A
19
A
12
A
13
WE
I/O
7
H
A18
A
8
A
9
A
10
A
11
DNU
48 Pin VFBGA (top)
8 x 10 mm
48-Pin
TSOP-I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
CE2
DNU
UB
LB
A18
A17
A7
A6
A5
A4
A3
A2
A1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
Vcc*
Vss
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE1
A0
Stock No. 23383-C
3
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N16L163WC2C
Advance Information
Functional Block Diagram
Functional Description
CE1
CE2
WE
OE
UB
LB
I/O
0
- I/O
15
1
1. When UB and LB are in select mode (low), I/O
0
- I/O
15
are affected as shown. When LB only is in the select mode only I/O
0
- I/O
7
are affected as shown. When UB is in the select mode only I/O
8
- I/O
15
are affected as shown.
MODE
POWER
H
X
X
X
X
X
High Z
Standby
2
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
Standby
X
L
X
X
X
X
High Z
Standby
2
Standby
X
X
X
X
H
H
High Z
Standby
2
Standby
L
H
L
X
3
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
L
1
L
1
Data In
Write
3
Active
L
H
H
L
L
1
L
1
Data Out
Read
Active
L
H
H
H
L
1
L
1
High Z
Active
Active
Capacitance
1
1. These parameters are verified in device characterization and are not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input Capacitance
C
IN
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
8
pF
I/O Capacitance
C
I/O
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
10
pF
Address
Inputs
A0 - A3
Address
Inputs
A4 - A19
Word
Address
Decode
Logic
1024K
x 16 bit
RAM Array
W
o
rd Mux
Input/
Output
Mux
and
Buffers
Page
Address
Decode
Logic
Control
Logic
CE1
CE2
WE
OE
UB
LB
I/O0 - I/O7
I/O8 - I/O15
Stock No. 23383-C
4
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N16L163WC2C
Advance Information
Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Absolute Maximum Ratings
Item
Symbol
Rating
Unit
Voltage on any pin relative to V
SS
V
IN,OUT
0.3 to V
CC
+0.3
V
Voltage on V
CC
Supply Relative to V
SS
V
CC
0.3 to 4.5
V
Power Dissipation
P
D
500
mW
Storage Temperature
T
STG
65 to 150
o
C
Operating Temperature
T
A
-40 to +85
o
C
Soldering Temperature and Time
T
SOLDER
260
o
C, 10sec
o
C
Operating Characteristics (Over Specified Temperature Range)
Item
Symbol
Test Conditions
Min.
Typ
1
1. Typical values are measured at Vcc=Vcc Typ., T
A
=25C and not 100% tested.
Max
Unit
Supply Voltage
V
CC
2.2
3.0
3.6
V
Data Retention Voltage
V
DR
Chip Disabled
1.5
V
Input High Voltage
V
IH
Vcc = 2.2V to 2.7V
1.8
V
CC
+0.3
V
Vcc = 2.7V to 3.6V
2.2
V
CC
+0.3
Input Low Voltage
V
IL
Vcc = 2.2V to 2.7V
-0.3
0.6
V
Vcc = 2.7V to 3.6V
-0.3
0.8
Output High Voltage
V
OH
I
OH
= -0.1mA, Vcc = 2.2V
2.0
V
I
OH
= -1.0mA, Vcc = 2.7V
2.4
Output Low Voltage
V
OL
I
OL
= 0.1mA, Vcc = 2.2V
0.4
V
I
OL
= 0.1mA, Vcc = 2.7V
0.4
Input Leakage Current
I
LI
V
IN
= 0 to V
CC
-1
1
A
Output Leakage Current
I
LO
OE = V
IH
or Chip Disabled
-1
1
A
Read/Write Operating Supply Cur-
rent @ 1
s Cycle Time
2
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive
output capacitance expected in the actual system.
I
CC1
V
CC
=3.6 V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0
2
4.0
mA
-L
2
4.0
Read/Write Operating Supply
Current @ fmax
I
CC2
V
CC
=3.6 V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0
15
30
mA
-L
15
30
Maximum Standby Current
I
SB1
V
IN
= V
CC
or 0V
Chip Disabled
t
A
= 85
o
C, V
CC
= 3.6 V
2.5
30
A
-L
2.5
22
Maximum Data Retention Current
I
DR
Vcc = 1.5V, V
IN
= V
CC
or 0
Chip Disabled, t
A
= 85
o
C
15
A
-L
10
Stock No. 23383-C
5
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N16L163WC2C
Advance Information
Note:
1. Full Device AC operation requires linear Vcc ramp from 0 to Vcc(min)
500us.
2. Full Device operation requires linear Vcc ramp from V
DR
to Vcc(min)
100 us or stable at Vcc(min) 100us.
3. Address valid prior to or coincident with CE1, LB, UB transition LOW and CE2 transition HIGH.
Timing Test Conditions
Item
Input Pulse Level
0.1V
CC
to 0.9 V
CC
Input Rise and Fall Time
1V/ns
Input and Output Timing Reference Levels
0.5 V
CC
Output Load
CL = 50pF
Operating Temperature
-40 to +85
o
C
Timing
Item
Symbol
55
Units
Min
Max
Read Cycle Time
t
RC
55
ns
Address Access Time (Random Access)
t
AA
55
ns
Chip Enable to Valid Output
t
CO
55
ns
Output Enable to Valid Output
t
OE
25
ns
Byte Select to Valid Output
t
LB
, t
UB
55
ns
Chip Enable to Low-Z output
t
LZ
10
ns
Output Enable to Low-Z Output
t
OLZ
5
ns
Byte Select to Low-Z Output
t
LBZ
, t
UBZ
10
ns
Chip Disable to High-Z Output
t
HZ
20
ns
Output Disable to High-Z Output
t
OHZ
20
ns
Byte Select Disable to High-Z Output
t
LBHZ
, t
UBHZ
20
ns
Output Hold from Address Change
t
OH
10
ns
Write Cycle Time
t
WC
55
ns
Chip Enable to End of Write
t
CW
40
ns
Address Valid to End of Write
t
AW
40
ns
Byte Select to End of Write
t
LBW
, t
UBW
40
ns
Write Pulse Width
t
WP
40
ns
Address Setup Time
t
AS
0
ns
Write Recovery Time
t
WR
0
ns
Write to High-Z Output
t
WHZ
20
ns
Data to Write Time Overlap
t
DW
25
ns
Data Hold from Write Time
t
DH
0
ns
End Write to Low-Z Output
t
OW
10
ns