NanoAmp Solutions, Inc.
1982 Zanker Road, San Jose, CA 95112
ph: 408-573-8878, FAX: 408-573-8877
www.nanoamp.com
N16T1618C2(D1/A1)A
Stock No. 23183 - 04 4/03
1
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
Advance Information
16Mb Ultra-Low Power Asynchronous CMOS PSRAM
1M x 16 bit
Overview
The N16T1618C2(D1/A1)A is an integrated
memory device containing a 16 Mbit Pseudo Static
Random Access Memory using a self-refresh
DRAM array organized as 1,048,576 words by 16
bits. It is designed to be compatible in operation
and interface to standard 6T SRAMS. The device
is designed for low standby and operating current
and includes a power-down feature to
automatically enter standby mode. The device is
available in a 2 CE (chip enable) version and two
ZZ (deep sleep) versions. The ZZ version includes
several power saving modes: a deep sleep mode
where data is not retained in the array and partial
array refresh mode where data is retained in a
portion of the array. Both these modes reduce
standby current drain. The VFBGA package has
separate power rails, VccQ and VssQ for the I/O to
be run from a separate power supply from the
device core.
Features
Dual voltage for Optimum Performance
V
CCQ
and V
SSQ
for separate I/O power rails
Vcc - 1.65V to 2.2 V
Vccq - 1.65V to 3.6V
Fast Cycle Times
T
ACC
< 85 nS
Very low standby current
I
SB
< 40A @ 1.8V
Very low operating current
Icc < 25mA
Memory expansion with CE and OE
Automatic power down mode
48-Pin VFBGA, Wafers Available
Pin Configuration
Product Family
Part Number
Feature
Package
Type
Operating
Temperature
Power
Supply
Speed
Standby
Current (I
SB
),
Max
Operating
Current
(Icc), Max
N16T1618C2AZ
2 CE
48 - BGA
-30
o
C to +85
o
C
1.65V - 2.2V
85ns @ 1.65V
40
A @ 1.8V
3 mA @ 1MHz
N16T1618D1AZ
Deep Sleep Disabled
N16T1618A1AZ
Deep Sleep Active
1
2
3
4
5
6
A
LB
OE
A
0
A
1
A
2
CE2/
ZZ
B
I/O
8
UB
A
3
A
4
CE1
I/O
0
C
I/O
9
I/O
10
A
5
A
6
I/O
1
I/O
2
D
V
SSQ
I/O
11
A
17
A
7
I/O
3
V
CC
E
V
CCQ
I/O
12
DNU
A
16
I/O
4
V
SS
F
I/O
14
I/O
13
A
14
A
15
I/O
5
I/O
6
G
I/O
15
A
19
A
12
A
13
WE
I/O
7
H
A
18
A
8
A
9
A
10
A
11
NC
48 Pin BGA (top)
6 x 8 mm
Pin Descriptions
Pin Name
Pin Function
A
0
-A
19
Address Inputs
WE
Write Enable Input
CE1
Chip Enable Input
CE2
Chip Enable Input (only for CE2
device)
ZZ
Deep Sleep Input (only for A1 or D1
deep sleep device)
OE
Output Enable Input
LB
Lower Byte Enable Input
UB
Upper Byte Enable Input
I/O
0
-I/O
15
Data Inputs/Outputs
V
CC
Power
V
SS
Ground
V
CCQ
Power I/O pin only
V
SSQ
Ground I/O pin only
DNU
Do Not Use (or connect to V
SS
)
Stock No. 23183 - 04 4/03
2
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N16T1618C2(D1/A1)A
Advance Information
Functional Block Diagram
Functional Description
CE1
CE2
1
WE
OE
UB/LB
ZZ
2
I/O
3
MODE
POWER
H
X
X
X
X
H
High Z
Standby
4
Standby
X
L
X
X
X
H
High Z
Standby
4
Standby
X
X
X
X
H
H
High Z
Standby
4
Standby
L
H
L
X
5
L
3
H
Data In
Write
5
Active -> Standby
6
L
H
H
L
L
3
H
Data Out
Read
Active -> Standby
6
L
H
H
H
L
3
H
High Z
Active
Standby
6
1.) Only on the two-CE option device.
2. Only on the one-CE option device with sleep mode.
3. When UB and LB are in select mode (low), I/O
0
- I/O
15
are affected as shown. When LB only is in the select mode only I/O
0
- IO
7
are affected as shown. When UB is in the select mode only I/O
8
- I/O
15
are affected as shown. If both UB and LB are in the deselect
mode (high), the chip is in a standby mode regardless of the state of CE1 or CE2.
4. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
5. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
6. The device will consume active power in this mode whenever addresses are changed. Data inputs are internally isolated from any
external influence.
Capacitance
1
1. These parameters are verified in device characterization and are not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input Capacitance
C
IN
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
8
pF
I/O Capacitance
C
I/O
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
8
pF
Control
Logic
Decode
Logic
Address
Inputs
A
0
- A
19
CE1
WE
OE
Input/
Output
Mux
and
Buffers
I/O
0
- I/O
7
UB
LB
I/O
8
- I/O
15
Address
CE2
1
1024K x 16
Memory
Array
ZZ
2
Stock No. 23183 - 04 4/03
3
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N16T1618C2(D1/A1)A
Advance Information
Absolute Maximum Ratings
1
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Symbol
Rating
Unit
Voltage on any pin relative to V
SS
V
IN,OUT
0.3 to V
CC
+0.3
V
Voltage on V
CC
Supply Relative to V
SS
V
CC
0.3 to 4.0
V
Power Dissipation
P
D
500
mW
Storage Temperature
T
STG
40 to 125
o
C
Operating Temperature
T
A
-30 to +85
o
C
Soldering Temperature and Time
T
SOLDER
240
o
C, 10sec(Lead only)
o
C
Operating Characteristics (Over Specified Temperature Range)
Item
Symbol
Comments
Min.
Typ
1
1. Typical values are measured at Vcc=Vcc Typ., T
A
=25C and not 100% tested.
Max.
Unit
Supply Voltage
V
CC
N16T1618
1.65
1.8
2.2
V
Supply Voltage for I/O
V
CCQ
1.65
3.6
V
Input High Voltage
V
IH
1.4
Vcc
V
Input Low Voltage
V
IL
0.3
0.4
V
Output High Voltage
V
OH
I
OH
= -0.2mA
0.8V
CCQ
V
Output Low Voltage
V
OL
I
OL
= 0.2mA
0.2
V
Input Leakage Current
I
LI
V
IN
= 0 to V
CC
0.5
A
Output Leakage Current
I
LO
OE = V
IH
or Chip Disabled
0.5
A
Read/Write Operating Supply Current
@ 1
s Cycle Time
2
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive
output capacitance expected in the actual system.
I
CC1
V
CC
=V
CC
MAX, V
IN
=V
IH
/ V
IL
Chip Enabled, I
OUT
= 0
4
mA
Read/Write Operating Supply Current
@ 70 ns Cycle Time
2
I
CC2
V
CC
=V
CC
MAX, V
IN
=V
IH
/ V
IL
Chip Enabled, I
OUT
= 0
25
mA
Standby Current
3
3. This device assumes a standby mode if the chip is disabled (CE1 high or CE2 low). In order to achieve low standby current all
inputs must be within 0.2 volts of either VCC or VSS.
I
SB1
V
IN
= V
CC
or 0V
Chip Disabled
t
A
= 30
o
C
tbd
A
I
SB2
t
A
= 85
o
C, V
CC
= 1.8V
40
A
t
A
= 85
o
C, V
CC
= 2.0V
70
A
t
A
= 85
o
C, V
CC
= 2.2V
100
A
Stock No. 23183 - 04 4/03
4
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N16T1618C2(D1/A1)A
Advance Information
Output Load Circuit
Timing Test Conditions
Item
Input Pulse Level
0.1V
CC
to 0.9 V
CC
Input Rise and Fall Time
5ns
Input Timing Reference Levels
0.5 V
CC
Output Timing Reference Levels
0.5 V
CCQ
Operating Temperature
-30
o
C to +85
o
C
V
CCQ
50 pF
I/O
14.5K
14.5K
Output Load
Stock No. 23183 - 04 4/03
5
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N16T1618C2(D1/A1)A
Advance Information
Timings
Item
Symbol
Min.
Max.
Unit
Read
Cycle
Read Cycle Time
t
RC
85
ns
Address Access Time
t
AA
85
ns
Chip Enable to Valid Output
t
CO
85
ns
Output Enable to Valid Output
t
OE
15
ns
Byte Select to Valid Output
t
LB
, t
UB
85
ns
Chip Enable to Low-Z output
t
LZ
10
ns
Output Enable to Low-Z Output
t
OLZ
5
ns
Byte Select to Low-Z Output
t
LBZ
, t
UBZ
10
ns
Chip Disable to High-Z Output
t
HZ
0
20
ns
Output Disable to High-Z Output
t
OHZ
0
20
ns
Byte Select Disable to High-Z Output t
LBHZ
, t
UBHZ
0
20
ns
Output Hold from Address Change
t
OH
5
ns
Write
Cycle
Write Cycle Time
t
WC
85
ns
Chip Enable to End of Write
t
CW
85
ns
Address Valid to End of Write
t
AW
85
ns
Byte Select to End of Write
t
LBW
, t
UBW
85
ns
Write Pulse Width
t
WP
65
30000
ns
Write Recovery Time
t
WR
0
ns
Write to High-Z Output
t
WHZ
20
ns
Address Setup Time
t
AS
0
ns
Data to Write Time Overlap
t
DW
25
ns
Data Hold from Write Time
t
DH
0
ns
End Write to Low-Z Output
t
OW
5
ns
All Cycle
Address Skew
t
SK
10
ns
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