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Электронный компонент: N32T1618C1B

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NanoAmp Solutions, Inc.
1982 Zanker Road, San Jose, CA 95112
ph: 408-573-8878, FAX: 408-573-8877
www.nanoamp.com
N32T1618C1B
Stock No. 23279 - Rev A 6/03
1
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
Advance Information
32Mb Ultra-Low Power Asynchronous CMOS PSRAM
2M x 16 bit
Overview
The N32T1618C1B is an integrated memory
device containing a 32 Mbit Pseudo Static Random
Access Memory using a self-refresh DRAM array
organized as 2,097,152 words by 16 bits. It is
designed to be compatible in operation and
interface to standard 6T SRAMS. The device is
designed for low standby and operating current
and includes a power-down feature to
automatically enter standby mode. The device
includes a ZZ input for deep sleep as well as
several other power saving modes: partial array
refresh mode where data is retained in a portion of
the array and temperature compensated refresh.
Both these modes reduce standby current drain.
The N32T1618C1B can be operated in a standard
asynchronous mode and data can also be read in a
4-word page mode for fast access times. The
VFBGA package has separate power rails, VccQ
and VssQ for the I/O to be run from a separate
power supply from the device core.
Features
Dual voltage rails for optimum power & per-
formance
Vcc 1.70V to 1.95V
VccQ 1.70V1.95V
VccQ 2.3V2.7V
VccQ 2.7V3.3V
Fast Cycle Times
T
ACC
< 60 nS
T
PACC
< 15 nS
Very low standby current
I
SB
< 70A
Very low operating current
Icc < 25mA
PASR (Partial Array Self Refresh)
TCR (Temperature Compensated Refresh)
48-Pin VFBGA, Wafers Available
Figure 1: Pin Configuration
Table 1: Product Family
Part Number
Package
Type
Operating
Temperature
Power
Supply
Speed
Standby
Current (I
SB
),
Max
Operating
Current (Icc),
Max
N32T1618C1BZ
48 - BGA
-25
o
C to +85
o
C
1.70V - 1.95
60/70 ns
70
A
3 mA @ 1MHz
1
2
3
4
5
6
A
LB
OE
A
0
A
1
A
2
ZZ
B
I/O
8
UB
A
3
A
4
CE
I/O
0
C
I/O
9
I/O
10
A
5
A
6
I/O
1
I/O
2
D
V
SSQ
I/O
11
A
17
A
7
I/O
3
V
CC
E
V
CCQ
I/O
12
NC
A
16
I/O
4
V
SS
F
I/O
14
I/O
13
A
14
A
15
I/O
5
I/O
6
G
I/O
15
A
19
A
12
A
13
WE
I/O
7
H
A
18
A
8
A
9
A
10
A
11
A
20
48 Pin BGA (top)
6 x 8 mm
Table 2: Pin Descriptions
Pin Name
Pin Function
A
0
-A
20
Address Inputs
WE
Write Enable Input
CE
Chip Enable Input
ZZ
Deep Sleep Input
OE
Output Enable Input
LB
Lower Byte Enable Input
UB
Upper Byte Enable Input
I/O
0
-I/O
15
Data Inputs/Outputs
V
CC
Power
V
SS
Ground
V
CCQ
Power I/O only
V
SSQ
Ground I/O only
Stock No. 23279 - Rev A 6/03
2
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N32T1618C1B
Advance Information
Figure 2: Functional Block Diagram
Table 3: Functional Description
CE
WE
OE
UB/LB
ZZ
I/O
1
1. When UB and LB are in select mode (low), I/O
0
- I/O
15
are affected as shown. When LB only is in the select mode only
I/O
0
- IO
7
are affected as shown. When UB is in the select mode only I/O
8
- I/O
15
are affected as shown.
MODE
POWER
H
X
X
X
H
High Z
Standby
2
2. When the device is in standby mode, control inputs (WE, OE), address inputs and data input/outputs are internally iso-
lated from any external influence and disabled from exerting any influence externally.
Standby
X
X
X
H
H
High Z
Active
Active
L
L
X
3
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
L
1
H
Data In
Write
Active -> Standby
4
4. The device will consume active power in this mode whenever addresses are changed. Data inputs are internally isolated
from any external influence.
L
H
L
L
1
H
Data Out
Read
Active -> Standby
4
L
H
H
L
H
High Z
Active
Standby
4
L
L
X
X
L
High-Z
Set register
Active
H
X
X
X
L
High-Z
Deep Sleep
Deep Sleep
Table 4: Capacitance
1
1. These parameters are verified in device characterization and are not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input Capacitance
C
IN
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
6
pF
I/O Capacitance
C
I/O
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
6
pF
Control
Logic
Decode
Logic
Address
Inputs
A
4
- A
20
CE
WE
OE
Input/
Output
Mux
and
Buffers
I/O
0
- I/O
7
UB
LB
I/O
8
- I/O
15
Address
2048K x 16
Memory
Array
ZZ
Page
Decode
Logic
Address
Word
Address
Inputs
A
0
- A
3
Stock No. 23279 - Rev A 6/03
3
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N32T1618C1B
Advance Information
Table 5: Absolute Maximum Ratings
1
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Symbol
Rating
Unit
Voltage on any pin relative to V
SS
V
IN,OUT
0.5 to 2.45
V
Voltage on V
CC
Supply Relative to V
SS
V
CC
0.2 to 2.45
V
Voltage on V
CCQ
Supply Relative to V
SS
V
CCQ
0.2 to 4.0
V
Power Dissipation
P
D
500
mW
Storage Temperature
T
STG
55 to 150
o
C
Operating Temperature
T
A
-25 to +85
o
C
Soldering Temperature and Time
T
SOLDER
240
o
C, 10sec(Lead only)
o
C
Table 6: Operating Characteristics (Over Specified Temperature Range)
Item
Symbol
Comments
Min.
Typ
1
1. Typical values are measured at Vcc=Vcc Typ., T
A
=25C and not 100% tested.
Max.
Unit
Supply Voltage
V
CC
1.70
1.8
1.95
V
Supply Voltage for I/O
V
CCQ
V
CCQ
= 1.8V
1.70
2.25
V
V
CCQ
= 2.5V
2.3
2.7
V
CCQ
= 3.0V
2.7
3.3
Input High Voltage
V
IH
1.4
Vcc+0.2
V
Input Low Voltage
V
IL
0.2
0.4
V
Output High Voltage
V
OH
I
OH
= -0.2mA
0.8V
CCQ
V
Output Low Voltage
V
OL
I
OL
= 0.2mA
0.2V
CCQ
V
Input Leakage Current
I
LI
V
IN
= 0 to V
CC
0.5
A
Output Leakage Current
I
LO
OE = V
IH
or Chip Disabled
0.5
A
Read/Write Operating Supply Current
@ 1
s Cycle Time
2
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive
output capacitance expected in the actual system.
I
CC1
V
CC
=V
CC
MAX, V
IN
=V
IH
/ V
IL
Chip Enabled, I
OUT
= 0
4
mA
Read/Write Operating Supply Current
@ 70 ns Cycle Time
2
I
CC2
V
CC
=V
CC
MAX, V
IN
=V
IH
/ V
IL
Chip Enabled, I
OUT
= 0
20
mA
Standby Current
3
V
IN
= V
CC
or 0V
Chip Disabled
V
CC
= V
CC
MAX
3. This device assumes a standby mode if the chip is disabled (CE high). In order to achieve low standby current all inputs must be
within 0.2 volts of either VCC or VSS.
I
SB
V
IN
= V
CC
or 0V
Chip Disabled
V
CC
= V
CC
MAX, t
A
= 85
o
C
70
A
Stock No. 23279 - Rev A 6/03
4
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N32T1618C1B
Advance Information
Figure 3: Output Load Circuit
Table 7: Timing Test Conditions
Item
Input Pulse Level
0.1V
CC
to 0.9 V
CC
Input Rise and Fall Time
5ns
Input Timing Reference Levels
0.5 V
CC
Output Timing Reference Levels
0.5 V
CCQ
Operating Temperature
-25
o
C to +85
o
C
V
CCQ
30 pF
I/O
14.5K
14.5K
Output Load
Stock No. 23279 - Rev A 6/03
5
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N32T1618C1B
Advance Information
Table 8: Timings
Item
Symbol
-60
-70
Unit
Min
Max
Min
Max
Read
Cycle
Read Cycle Time
t
RC
60
70
ns
Chip Enable Active Time
1
t
CE
10000
10000
ns
Page Mode Cycle Time
t
PC
15
17.5
ns
Address Access Time
t
AA
60
70
ns
Page Mode Access Time
t
PA
15
17.5
ns
Chip Enable to Valid Output
t
CO
60
70
ns
Output Enable to Valid Output
t
OE
20
20
ns
Byte Select to Valid Output
t
BO
60
70
ns
Address Valid to End of Chip Enable
t
AC
55
65
ns
Chip Enable to Low-Z output
t
LZ
10
10
ns
Output Enable to Low-Z Output
t
OLZ
5
5
ns
Byte Select to Low-Z Output
t
BLZ
10
10
ns
Chip Disable to High-Z Output
t
HZ
0
8
0
8
ns
Output Disable to High-Z Output
t
OHZ
0
8
0
8
ns
Byte Select Disable to High-Z Output
t
BHZ
0
8
0
8
ns
Output Hold from Address Change
t
OH
5
8
ns
Write
Cycle
Write Cycle Time
t
WC
60
70
ns
Chip Enable Active Time
t
CE
10000
10000
ns
Chip Enable to End of Write
t
CW
60
70
ns
Address Valid to End of Write
t
AW
60
70
ns
Byte Select to End of Write
t
BW
60
70
ns
Write Pulse Width
t
WP
40
46
ns
Write Recovery Time
t
WR
0
0
ns
Write to High-Z Output
t
WHZ
0
8
0
8
ns
Address Setup Time
t
AS
0
0
ns
Data to Write Time Overlap
t
DW
20
23
ns
Data Hold from Write Time
t
DH
0
0
ns
End Write to Low-Z Output
t
OW
5
5
ns
1. Maximum Chip Enable Active Time is defined for Page Mode only.