1
Stock No. 23251-C 7/03
N32T1618CBB
Advance Information
NanoAmp Solutions, Inc.
1982 Zanker Road, San Jose, CA 95112
ph: 408-573-8878, FAX: 408-573-8877
www.nanoamp.com
This is an ADVANCE DATASHEET and subject to change without notice.
32Mb Ultra-Low Power Async, Page and Burst CMOS PSRAM
Overview
The N32T1618CBB is an integrated memory
device containing a 32 Mbit Pseudo Static Random
Access Memory using a self-refresh DRAM array
organized as 2,097,152 words by 16 bits. It is
designed to be compatible in operation and inter-
face to standard 6T SRAMS. The device is
designed for low standby and operating current
and includes a power-down feature to automati-
cally enter standby mode. The device includes a
deep power-down mode as well as several other
power saving modes: Partial Array Self Refresh
mode where data is retained in a portion of the
array and Temperature Compensated Refresh.
Both these modes reduce standby current drain.
The device can be operated in a standard asyn-
chronous mode, a 16-word page mode and a high-
performance burst mode. The device has separate
power rails, VccQ and VssQ for the I/O to be run
from a separate power supply from the device
core.
.
Ball Configuration 54-Ball BGA
Features
Single Device Supports Asynchronous, Page
and Burst Operations
Dual voltage rails for optimal performance
VCC 1.70V1.95V
VCCQ 1.70V2.25V
VCCQ 2.3V2.7V (future)
VCCQ 2.7V3.3V future)
Burst Mode Continuous Write Burst
Burst Mode Read Access: 4, 8, 16 or Continuous
MAX clock rate: 104 MHz (
t
CLK = 9.62ns)
Initial latency: 39ns (4 clocks) @ 104 MHz
t
ACLK: 6.5ns @ 104 MHz
Sixteen-word page size
Interpage read access: 70ns
Intrapage read access: 20ns
Low Power Consumption
Asynchronous Read < 25mA
Intrapage Read < 15mA
Burst Read < 35mA
Continuous Burst Read < 15mA
Standby: 90A
Deep power-down < 10A (MAX)
Low Power Features
Partial Array Self Refresh (PASR)
Temperature Compensated Refresh (TCR)
Deep Power-Down mode (DPD)
High Performance access of 70ns and 85ns
High frequency operation of 104M and 66MHz
Temperature Range of -25C to +85C
54-Ball VFBGA
For 2.5V and 3.0V VccQ options, please contact factory.
B
LB#
A5
OE#
A3
A17
A21
A14
A12
1
2
3
4
5
6
A
C
D
E
F
G
H
A4
CE#
A6
A7
A16
A15
A13
A10
A18
A8
WAIT
A9
DQ5
WE#
A11
DQ4
VSS
DQ7
A20
DQ1
DQ3
VCC
DQ2
DQ6
J
DQ10
UB#
DQ11
DQ12
DQ13
A19
DQ9
DQ8
VSSQ
VCCQ
DQ14
DQ15
NC
CLK
ADV#
NC
NC
DQ0
A0
A1
A2
CRE
Top View
(Bump Down)
Options
Part Number
Package
Type
Operating
Temperature
Power
Supply
I/O Supply
Speed
Standby
Current (I
SB
),
Max
Operating
Current (Icc),
Max
N32T1618CBBZ
BGA
-25
o
C to +85
o
C 1.70V - 1.95
1.70V - 1.95
70/85ns
90
A
3 mA @ 1MHz
N32T1628CBBZ
2.3V - 2.7V
N32T1638CBBZ
2.7V - 3.3V
NanoAmp Solutions, Inc.
2
Stock No. 23251-C 7/03
This is an ADVANCE DATASHEET and subject to change without notice.
N32T1618CBB
Advance Information
General Description
The N32T1618CBB is a 32Mb device organized as
2M x 16 bits. These devices include the industry
standard burst mode Flash interface that dramati-
cally increases read/write bandwidth when com-
pared with other low-power SRAM or Pseudo-
SRAM offerings. To operate seamlessly on a burst
Flash bus, a transparent self-refresh mechanism is
incorporated. The hidden refresh requires no addi-
tional support from the system memory controller
and has no significant impact on device read/write
performance. Two user-accessible control registers
define device operation. The Bus Configuration
Register (BCR) defines how the device interacts
with the system memory bus and is nearly identical
to its counterpart found on burst-mode Flash
devices. The Refresh Configuration Register
(RCR) is used to control how refresh is performed
on the DRAM array. These registers are automati-
cally loaded with default settings during power-up
and can be updated any time during normal opera-
tion. Special attention has been focused on
standby current consumption during self-refresh.
The N32T1618CBB device includes three system-
accessible mechanisms used to minimize standby
current. Partial Array Self Refresh (PASR) limits
refresh to only that part of the DRAM array that
contains essential data. Temperature Compen-
sated Refresh (TCR) is used to adjust the refresh
rate according to the ambient temperature. The
refresh rate can be decreased at lower tempera-
tures to minimize current consumption during
standby. Deep Power Down (DPD) halts the
refresh operation altogether and is used when no
vital information is stored in the device. These
three refresh mechanisms are adjusted through the
Refresh Configuration Register.
A[20-0]
2,048Kx 16
DRAM
MEMORY
ARRAY
Input/
Output
Mux
and
Buffers
Address Decode
Logic
Control
Logic
CE#
WE#
OE#
CLK
ADV#
CRE
WAIT
LB#
UB#
DQ0 - DQ7
DQ8 - DQ15
Refresh Configuration
Register
Bus Configuration
Register
Functional Block Diagram
NanoAmp Solutions, Inc.
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Stock No. 23251-C 7/03
This is an ADVANCE DATASHEET and subject to change without notice.
N32T1618CBB
Advance Information
NOTE: The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode. The WAIT sig-
nal will be driven to an undefined state when operating in asynchronous or page mode. Otherwise, WAIT will be in High-Z condi-
tion.
Table 1: Pad Description
SYMBOL
TYPE
DESCRIPTION
A0-A20
Input
Address Inputs: Inputs for addresses during READ and WRITE operations.
Addresses are internally latched during READ and WRITE cycles. The address
lines are also used to define the value to be loaded into the Bus Configuration
Register or the Refresh Configuration Register.
CLK
Input
Clock: Synchronizes the memory to the system operating frequency during
synchronous operations. When configured for synchronous operation, the
address is latched on the first rising (or falling, depending upon the Bus Config-
uration Register setting) CLK edge when ADV# is active, or upon a rising ADV#
edge, whichever occurs first. CLK is static during asynchronous access READ
and WRITE operations and during PAGE READ ACCESS operations. CLK
must be held LOW during asynchronous or page mode transactions.
ADV#
Input
Address Valid: Indicates that a valid address is present on the address inputs.
Addresses can be latched on the rising edge of ADV# during READ and
WRITE operations. ADV# may be driven LOW during asynchronous READ and
WRITE operations.
CRE
Input
Control Register Enable: When CRE is HIGH, write operations load the
Refresh Control Register or Bus Control Register.
CE#
Input
Chip Enable: Activates the device when LOW. When CE# is HIGH, the device
is disabled and goes into standby power mode.
OE#
Input
Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the
output buffers are disabled.
WE#
Input
Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the
cycle is a WRITE to either a control register or to the memory array.
UB#
Input
Upper Byte Enable. DQ <8:15>
LB#
Input
Lower Byte Enable. DQ <0:7>
DQ0-
DQ15
Input/Out-
put
Data Inputs/Outputs
WAIT
Output
Wait: Provides data-valid feedback during burst READ and WRITE operations.
The signal is gated by CE#. WAIT is used to arbitrate collisions between
refresh and READ/WRITE operations. WAIT is asserted when a burst crosses
a row boundary. WAIT is also used to mask the delay associated with opening
a new internal page. WAIT is asserted and should be ignored during asynchro-
nous and page mode operations.
NC
Internally not connected
Vcc
Supply
Device Power Supply: [1.70V-1.95V] Power supply for device core operation.
VccQ
Supply
I/O Power Supply: [1.8V, 2.5V, 3.0V]Power supply for input/output buffers.
Vss
Supply
All Vss supply pins must be connected to ground.
VssQ
Supply
All VssQ supply pins must be connected to ground.
NanoAmp Solutions, Inc.
4
Stock No. 23251-C 7/03
This is an ADVANCE DATASHEET and subject to change without notice.
N32T1618CBB
Advance Information
NOTE:
1. When UB# and LB# are in select mode (LOW), DQ0-DQ15 are affected as shown. When only LB# is in select mode, DQ0-DQ7 are
affected as shown. When only UB# is in the select mode, DQ8-DQ15 are affected as shown.
2. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence.
3. Burst Mode operation is initialized through the Bus Configuration Register (BCR[15]).
4. The device will consume active power in this mode whenever addresses are changed.
5. The WAIT polarity is configured through the Bus Configuration Register (BCR[10]).
6. V
IN
= V
CC
or 0V, all device pins must be static (unswitched) in order to achieve standby current.
7. The clock polarity is configured through the Bus Configuration Register (BCR[6]).
8. P refers to a clock pulse.
TABLE 2: Functional Description
Asynchronous Mode
MODE
POWER
CLK
ADV#
CE#
OE#
WE#
CRE
UB#/
LB#
WAIT
5
DQ0-DQ15
1
NOTES
Read
Active > Standby
L
L
L
L
H
L
L
1
L
Data-Out
4
Write
Active > Standby
L
L
L
X
L
L
L
1
L
Data-In
4
Standby
Standby
X
X
H
X
X
L
X
X
High-Z
2
Standby
Standby
X
X
L
X
X
L
X
X
X
4, 6
Mode Register Active
L
L
L
H
L
H
X
L
High-Z
DPD
Deep Power
Down
L
X
H
X
X
H
X
X
High-Z
Burst Mode
MODE
POWER
CLK
8
ADV#
CE#
OE#
WE#
CRE
UB#/
LB#
WAIT
5
DQ0-DQ15
1
NOTES
Async. Read
Active > Standby
L
L
L
L
H
L
L
L
Data-Out
1,4
Async. Write
Active > Standby
L
L
L
X
L
L
L
L
Data-In
1,4
Standby
Standby
X
X
H
X
X
L
X
X
High-Z
2
Standby
Standby
X
X
L
X
X
L
X
X
X
4,6
Initial Burst
Read
Active > Standby
P
L
L
L
H
L
L
L
Data-Out 1,3,4,7
Initial Burst
Write
Active > Standby
P
L
L
H
L
L
X
L
Data-In
3,4,7
Burst Continue Active > Standby
P
H
L
X
X
L
X
X
Data-In or
Data-Out
3,4,7
Burst Suspend Active > Standby
L
X
L
X
X
L
X
X
High-Z
3,4
Mode Register
Active
P
L
L
H
L
H
X
X
High-Z
3,7
DPD
Deep Power
Down
L
X
H
X
X
H
X
X
High-Z
NanoAmp Solutions, Inc.
5
Stock No. 23251-C 7/03
This is an ADVANCE DATASHEET and subject to change without notice.
N32T1618CBB
Advance Information
FUNCTIONAL DESCRIPTION
In general, the N32T1618CBB device can be con-
sidered a high-density alternative to SRAM prod-
ucts popular in low-power portable applications.
The N32T1618CBB contains 33,554,432 bits orga-
nized as 2,097,152 addresses x 16 bits. The
device implements the same high-speed bus inter-
face found on burst-mode Flash products.
The bus interface supports both asynchronous and
burst-mode transfers. Page-mode accesses are
also included as a bandwidth-enhancing extension
to the asynchronous read protocol.
POWER-UP INITIALIZATION
The N32T1618CBB includes an on-chip voltage
sensor used to launch the power-up initialization
process. Initialization will configure the Bus Config-
uration Register (BCR) and the Refresh Configura-
tion Register (RCR) with their default settings (See
Tables 3 and 6). V
CC
and V
CC
Q must be applied
simultaneously. Once they reach a stable level
above 1.70V, the device will require 150s to com-
plete its self-initialization process. During the initial-
ization period the CE# pin should remain HIGH.
Once initialization has completed, the device is
ready for normal operation.
Figure 2: Power-Up Initialization Timing
BUS OPERATING MODES
The N32T1618CBB product incorporates the burst
mode interface found on Flash products targeting
low-power wireless applications. This bus interface
supports asynchronous, page-mode and burst-
mode READ and WRITE transfers. The specific
interface supported is defined by the value loaded
into the Bus Configuration Register. Page Mode is
controlled by the Refresh Configuration Register
(RCR[7]).
Asynchronous Mode
The N32T1618CBB device default power-up state
is in the asynchronous operating mode. This mode
uses the industry standard SRAM control bus
(CE#, OE#, WE#, LB#/UB#). READ operations
(Figure 3) are initiated by bringing CE#, OE# and
LB#/UB# LOW while keeping WE# HIGH. Valid
data will be driven out of the I/O pins after the spec-
ified access time has elapsed. WRITE operations
(Figure 4) occur when CE#, WE# and LB#/UB# are
driven LOW. During asynchronous write operations
the OE# level is a "don't care," and WE# will over-
ride OE#. The data to be written will be latched on
the rising edge of CE#, WE# or LB#/UB# (which-
ever occurs first). Asynchronous operations (page-
mode disabled) can either use the ADV input to
latch the address, or ADV can be driven LOW dur-
ing the entire READ/WRITE operation.
During asynchronous operation the CLK input
should be held LOW. The WAIT pin will be driven
while the device is enabled and its state should be
ignored.
VCC
VccQ
Vcc=1.70V
Device Initialization
tPU>150s
Device ready for
normal operation
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