N64T1618C1A.fm
NanoAmp Solutions, Inc.
1982 Zanker Road, San Jose, CA 95112
ph: 408-573-8878, FAX: 408-573-8877
www.nanoamp.com
N64T1618C1A
Stock No. 23192 - Rev A 10/02
1
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
Advance Information
64Mb Ultra-Low Power Asynchronous CMOS PSRAM
4M x 16 bit
Overview
The N64T1618C1A is an integrated memory
device containing a 64 Mbit Pseudo Static Random
Access Memory using a self-refresh DRAM array
organized as 4,194,304 words by 16 bits. It is
designed to be compatible in operation and
interface to standard 6T SRAMS. The device is
designed for low standby and operating current
and includes a power-down feature to
automatically enter standby mode. The device
includes a ZZ input for deep sleep as well as
several other power saving modes: partial array
refresh mode where data is retained in a portion of
the array and temperature compensated refresh.
Both these modes reduce standby current drain.
The N64T1618C1A can be operated in a standard
asynchronous mode and data can also be read in a
4-word page mode for fast access times. The
VFBGA package has separate power rails, VccQ
and VssQ for the I/O to be run from a separate
power supply from the device core.
Features
Dual voltage rails for optimum power & per-
formance
Vcc 1.70V to 1.95V
VccQ 1.70V1.95V
VccQ 2.3V2.7V
VccQ 2.7V3.3V
Fast Cycle Times
T
ACC
< 60 nS
T
PACC
< 15 nS
Very low standby current
I
SB
< 80A
Very low operating current
Icc < 25mA
PASR (Partial Array Self Refresh)
TCR (Temperature Compensated Refresh)
48-Pin VFBGA, Wafers Available
Figure 1: Pin Configuration
Table 1: Product Family
Part Number
Package
Type
Operating
Temperature
Power
Supply
Speed
Standby
Current (I
SB
),
Max
Operating
Current (Icc),
Max
N64T1618C1AZ
48 - BGA
-25
o
C to +85
o
C
1.70V - 1.95
60/70 ns
80
A
3 mA @ 1MHz
1
2
3
4
5
6
A
LB
OE
A
0
A
1
A
2
ZZ
B
I/O
8
UB
A
3
A
4
CE
I/O
0
C
I/O
9
I/O
10
A
5
A
6
I/O
1
I/O
2
D
V
SSQ
I/O
11
A
17
A
7
I/O
3
V
CC
E
V
CCQ
I/O
12
A
21
A
16
I/O
4
V
SS
F
I/O
14
I/O
13
A
14
A
15
I/O
5
I/O
6
G
I/O
15
A
19
A
12
A
13
WE
I/O
7
H
A
18
A
8
A
9
A
10
A
11
A
20
48 Pin BGA (top)
6 x 8 mm
Table 2: Pin Descriptions
Pin Name
Pin Function
A
0
-A
21
Address Inputs
WE
Write Enable Input
CE
Chip Enable Input
ZZ
Deep Sleep Input
OE
Output Enable Input
LB
Lower Byte Enable Input
UB
Upper Byte Enable Input
I/O
0
-I/O
15
Data Inputs/Outputs
V
CC
Power
V
SS
Ground
V
CCQ
Power I/O only
V
SSQ
Ground I/O only
Stock No. 23192 - Rev A 10/02
2
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N64T1618C1A
Advance Information
Figure 2: Functional Block Diagram
Table 3: Functional Description
CE
WE
OE
UB/LB
ZZ
I/O
1
1. When UB and LB are in select mode (low), I/O
0
- I/O
15
are affected as shown. When LB only is in the select mode only
I/O
0
- IO
7
are affected as shown. When UB is in the select mode only I/O
8
- I/O
15
are affected as shown.
MODE
POWER
H
X
X
X
H
High Z
Standby
2
2. When the device is in standby mode, control inputs (WE, OE), address inputs and data input/outputs are internally iso-
lated from any external influence and disabled from exerting any influence externally.
Standby
X
X
X
H
H
High Z
Active
Active
L
L
X
3
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
L
1
H
Data In
Write
Active -> Standby
4
4. The device will consume active power in this mode whenever addresses are changed. Data inputs are internally isolated
from any external influence.
L
H
L
L
1
H
Data Out
Read
Active -> Standby
4
L
H
H
L
H
High Z
Active
Standby
4
L
L
X
X
L
High-Z
Set register
Active
H
X
X
X
L
High-Z
Deep Sleep
Deep Sleep
Table 4: Capacitance
1
1. These parameters are verified in device characterization and are not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input Capacitance
C
IN
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
6
pF
I/O Capacitance
C
I/O
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
6
pF
Control
Logic
Decode
Logic
Address
Inputs
A
4
- A
21
CE
WE
OE
Input/
Output
Mux
and
Buffers
I/O
0
- I/O
7
UB
LB
I/O
8
- I/O
15
Address
4096K x 16
Memory
Array
ZZ
Page
Decode
Logic
Address
Word
Address
Inputs
A
0
- A
3
Stock No. 23192 - Rev A 10/02
3
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N64T1618C1A
Advance Information
Table 5: Absolute Maximum Ratings
1
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Symbol
Rating
Unit
Voltage on any pin relative to V
SS
V
IN,OUT
0.5 to 2.45
V
Voltage on V
CC
Supply Relative to V
SS
V
CC
0.2 to 2.45
V
Voltage on V
CCQ
Supply Relative to V
SS
V
CCQ
0.2 to 4.0
V
Power Dissipation
P
D
500
mW
Storage Temperature
T
STG
55 to 150
o
C
Operating Temperature
T
A
-25 to +85
o
C
Soldering Temperature and Time
T
SOLDER
240
o
C, 10sec(Lead only)
o
C
Table 6: Operating Characteristics (Over Specified Temperature Range)
Item
Symbol
Comments
Min.
Typ
1
1. Typical values are measured at Vcc=Vcc Typ., T
A
=25C and not 100% tested.
Max.
Unit
Supply Voltage
V
CC
1.70
1.8
1.95
V
Supply Voltage for I/O
V
CCQ
V
CCQ
= 1.8V
1.70
2.25
V
V
CCQ
= 2.5V
2.3
2.7
V
CCQ
= 3.0V
2.7
3.3
Input High Voltage
V
IH
1.4
Vcc+0.2
V
Input Low Voltage
V
IL
0.2
0.4
V
Output High Voltage
V
OH
I
OH
= -0.2mA
0.8V
CCQ
V
Output Low Voltage
V
OL
I
OL
= 0.2mA
0.2V
CCQ
V
Input Leakage Current
I
LI
V
IN
= 0 to V
CC
0.5
A
Output Leakage Current
I
LO
OE = V
IH
or Chip Disabled
0.5
A
Read/Write Operating Supply Current
@ 1
s Cycle Time
2
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive
output capacitance expected in the actual system.
I
CC1
V
CC
=V
CC
MAX, V
IN
=V
IH
/ V
IL
Chip Enabled, I
OUT
= 0
4
mA
Read/Write Operating Supply Current
@ 70 ns Cycle Time
2
I
CC2
V
CC
=V
CC
MAX, V
IN
=V
IH
/ V
IL
Chip Enabled, I
OUT
= 0
20
mA
Standby Current
3
V
IN
= V
CC
or 0V
Chip Disabled
V
CC
= V
CC
MAX
3. This device assumes a standby mode if the chip is disabled (CE high). In order to achieve low standby current all inputs must be
within 0.2 volts of either VCC or VSS.
I
SB
V
IN
= V
CC
or 0V
Chip Disabled
V
CC
= V
CC
MAX, t
A
= 85
o
C
80
A
Stock No. 23192 - Rev A 10/02
4
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N64T1618C1A
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Figure 3: Output Load Circuit
Table 7: Timing Test Conditions
Item
Input Pulse Level
0.1V
CC
to 0.9 V
CC
Input Rise and Fall Time
5ns
Input Timing Reference Levels
0.5 V
CC
Output Timing Reference Levels
0.5 V
CCQ
Operating Temperature
-25
o
C to +85
o
C
V
CCQ
30 pF
I/O
14.5K
14.5K
Output Load
Stock No. 23192 - Rev A 10/02
5
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N64T1618C1A
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Table 8: Timings
Item
Symbol
-60
-70
Unit
Min
Max
Min
Max
Read
Cycle
Read Cycle Time
t
RC
60
70
ns
Chip Enable Active Time
1
t
CE
10000
10000
ns
Page Mode Cycle Time
t
PC
15
17.5
ns
Address Access Time
t
AA
60
70
ns
Page Mode Access Time
t
PA
15
17.5
ns
Chip Enable to Valid Output
t
CO
60
70
ns
Output Enable to Valid Output
t
OE
20
20
ns
Byte Select to Valid Output
t
BO
60
70
ns
Address Valid to End of Chip Enable
t
AC
55
65
ns
Chip Enable to Low-Z output
t
LZ
10
10
ns
Output Enable to Low-Z Output
t
OLZ
5
5
ns
Byte Select to Low-Z Output
t
BLZ
10
10
ns
Chip Disable to High-Z Output
t
HZ
0
8
0
8
ns
Output Disable to High-Z Output
t
OHZ
0
8
0
8
ns
Byte Select Disable to High-Z Output
t
BHZ
0
8
0
8
ns
Output Hold from Address Change
t
OH
5
8
ns
Write
Cycle
Write Cycle Time
t
WC
60
70
ns
Chip Enable Active Time
t
CE
10000
10000
ns
Chip Enable to End of Write
t
CW
60
70
ns
Address Valid to End of Write
t
AW
60
70
ns
Byte Select to End of Write
t
BW
60
70
ns
Write Pulse Width
t
WP
40
46
ns
Write Recovery Time
t
WR
0
0
ns
Write to High-Z Output
t
WHZ
0
8
0
8
ns
Address Setup Time
t
AS
0
0
ns
Data to Write Time Overlap
t
DW
20
23
ns
Data Hold from Write Time
t
DH
0
0
ns
End Write to Low-Z Output
t
OW
5
5
ns
1. Maximum Chip Enable Active Time is defined for Page Mode only.
Stock No. 23192 - Rev A 10/02
6
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N64T1618C1A
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Figure 4: Timing of Read Cycle (CE = OE = V
IL
, WE = V
IH
)
Figure 5: Timing Waveform of Read Cycle (WE=V
IH
)
Address
Data Out
t
RC
t
AA
t
OH
Data Valid
Previous Data Valid
Address
LB, UB
OE
Data Valid
t
RC
t
AA
t
CO
t
HZ
t
OHZ
t
BHZ
t
OLZ
t
OE
t
LZ
High-Z
Data Out
t
BO
t
BLZ
CE
t
AC
Stock No. 23192 - Rev A 10/02
7
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N64T1618C1A
Advance Information
Figure 6: Timing Waveform of Page Mode Read Cycle (WE=V
IH
)
Address
LB, UB
OE
Data Valid
t
RC
t
AA
t
CO
t
HZ
t
OHZ
t
BHZ
t
OLZ
t
OE
t
LZ
High-Z
Data Out
t
BO
t
BLZ
CE
t
AC
Data Valid
Data Valid
Data Valid
t
PA
t
PA
t
PA
t
OH
t
PC
t
PC
Stock No. 23192 - Rev A 10/02
8
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N64T1618C1A
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Figure 7: Timing Waveform of Write Cycle (WE control)
Figure 8: Timing Waveform of Write Cycle (CE Control)
Address
Data In
CE
LB, UB
Data Valid
t
WC
t
AW
t
CW
t
WR
t
WHZ
t
DH
High-Z
WE
Data Out
High-Z
t
OW
t
AS
t
WP
t
DW
t
BW
Address
WE
Data Valid
t
WC
t
AW
t
CW
t
WR
t
DH
LB, UB
Data In
High-Z
t
AS
t
WP
t
DW
t
BW
Data Out
t
WHZ
CE
Stock No. 23192 - Rev A 10/02
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The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N64T1618C1A
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Figure 9: Timing Waveform of Write Cycle (UB, LB control)
Address
WE
Data Valid
t
WC
t
AW
t
CW
t
WR
t
DH
LB, UB
Data In
High-Z
t
AS
t
WP
t
DW
t
BW
Data Out
t
WHZ
CE
Stock No. 23192 - Rev A 10/02
10
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N64T1618C1A
Advance Information
Power Up Requirements
After power is applied to bring Vcc and VccQ up, CE should be brought high. Once CE is high, a 150us
delay is required to ensure proper operation. After a 150us delay, the device is now ready for operation or
programming of the mode register.
Timing Restrictions
With Page Mode Enabled
If Page Mode is enabled, a maximum Chip Enable Active Time (t
CE
) must be met as defined in the Timings
of Table 8.
With Page Mode Disabled
If Page Mode is disabled, either one of the following two timing requirements must be met.
1) Chip Enable Active Time must be limited to a maximum of 10us.
2) A maximum elapsed time between any addresses toggling must be limited to 10us or less.
Stock No. 23192 - Rev A 10/02
11
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N64T1618C1A
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Power Savings Modes
In the N64T1618C1A device there are several power savings modes. The three modes are:
Partial Array Refresh
Temperature Compensated Refresh
Deep Sleep Mode
The operation of the power saving modes is controlled by the settings of bits contained in the Mode Regis-
ter. This definition of the Mode Register is shown in Figure 10 and the various bits are used to enable and
disable the various low power modes as well as enabling Page Mode operation. The Mode Register is set
by using the timings defined in Figure 11. The register must be set in less then 1us after ZZ is enabled low.
1) Partial Array Refresh (PAR)
In this mode of operation, the internal refresh operation can be restricted to a 16Mb, 32Mb or 48Mb portion
of the array. The array partition to be refreshed is determined by the respective bit settings in the Mode
Register. The register settings for the PAR operation are defined in Table 10. In this PAR mode, when ZZ
is active low, only the portion of the array that is set in the register is refreshed. The data in the remainder
of the array will be lost. The PAR operating mode is only available during standby time (ZZ low) and once
ZZ is returned high, the device resumes full array refresh. All future PAR cycles will use the contents of the
Mode Register that has been previously set. To change the address space of the PAR mode, the Mode
Register must be reset using the previously defined procedures. For PAR to be activated, the register bit,
A4 must be set to a `1' value, "Deep Sleep Disabled". If this is the case, PAR will be activated 10us after
ZZ is brought low. If the A4 register bit is set equal to `0', PAR will not be activated.
2) Temperature Compensated Refresh (TCR)
In this mode of operation, the internal refresh rate can be optimized for the operating temperature used an
this can then lower standby current. The DRAM array in the PSRAM must be refreshed internally on a reg-
ular basis. At higher temperatures, the DRAM cell must be refreshed more often than at lower temper-
tures. By setting the temperature of operation in the Mode Register, this refresh rate can be optimized to
yield the lowest standby current at the given operating temperature. There are four different temperature
settings that can be programmed in to the PSRAM. These are defined in Figure 10.
3) Deep Sleep Mode
In this mode of operation, the internal refresh is turned off and all data integrity of the array is lost. Deep
Sleep is entered by bringing ZZ low with the A4 register bit set to a `0', "Deep Sleep Enabled". If this is the
case, Deep Sleep will be entered 10us after ZZ is brought low. The device will remain in this mode as long
as ZZ remains low. If the A4 register bit is set equal to `1', Deep Sleep will not be activated.
Other Mode Register Settings
The Page Mode operation can also be enabled and disabled using the Mode Register. Register bit A7
controls the operation of Page Mode and setting this bit to a `1', enables Page Mode. If the register bit A7
is set to a `0', Page Mode operation is disabled.
Stock No. 23192 - Rev A 10/02
12
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N64T1618C1A
Advance Information
Figure 10: Mode Register
Figure 11: Mode Register Update Timings (UB, LB, OE are Don't Care)
Deep Sleep Enable/Disable
0 = Deep Sleep Enabled
1 = Deep Sleep Disabled (default)
PAR Section
1 1 1 = Top 1/4 array
1 1 0 = Top 1/2 array
1 0 1 = Top 3/4 array
1 0 0 = No PAR
0 1 1 = Bottom 1/4 array
0 1 0 = Bottom 1/2 array
0 0 1 = Bottom 3/4 array
0 0 0 = Full array (default)
Reserved
Must set to all 0
A21 - A8
A7
A6
A5
A4
A3
A2
A1
A0
Page Mode
0 = Page Mode Disabled (default)
1 = Page Mode Enabled
Temp
Compensated
Refresh
1 0 = 15
o
C
0 1 = 45
o
C
0 0 = 70
o
C
1 1 = 85
o
C (default)
Reserved
Must set to `0'
Address
ZZ
t
WC
t
AS
CE
WE
t
ZZWE
t
AW
t
WP
t
WR
t
CDZZ
Stock No. 23192 - Rev A 10/02
13
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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N64T1618C1A
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Figure 12: Deep Sleep Mode - Entry/Exit Timings
Table 9: Mode Register Update and Deep Sleep Timings
Item
Symbol
Min
Max
Unit
Note
Chip deselect to ZZ low
t
CDZZ
5
ns
ZZ low to WE low
t
ZZWE
10
500
ns
Write register cycle time
t
WC
60/70
ns
1
Address valid to end of write
t
AW
60/70
ns
1
Write recovery time
t
WR
0
ns
Address setup time
t
AS
0
ns
Write pulse width
t
WR
40
ns
Deep Sleep Pulse Width
t
ZZMIN
10
us
Deep Sleep Recovery
t
R
150
us
1) Minimum cycle time for writing register is equal to speed grade of product.
Table 10: Address Patterns for PAR (A4 = 1)
A2
A1
A0
Active Section
Address space
Size
Density
1
1
1
Top quarter of die
300000h - 3FFFFFh 1Mb x 16
16Mb
1
1
0
Top half of die
200000h - 3FFFFFh 2Mb x 16
32Mb
1
0
1
Top three-quarters of die
100000h - 3FFFFFh 3Mb x 16
48Mb
1
0
0
No PAR
None
0
0
0
1
1
Bottom quarter of die
000000h - 0FFFFFh 1Mb x 16
16Mb
0
1
0
Bottom half of die
000000h - 1FFFFFh 2Mb x 16
32Mb
0
0
1
Bottom three-quarters of die 000000h - 2FFFFFh 3Mb x 16
48Mb
0
0
0
Full array
000000h - 3FFFFFh 4Mb x 16
64Mb
ZZ
t
ZZMIN
t
CDZZ
t
R
CE
Stock No. 23192 - Rev A 10/02
14
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
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Table 11: Deep ICC Characteristics for N64T1618C1A
Item
Symbol
Test
Array
Partition
Typ
Max Unit
PAR Mode Standby
Current
I
PAR
V
IN
= V
CC
or 0V,
Chip Disabled, t
A
= 85
o
C
None
50
uA
1/4 Array
57
1/2 Array
64
3/4 Array
72
Full Array
80
Item
Symbol
Test
Max
Temperature
Typ
Max Unit
Temperature Com-
pensated Refresh
Current
I
TCR
15
o
C
50
uA
45
o
C
60
70
o
C
70
85
o
C
80
Item
Symbol
Test
Typ
Max Unit
Deep Sleep Current
I
ZZ
V
IN
= V
CC
or 0V,
Chip in ZZ mode, t
A
= 85
o
C
10
uA
Stock No. 23192 - Rev A 10/02
15
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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N64T1618C1A
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Figure 13: Ball Grid Array Package
Table 12: Dimensions (mm)
D
E
e = 0.75
BALL
MATRIX
TYPE
SD
SE
J
K
60.10
80.10
0.375
0.375
1.125
1.375
FULL
SIDE VIEW
TOP VIEW
BOTTOM VIEW
E
D
A1 BALL PAD
CORNER (3)
0.900.10
0.230.05
0.15
0.08
Z
Z
1. 0.300.05 DIA.
1. DIMENSION IS MEASURED AT THE
MAXIMUM SOLDER BALL DIAMETER.
PARALLEL TO PRIMARY Z.
2. PRIMARY DATUM Z AND SEATING
PLANE ARE DEFINED BY THE
SPHERICAL CROWNS OF THE
SOLDER BALLS.
3. A1 BALL PAD CORNER I.D. TO BE
MARKED BY INK.
2. SEATING PLANE - Z
SD
SE
e
K TYP
J TYP
e
A1 BALL PAD
CORNER
Stock No. 23192 - Rev A 10/02
16
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N64T1618C1A
Advance Information
Figure 14: Ordering Information
2002 NanoAmp Solutions, Inc. All rights reserved.
NanoAmp Solutions, Inc. ("NanoAmp") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice.
NanoAmp does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration pur-
poses only and they vary depending upon specific applications.
NanoAmp makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does NanoAmp assume any liability arising out of the application
or use of any product or circuit described herein. NanoAmp does not authorize use of its products as critical components in any application in which the failure of the NanoAmp
product may be expected to result in significant injury or death, including life support systems and critical medical instrument.
Table 13: Revision History
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