N64T1618CBA_new.fm
1
Stock No. 23250-C 7/03
N64T1618CBA
Advance Information
NanoAmp Solutions, Inc.
1982 Zanker Road, San Jose, CA 95112
ph: 408-573-8878, FAX: 408-573-8877
www.nanoamp.com
This is an ADVANCE DATASHEET and subject to change without notice.
64Mb Ultra-Low Power Async, Page and Burst CMOS PSRAM
Overview
The N64T1618CBA is an integrated memory
device containing a 64 Mbit Pseudo Static Random
Access Memory using a self-refresh DRAM array
organized as 4,194,304 words by 16 bits. It is
designed to be compatible in operation and inter-
face to standard 6T SRAMS. The device is
designed for low standby and operating current
and includes a power-down feature to automati-
cally enter standby mode. The device includes a
deep power-down mode as well as several other
power saving modes: Partial Array Self Refresh
mode where data is retained in a portion of the
array and Temperature Compensated Refresh.
Both these modes reduce standby current drain.
The device can be operated in a standard asyn-
chronous mode, a 16-word page mode and a high-
performance burst mode. The die has separate
power rails, VccQ and VssQ for the I/O to be run
from a separate power supply from the device
core.
Ball Configuration 54-Ball BGA
Features
Single Device Supports Asynchronous, Page
and Burst Operations
Dual voltage rails for optimal performance
VCC 1.70V1.95V
VCCQ 1.70V2.25V
VCCQ 2.3V2.7V (future)
VCCQ 2.7V3.3V future)
Burst Mode Continuous Write Burst
Burst Mode Read Access: 4, 8, 16 or Continuous
MAX clock rate: 104 MHz (
t
CLK = 9.62ns)
Initial latency: 39ns (4 clocks) @ 104 MHz
t
ACLK: 6.5ns @ 104 MHz
Sixteen-word page size
Interpage read access: 70ns
Intrapage read access: 20ns
Low Power Consumption
Asynchronous Read < 25mA
Intrapage Read < 15mA
Burst Read < 35mA
Continuous Burst Read < 15mA
Standby: 100A
Deep power-down < 10A (MAX)
Low Power Features
Partial Array Self Refresh (PASR)
Temperature Compensated Refresh (TCR)
Deep Power-Down mode (DPD)
High Performance access of 70ns and 85ns
High frequency operation of 104M and 66MHz
Temperature Range of -25C to +85C
54-Ball VFBGA
For 2.5V and 3.0V VccQ options, please contact factory.
B
LB#
A5
OE#
A3
A17
A21
A14
A12
1
2
3
4
5
6
A
C
D
E
F
G
H
A4
CE#
A6
A7
A16
A15
A13
A10
A18
A8
WAIT
A9
DQ5
WE#
A11
DQ4
VSS
DQ7
A20
DQ1
DQ3
VCC
DQ2
DQ6
J
DQ10
UB#
DQ11
DQ12
DQ13
A19
DQ9
DQ8
VSSQ
VCCQ
DQ14
DQ15
NC
CLK
ADV#
NC
NC
DQ0
A0
A1
A2
CRE
Top View
(Bump Down)
Part Number
Package
Type
Operating
Temperature
Power
Supply
I/O Supply
Speed
Standby
Current (I
SB
),
Max
Operating
Current (Icc),
Max
N64T1618CBAZ
BGA
-25
o
C to +85
o
C 1.70V - 1.95
1.70V - 1.95
70/85ns
100
A
3 mA @ 1MHz
N64T1628CBAZ
2.3V - 2.7V
N64T1638CBAZ
2.7V - 3.3V
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N64T1618CBA
Advance Information
This is an ADVANCE DATASHEET and subject to change without notice.
Stock No. 23250-C 7/03
General Description
The N64T1618CBA is a 64Mb device organized as
4M x 16 bits. These devices include the industry
standard burst mode Flash interface that dramati-
cally increases read/write bandwidth when com-
pared with other low-power SRAM or Pseudo-
SRAM offerings. To operate seamlessly on a burst
Flash bus, a transparent self-refresh mechanism is
incorporated. The hidden refresh requires no addi-
tional support from the system memory controller
and has no significant impact on device read/write
performance. Two user-accessible control registers
define device operation. The Bus Configuration
Register (BCR) defines how the device interacts
with the system memory bus and is nearly identical
to its counterpart found on burst-mode Flash
devices. The Refresh Configuration Register
(RCR) is used to control how refresh is performed
on the DRAM array. These registers are automati-
cally loaded with default settings during power-up
and can be updated any time during normal opera-
tion. Special attention has been focused on
standby current consumption during self-refresh.
The N64T1618CBA device includes three system-
accessible mechanisms used to minimize standby
current. Partial Array Self Refresh (PASR) limits
refresh to only that part of the DRAM array that
contains essential data. Temperature Compen-
sated Refresh (TCR) is used to adjust the refresh
rate according to the ambient temperature. The
refresh rate can be decreased at lower tempera-
tures to minimize current consumption during
standby. Deep Power Down (DPD) halts the
refresh operation altogether and is used when no
vital information is stored in the device. These
three refresh mechanisms are adjusted through the
Refresh Configuration Register.
Functional Block Diagram
A[21-0]
4,096Kx 16
DRAM
MEMORY
ARRAY
Input/
Output
Mux
and
Buffers
Address Decode
Logic
Control
Logic
CE#
WE#
OE#
CLK
ADV#
CRE
WAIT
LB#
UB#
DQ0 - DQ7
DQ8 - DQ15
Refresh Configuration
Register
Bus Configuration
Register
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N64T1618CBA
Advance Information
This is an ADVANCE DATASHEET and subject to change without notice.
Stock No. 23250-C 7/03
NOTE: The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode. The WAIT sig-
nal will be driven to an undefined state when operating in asynchronous or page mode. Otherwise, WAIT will be in High-Z condi-
tion.
TABLE 1: Pad Description
SYMBOL
TYPE
DESCRIPTION
A0-A21
Input
Address Inputs: Inputs for addresses during READ and WRITE operations.
Addresses are internally latched during READ and WRITE cycles. The address
lines are also used to define the value to be loaded into the Bus Configuration
Register or the Refresh Configuration Register.
CLK
Input
Clock: Synchronizes the memory to the system operating frequency during
synchronous operations. When configured for synchronous operation, the
address is latched on the first rising (or falling, depending upon the Bus Config-
uration Register setting) CLK edge when ADV# is active, or upon a rising ADV#
edge, whichever occurs first. CLK is static during asynchronous access READ
and WRITE operations and during PAGE READ ACCESS operations. CLK
must be held LOW during asynchronous or page mode transactions.
ADV#
Input
Address Valid: Indicates that a valid address is present on the address inputs.
Addresses can be latched on the rising edge of ADV# during READ and
WRITE operations. ADV# may be driven LOW during asynchronous READ and
WRITE operations.
CRE
Input
Control Register Enable: When CRE is HIGH, write operations load the
Refresh Control Register or Bus Control Register.
CE#
Input
Chip Enable: Activates the device when LOW. When CE# is HIGH, the device
is disabled and goes into standby power mode.
OE#
Input
Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the
output buffers are disabled.
WE#
Input
Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the
cycle is a WRITE to either a control register or to the memory array.
UB#
Input
Upper Byte Enable. DQ <8:15>
LB#
Input
Lower Byte Enable. DQ <0:7>
DQ0-
DQ15
Input/Out-
put
Data Inputs/Outputs
WAIT
Output
Wait: Provides data-valid feedback during burst READ and WRITE operations.
The signal is gated by CE#. WAIT is used to arbitrate collisions between
refresh and READ/WRITE operations. WAIT is asserted when a burst crosses
a row boundary. WAIT is also used to mask the delay associated with opening
a new internal page. WAIT is asserted and should be ignored during asynchro-
nous and page mode operations.
NC
Internally not connected
Vcc
Supply
Device Power Supply: [1.70V-1.95V] Power supply for device core operation.
VccQ
Supply
I/O Power Supply: [1.8V, 2.5V, 3.0V]Power supply for input/output buffers.
Vss
Supply
All Vss supply pins must be connected to ground.
VssQ
Supply
All VssQ supply pins must be connected to ground.
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N64T1618CBA
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Stock No. 23250-C 7/03
NOTE: P symbolizes clock pulse
1. When UB# and LB# are in select mode (LOW), DQ0-DQ15 are affected as shown. When only LB# is in select mode, DQ0-DQ7 are
affected as shown. When only UB# is in the select mode, DQ8-DQ15 are affected as shown.
2. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence.
3. Burst Mode operation is initialized through the Bus Configuration Register (BCR[15]).
4. The device will consume active power in this mode whenever addresses are changed.
5. The WAIT polarity is configured through the Bus Configuration Register (BCR[10]).
6. V
IN
= V
CC
or 0V, all device pins must be static (unswitched) in order to achieve standby current.
7. The clock polarity is configured through the Bus Configuration Register (BCR[6]).
8. P refers to a clock pulse.
2MEG refers to
TABLE 2: Functional Description
Asynchronous Mode
MODE
POWER
CLK
ADV#
CE#
OE#
WE#
CRE
UB#/
LB#
WAIT
5
DQ0-DQ15
1
NOTES
Read
Active > Standby
L
L
L
L
H
L
L
1
L
Data-Out
4
Write
Active > Standby
L
L
L
X
L
L
L
1
L
Data-In
4
Standby
Standby
X
X
H
X
X
L
X
X
High-Z
2
Standby
Standby
X
X
L
X
X
L
X
X
X
4, 6
Mode Register Active
L
L
L
H
L
H
X
L
High-Z
DPD
Deep Power Down
L
X
H
X
X
H
X
X
High-Z
Burst Mode
MODE
POWER
CLK
8
ADV#
CE#
OE#
WE#
CRE
UB#/
LB#
WAIT
5
DQ0-DQ15
1
NOTES
Async. Read
Active > Standby
L
L
L
L
H
L
L
L
Data-Out
1,4
Async. Write
Active > Standby
L
L
L
X
L
L
L
L
Data-In
1,4
Standby
Standby
X
X
H
X
X
L
X
X
High-Z
2
Standby
Standby
X
X
L
X
X
L
X
X
X
4,6
Initial Burst
Read
Active > Standby
P
L
L
L
H
L
L
L
Data-Out
1,3,4,7
Initial Burst
Write
Active > Standby
P
L
L
H
L
L
X
L
Data-In
3,4,7
Burst Continue Active > Standby
P
H
L
X
X
L
X
X
Data-In or
Data-Out
3,4,7
Burst Suspend Active > Standby
L
X
L
X
X
L
X
X
High-Z
3,4
Mode Register Active
P
L
L
H
L
H
X
X
High-Z
3,7
DPD
Deep Power Down
L
X
H
X
X
H
X
X
High-Z
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N64T1618CBA
Advance Information
This is an ADVANCE DATASHEET and subject to change without notice.
Stock No. 23250-C 7/03
FUNCTIONAL DESCRIPTION
In general, the N64T1618CBA device can be con-
sidered a high-density alternative to SRAM prod-
ucts popular in low-power portable applications.
The N64T1618CBA contains 67,108,864 bits orga-
nized as 4,194,304 addresses x 16 bits. The
device implements the same high-speed bus inter-
face found on burst-mode Flash products.
The bus interface supports both asynchronous and
burst-mode transfers. Page-mode accesses are
also included as a bandwidth-enhancing extension
to the asynchronous read protocol.
POWER-UP INITIALIZATION
The N64T1618CBA includes an on-chip voltage
sensor used to launch the power-up initialization
process. Initialization will configure the Bus Config-
uration Register (BCR) and the Refresh Configura-
tion Register (RCR) with their default settings (See
Tables 3 and 6). V
CC
and V
CC
Q must be applied
simultaneously. Once they reach a stable level
above 1.70V, the device will require 150s to com-
plete its self-initialization process. During the initial-
ization period the CE# pin should remain HIGH.
Once initialization has completed, the device is
ready for normal operation.
Figure 2: Power-Up Initialization Timing
BUS OPERATING MODES
The N64T1618CBA product incorporates the burst
mode interface found on Flash products targeting
low-power wireless applications. This bus interface
supports asynchronous, page-mode and burst-
mode READ and WRITE transfers. The specific
interface supported is defined by the value loaded
into the Bus Configuration Register. Page Mode is
controlled by the Refresh Configuration Register
(RCR[7]).
Asynchronous Mode
The N64T1618CBA device default power-up state
is in the asynchronous operating mode. This mode
uses the industry standard SRAM control bus
(CE#, OE#, WE#, LB#/UB#). READ operations
(Figure 3) are initiated by bringing CE#, OE# and
LB#/UB# LOW while keeping WE# HIGH. Valid
data will be driven out of the I/O pins after the spec-
ified access time has elapsed. WRITE operations
(Figure 4) occur when CE#, WE# and LB#/UB# are
driven LOW. During asynchronous write operations
the OE# level is a "don't care," and WE# will over-
ride OE#. The data to be written will be latched on
the rising edge of CE#, WE# or LB#/UB# (which-
ever occurs first). Asynchronous operations (page-
mode disabled) can either use the ADV input to
latch the address, or ADV can be driven LOW dur-
ing the entire READ/WRITE operation.
During asynchronous operation the CLK input
should be held LOW. The WAIT pin will be driven
while the device is enabled and its state should be
ignored.
VCC
VccQ
Vcc=1.70V
Device Initialization
tPU>150s
Device ready for
normal operation
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Figure 3: READ Operation (ADV=LOW)
NOTE: ADV must remain LOW for page mode.
Figure 4: WRITE Operation (ADV=LOW)
CE#
ADDRESS
WE#
Data Valid
DATA
OE#
LB#,UB#
tRC = READ Cycle Time
ADDRESS VALID
DON'T CARE
CE#
ADDRESS
WE#
Data Valid
DATA
OE#
LB#,UB#
tWC = WRITE Cycle Time
ADDRESS VALID
DON'T CARE
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Page Mode READ Operation
Page mode is a performance-enhancing extension
to the legacy asynchronous READ operation. In
page-mode capable products, an initial asynchro-
nous read access is performed, and then adjacent
addresses can be read quickly by simply changing
the low-order address. The [A3:A0] inputs are used
to determine the members of the 16-address page.
Addresses [A4...] and higher must remain fixed
during the entire page mode access. Figure 5
shows the timing for a page mode access. Page
mode takes advantage of the fact that adjacent
addresses can be read in a shorter period of time
than random addresses. WRITE operations do not
include comparable page mode functionality. Dur-
ing asynchronous page-mode operation the CLK
input must be held LOW. CE# must be driven
HIGH upon completion of a page-mode access.
The WAIT pin will be driven while the device is
enabled and its state should be ignored. Page
mode is enabled by setting RCR[7] to HIGH.
WRITE operations do not include comparable
page-mode functionality. ADV must be driven LOW
during all page-mode READ accesses.
Figure 5: PAGE READ Operation (ADV=LOW)
Burst Mode
Burst-mode operations allow high-speed synchro-
nous READ and WRITE transactions. Burst opera-
tions consist of a multi-clock sequence that must
be performed in an ordered fashion. After CE#
goes LOW, the address to access is latched on the
next rising edge of CLK or ADV# (whichever
occurs first). During this first clock rising edge the
WE# pin indicates whether the operation is going
to be a READ (WE#=HIGH, Figure 6) or WRITE
(WE#=LOW, Figure 7). The size of a burst can be
specified in the BCR as either fixed length or con-
tinuous. Fixed-length bursts consist of four, eight or
sixteen words. Continuous bursts have the ability
to start at a specified address and burst through
the entire memory. The latency count stored in the
BCR defines how many clock cycles elapse before
the initial data value is transferred between the pro-
cessor and the device. The WAIT output will be
asserted as soon as a burst is initiated and will be
deasserted to indicate when data is to be trans-
ferred into (or out of) the memory. The WAIT pin
will again be asserted if the burst crosses a row
boundary. Once the device has restored the previ-
ous row's data and accessed the next row, the
WAIT pin will be deasserted and the burst can con-
tinue (See Figure 28). Rows consist of 128 words
and are defined by the address values placed on
[A21:A7].
CE#
ADDRESS
WE#
DATA
OE#
LB#,UB#
DON'T CARE
D[0]
D[1]
D[2]
D[3]
Add[0]
Add[1]
Add[2]
Add[3]
t
AA
t
APA
t
APA
t
APA
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Figure 6: Burst Mode READ (4-word burst)*
MEG
Figure 7: Burst Mode WRITE (4-word burst)*
*Non-default BCR settings: Latency Code 2 (3 clocks); WAIT active LOW; Hold Data one clock; WAIT asserted during delay.
CE#
WAIT
WE#
D0-D15
UB#/LB#
DON'T CARE
D[0]
D[1]
D[2]
D[3]
OE#
CLK
A0-A20
ADV#
Read Burst identified
(WE# = HIGH)
Latency Code 2 (3 clocks)
Address
Valid
CE#
WAIT
WE#
D0-D15
UB#/LB#
DON'T CARE
D[0]
D[1]
D[2]
D[3]
OE#
CLK
A0-A20
ADV#
Write Burst identified
(WE# = LOW)
Latency Code 2 (3 clocks)
Address
Valid
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Mixed Mode Operation
The device can support a combination of synchro-
nous READ and asynchronous WRITE operations
when the BCR is configured for synchronous oper-
ation. The asynchronous WRITE operation
requires that the clock (CLK) remain LOW during
the entire sequence. The ADV# signal can be used
to latch the target address or it can remain LOW
during the entire WRITE operation. CE# must
return HIGH when transitioning between mixed-
mode operations. Note that the
t
CKA period is the
same as a READ or WRITE cycle. This time is
required to assure adequate refresh. Mixed Mode
operation facilitates a seamless interface to legacy
burst-mode Flash memory controllers. See Figure
36 for the "Asynchronous Write Followed By Burst
Read" timing diagram.
Wait Operation
The WAIT pin on the device is typically connected
to a shared system-level WAIT signal (See Figure
8). The shared WAIT signal is used by the proces-
sor to coordinate transactions with multiple memo-
ries on the synchronous bus.
Figure 8: Wired OR Wait Configuration
Once a READ or WRITE transaction has been initi-
ated the WAIT pin goes active to indicate that the
device requires additional time before data can be
transferred. For READ operations, the WAIT pin
will remain active until valid data is output from the
device. For WRITE operations, WAIT will indicate
to the memory controller when data will be
accepted into the device. Once WAIT transitions to
an inactive state, the data burst will progress on
successive clock edges. CE# must remain
asserted at least as long as WAIT is asserted.
Bringing CE# HIGH while WAIT is asserted may
cause data corruption. The WAIT pin also performs
an arbitration role when a READ or WRITE opera-
tion is launched while an on-chip refresh is in
progress. If a collision occurs, the WAIT pin will be
asserted until the refresh has completed (See Fig-
ure 9 and Figure 10). Once the refresh operation
has completed, WAIT will be deasserted and the
READ or WRITE operation will be allowed to con-
tinue normally.
LB#/UB# Operation
The lower byte (LB#) enable and upper byte
enable (UB#) signals allow for byte-wide data
transfers. During READ operations the enabled
byte(s) are driven onto the DQs. The DQs associ-
ated with a disabled byte are put into a High-Z
state during a READ operation. During WRITE
operations, any disabled bytes will not be trans-
ferred to the RAM array and the internal value will
remain unchanged. During an asynchronous
WRITE cycle, the data to be written is latched on
the rising edge of CE#, WE#, LB# or UB#, which-
ever occurs first. When both the upper byte (UB#)
and lower byte (LB#) are disabled (HIGH) during
an operation, the device will disable the data bus
from receiving or transmitting data. Although the
device will seem to be deselected, the device
remains in an active mode as long as CE# remains
LOW.
READY
Processor
WAIT
WAIT
OTHER
DEVICE
WAIT
OTHER
DEVICE
Optional
External
Pull-Up/
Pull-Down
Resistor
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Figure 9: Refresh Collision during READ Operation*
Figure 10: Refresh Collision during WRITE Operation*
*Non-default BCR settings: Latency Code 2 (3 clocks); WAIT active LOW; Hold Data one clock; WAIT asserted during delay.
CE#
UB#/LB#
WE#
WAIT
D0-D15
DON'T CARE
D[0]
D[1]
D[2]
D[3]
OE#
CLK
A0-A21
ADV#
Wait states inserted to allow Refresh completion
Valid
Address
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
CE#
UB#/LB#
WE#
WAIT
D0-D15
DON'T CARE
D[0]
D[1]
D[2]
D[3]
OE#
CLK
A0-A21
ADV#
Wait states inserted to allow Refresh completion
Valid
Address
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
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LOW-POWER OPERATION
Standby Mode Operation
During standby the device current consumption is
reduced to the level necessary to perform the
DRAM refresh operation. Standby operation occurs
when the CE# pin is HIGH and there are no trans-
actions in progress.
The device will enter standby operation on comple-
tion of a READ or WRITE operation, or when the
address and control inputs remain static for an
extended period of time. This "active" standby
mode will continue until a change occurs to the
address or control inputs.
Deep Power Down Operation
Deep Power Down (DPD) operation disables all
refresh-related activity. This mode would be used if
the system did not require the storage provided by
the device. Any stored data will become corrupted
once the DPD is enabled. Once refresh activity has
been re-enabled, the device will require 150s to
perform an initialization procedure before normal
operations can resume. During this 150s period,
the current consumption will be higher than the
specified standby levels, but considerably lower
than the active-current specification.
Partial Array Self Refresh
Partial Array Self Refresh (PASR) restricts refresh
operation to a portion of the total memory array.
This feature allows the device to reduce standby
current by refreshing only that part of the memory
array required by the host system. The refresh
options are full array, array, array, array or
None of the array. The mapping of these partitions
can start at either the beginning or the end of the
address map (See Table 7). READ and WRITE
operations to address ranges receiving refresh will
not be affected. Data stored in addresses not
receiving refresh will become corrupted.
Temperature-Compensated Refresh
Temperature Compensated Refresh (TCR) is used
to adjust the refresh rate depending on the device
operating temperature. DRAM technology requires
increasingly frequent refresh operations to main-
tain data integrity as temperatures increase. More
frequent refresh is required due to increased leak-
age of the DRAM capacitive storage elements as
temperatures rise. A decreased refresh rate at
lower temperatures will facilitate a savings in
standby current. TCR allows for adequate refresh
at four different temperature thresholds (15C,
45C, 70C and 85C). The setting selected must
be for a temperature higher than the case tempera-
ture of the device. If the case temperature were
50C the system could minimize self-refresh cur-
rent consumption by selecting the 70C setting.
The 15C and 45C settings would result in inade-
quate refreshing and cause data corruption.
CONFIGURATION REGISTERS
Two WRITE-only user-accessible configuration
registers have been included to define device oper-
ation. The Bus Configuration Register (BCR)
defines how the N64T1618CBA interacts with the
system memory bus and is nearly identical to its
counterpart found on burst-mode Flash devices.
The Refresh Configuration Register (RCR) is used
to control how refresh is performed on the DRAM
array. These registers are automatically loaded
with default settings during power-up and can be
updated any time the devices are operating in a
standby state.
Bus Configuration Register
The Bus Configuration Register (BCR) defines how
the device interacts with the system memory bus.
Page mode operation is enabled by a bit contained
in the Refresh Configuration Register. The BCR is
loaded using either a synchronous or an asynchro-
nous WRITE operation when A19 is HIGH and the
Control Register Enable pin (CRE) is also HIGH
(see Figures 11 and 12). When CRE is LOW, a nor-
mal WRITE operation will access the memory
array. The values placed on address pins [A21:A0]
are latched into the BCR on the rising edge of
ADV#, CE#, or WE#, which ever occurs first. UB#
and LB# are "don't care." Table 3 describes the
control bits in the Bus Configuration Register. At
power-up, the BCR is set to 9F4Fh.
MEG
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Figure 11: Configuration Register WRITE in Asynchronous Mode followed by READ*
N*Non-default BCR settings: Latency Code 2 (3 clocks); WAIT active LOW; Hold Data one clock; WAIT asserted during delay.
NOTE: 1. A19=LOW to load RCR; A19=HIGH to load BCR.
UB#/LB#
WE#
D15-D0
DON'T CARE
CLK
A0-A20
(except A19)
OPCODE
CRE
A19
1
CE#
OE#
ADV#
ADDRESS
Open Address Bus Latch
Select Control Register
t
AVS
t
VPH
t
VP
t
CW
t
WP
Initiate Control Register Access
Write Address Bus
Value to Control Regis-
ter
ADDRESS
DATA VALID
t
WC
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Figure 12:
Configuration Register WRITE in Synchronous Mode followed by a READ*
MEG
*Non-default BCR settings: Latency Code 2 (3 clocks); WAIT active LOW; Hold Data one clock; WAIT asserted during delay.
NOTE: 1. A19=LOW to load RCR; A19=HIGH to load BCR.
CE#
UB#/LB#
WE#
WAIT
D15-D0
DON'T CARE
OE#
CLK
A0-A20
(except A19)
ADV#
OPCODE
CRE
A19
1
Latch Control Register Value
LatchControlRegisterAddress
t
SP
t
SP
t
CSP
t
SP
t
CW
t
HD
t
HD
HIGH-Z
HIGH-Z
Address
Address
t
WC
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TABLE 3: Bus Configuration Register Definition
MEG
NOTE: 1. All burst WRITES are continuous.
BCR[8]
WAIT Configuration
0
Asserted during delay
1
Asserted one data cycle before delay (default)
A21 -A20
BCR[19]
Register Select
0
Select RCR
1
Select BCR
BCR[15]
Operation Mode
0
Synchronous Burst Access Mode
1
Asynchronous Access Mode (Default)
BCR[10]
Wait Polarity
0
Active LOW
1
Active HIGH (Default)
BCR[13]
BCR[12]
BCR[11]
Latency Counter
0
0
0
Code 0-Reserved
0
0
1
Code 1-Reserved
0
1
0
Code 2
0
1
1
Code 3 (Default)
1
0
0
Code 4-Reserved
1
0
1
Code 5-Reserved
1
1
0
Code 6-Reserved
1
1
1
Code 7-Reserved
BCR[2]
BCR[1]
BCR[0]
Burst Length (Note 1)
0
0
1
4 words
0
1
0
8 words
0
1
1
16 words
1
1
1
Continuous burst (default)
BCR[3]
Burst Wrap
0
Burst wraps within the burst length
1
Burst no wrap (default)
BCR[5]
Output Impedance
0
Full Drive (default)
1
1/4 Drive
BCR[6]
Clock Configuration
0
Falling Edge
1
Rising Edge (default)
A19 A18-A16 A15 A14 A13 A12
A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
21 20
19
18-16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Must be set to "0"
Must be set to "0"
Must be set to "0"
Must be set to "0"
Must be set to "0"
Must be set to "0"
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Burst Length (BCR[2..0])
Default - Continuous Burst
Burst lengths define the number of words the
device outputs during a burst READ operation. The
device supports a burst length of 4, 8 or 16 words.
The device can also be set in continuous burst
mode where data is output sequentially without
regard to address boundaries. WRITE bursts are
always performed using continuous burst mode.
Burst Wrap (BCR[3])
Default=Burst Wraps Within Address Boundary
The burst wrap option determines if a 4, 8, or 16-
word READ burst wraps within the burst length or
steps through sequential addresses. If the wrap
option is not enabled, the device outputs data from
sequential addresses without regard to burst
boundaries. When continuous burst operation is
selected, the internal address wraps to 000000h if
the device is read past the last address.
Output Impedance (BCR[5])
Default=Outputs Use Full Drive Strength
The output driver strength can be altered to adjust
for different data bus loading scenarios. The
reduced-strength option will be more than ade-
quate in stacked chip (Flash + N64T1618CBA)
environments when there is a dedicated memory
bus. The reduced-drive-strength option is included
to minimize noise generated on the data bus during
READ operations. Normal output impedance
should be selected when using a discrete device in
a more heavily loaded data bus environment. The
devices are tested using the Full Drive Strength
setting. Partial drive is approximately 1/4 Full Drive
Strength.
TABLE 4: Sequence and Burst Length
STARTING
ADDRESS
WRAP
NO WRAP
4-WORD
BURST
LENGTH
8-WORD BURST LENGTH
16-WORD BURST LENGTH
CONTINUOUS BURST
(DEC)
BCR3
BCR3
LINEAR
LINEAR
LINEAR
LINEAR
0
0
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
0-1-2-3-4-5-6-...
1
0
1-2-3-0
1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 1-2-3-4-5-6-7-...
2
0
2-3-0-1
2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 2-3-4-5-6-7-8-...
3
0
3-0-1-2
3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 3-4-5-6-7-8-9-...
4
0
4-5-6-7-0-
1-2-3
4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3
4-5-6-7-8-9-10-...
5
0
5-6-7-0-1-
2-3-4
5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4
5-6-7-8-9-10-11-...
6
0
6-7-0-1-2-
3-4-5
6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5
6-7-8-9-10-11-12-
7
0
7-0-1-2-3-
4-5-6
7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6
7-8-9-10-11-12-13-...
...
...
...
...
...
...
...
14
0
14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 14-15-16-17-18-19-20-..
15
0
15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-16-17-18-19-20-21..
...
...
...
...
...
...
...
0
1
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
0-1-2-3-4-5-6-...
1
1
1-2-3-4
1-2-3-4-5-6-7-8
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 1-2-3-4-5-6-7-...
2
1
2-3-4-5
2-3-4-5-6-7-8-9
2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17 2-3-4-5-6-7-8-...
3
1
3-4-5-6
3-4-5-6-7-8-9-10
3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18 3-4-5-6-7-8-9-...
4
1
4-5-6-7-8-9-10-11
4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19 4-5-6-7-8-9-10-...
5
1
5-6-7-8-9-10-11-12
5-6-7-8-9-10-11-12-13-...-15-16-17-18-19-20 5-6-7-8-9-10-11...
6
1
6-7-8-9-10-11-12-13
6-7-8-9-10-11-12-13-14-...-16-17-18-19-20-21 6-7-8-9-10-11-12...
7
1
...
7-8-9-10-11-12-13-14
7-8-9-10-11-12-13-14-...-17-18-19-20-21-22 7-8-9-10-11-12-13...
...
...
...
...
...
...
...
14
1
...
14-15-16-17-18-19-...-23-24-25-26-27-28-29 14-15-16-17-18-19-20-
...
15
1
15-16-17-18-19-20-...-24-25-26-27-28-29-30 15-16-17-18-19-20-21-
...
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Clock Configuration (BCR[6])
Default=Transactions Processed On Rising
Edge Of Clock
The Clock Configuration Bit indicates whether syn-
chronous operations are dependant upon the rising
or falling edge of the clock pin. All of the timing dia-
grams in this data sheet show the bus interaction
aligned with the rising edge of the clock.
WAIT Configuration (BCR[8])
Default = WAIT Transitions One Clock Before
Data Valid/Invalid
The WAIT Configuration Bit is used to determine
when the WAIT pin transitions between the
asserted and the deasserted state with respect to
valid data presented on the data bus. The memory
controller will use the WAIT signal to coordinate
data transfer during synchronous read and write
operations. When BCR[8]=0, data will be valid or
invalid on the clock edge immediately after WAIT
transitions to the deasserted or asserted state
respectively (Figures 13, 16 and 17). When
BCR[8]=1, the WAIT signal transitions one clock
period prior to the data bus going valid or invalid
(Figures 14 and 16).
Figure 13: WAIT Configuration
(BCR[8]=0)
Figure 14: WAIT Configuration
(BCR[8]=1)
WAIT Polarity (BCR[10])
Default = WAIT Active HIGH
The WAIT Polarity Bit indicates whether an
asserted WAIT pin should be HIGH or LOW. This
bit will determine whether the WAIT signal requires
a pull-up or pull-down resistor to maintain the deas-
serted state.
Latency Counter (BCR[13..11])
Default = 3 Clock Latency
The Latency Counter Bits determine how many
clocks occur between the beginning of a READ or
WRITE operation and the first data value trans-
ferred. Only Latency Code 2 (3 clocks) or Latency
Code 3 (4 clocks) are allowed (see Table 5 and
Figure 18).
CLK
WAIT#
D0-D15
z
Data[0]
Data[1]
Data Immediately Valid (or Invalid)
CLK
WAIT#
D0-D15
Data[0]
Data Valid (or Invalid) After 1 Clock Delay
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Figure 16: WAIT and Hold Data Output During Burst READ Operation*
*Clocked on rising edge.
TABLE 5: Latency Configuration
1. Clock rates below 50 MHz are allowed as long as tCSP specs are satisfied.
Figure 18: Latency Counter
LATENCY CONFIGURATION CODE
MAX INPUT CLK FREQUENCY (MHZ)
-71
-86
2 (3 clocks)
75
44
1
3 (4 clocks)--default
104
66
DQ0-DQ15
DON'T CARE
CLK
WAIT
WAIT
D[0]
D[1]
D[2]
D[3]
D[4]
BCR[8]=0
DATA VALID IN CURRENT
CYCLE
BCR[8]=1
DATA VALID IN NEXT
CYCLE
DON'T CARE
CLK
A0-A21
DQ15-DQ0
VALID
ADDRESS
D15-D0
ADV#
Latency Code 2 (3 clocks)
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
Latency Code 3 (4 clocks)
UNDEFINED
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Operating Mode (BCR[15])
Default = Asynchronous Operation
The Operating Mode Bit selects either synchro-
nous burst operation or the default asynchronous
mode of operation.
REFRESH CONFIGURATION
REGISTER
The Refresh Configuration Register (RCR) defines
how the device performs its transparent self-
refresh. The RCR is loaded using either a synchro-
nous or an asynchronous WRITE operation when
A19 is LOW and the Control Register Enable pin
(CRE) is HIGH (see Figures 11 and 12). When
CRE is LOW, a WRITE operation will access the
memory array. The values placed on address pins
[A21:A0] are latched into the RCR on the rising
edge of ADV#, CE#, or WE#, which ever occurs
first. UB# and LB# are "don't care." Altering the
refresh parameters can dramatically reduce cur-
rent consumption during standby mode. Page-
mode control is also embedded into the Refresh
Configuration Register. Table 6 describes the con-
trol bits used in the Refresh Configuration Register.
At power-up, the RCR is set to 0070h.
Partial Array Self Refresh (RCR[2..0])
Default = Full Array Refresh
The PASR bits restrict refresh operation to a por-
tion of the total memory array. This feature allows
the device to reduce standby current by refreshing
only that part of the memory array required by the
host system. The refresh options are full array,
array, array, array or None of the array. The
mapping of these partitions can start at either the
beginning or the end of the address map (See
Table7).
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TABLE 6: Refresh Configuration Register
Deep Power Down (RCR[4])
Default = DPD Disabled
The Deep Power Down bit enables and disables all
refresh-related activity. This mode would be used if
the system did not require the storage provided by
the device. Any stored data will become corrupted
once the DPD is enabled.
Once refresh activity has been re-enabled, the
device will require 150s to perform an initialization
procedure before normal operations can resume.
Deep power down is enabled when RCR[4]=0 and
remains enabled until RCR[4] is set to a "1".
Temperature Compensated Refresh
(RCR[6..5])
Default = 85C Operation
The TCR bits allow for adequate refresh at four dif-
ferent temperature thresholds (15C, 45C, 70C
and 85C). The setting selected must be for a tem-
perature higher than the case temperature of the
device. If the case temperature were 50C, the
system could minimize self-refresh current con-
sumption by selecting the 70C setting. The 15C
and 45C settings would result in inadequate
TABLE 8: Address Patterns for PASR (A4=1)
RCR[2]
RCR[1]
RCR[0]
ACTIVE SECTION
ADDRESS SPACE
SIZE
DENSITY
0
0
0
Full die
000000h-3FFFFFh
4Mb x 16
64Mb
0
0
1
Three-quarters of die 000000h-2FFFFFh
3Mb x 16
48Mb
0
1
0
One-half of die
000000h-1FFFFFh
2Mb x 16
32Mb
0
1
1
One-quarter of die
000000h-0FFFFFh
1Mb x 16
16Mb
1
0
0
None of die
0
0Mb
0Mb
1
0
1
Three-quarters of die 100000h-3FFFFFh
3Mb x 16
48Mb
1
1
0
One-half of die
200000h-3FFFFFh
2Mb x 16
32Mb
1
1
1
One-quarter of die
300000h-3FFFFFh
1Mb x 16
16Mb
A21-A20
RCR[7]
Page Mode Enable/Disable
0
No Page Mode (Default)
1
Page Mode Enable
RCR[6]
RCR[5]
Maximum Case Temp.
1
1
85C(Default)
0
0
70C
0
1
45C
1
0
15C
RCR[4]
Deep Power Down
0
DPD Enable
1
DPD Disable (default)
RCR[19]
Register Select
0
Select RCR
1
Select BCR
RCR[2]
RCR[1]
RCR[0]
Refresh Coverage
0
0
0
Full array (default)
0
0
1
Bottom 3/4 array
0
1
0
Bottom 1/2 array
0
1
1
Bottom 1/4 array
1
0
0
None of array
1
0
1
Top 3/4 array
1
1
0
Top 1/2 array
1
1
1
Top 1/4 array
A19 A18-A8
A7
A6
A5
A4
A3
A2
A1
A0
21-20
19
18-8
7
6
5
4
3
2
1
0
All must be set to "0"
Must be set to "0"
All must be set to "0"
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refreshing and cause data corruption.
Page Mode Operation (RCR[7])
Default = Disabled
The Page Mode Operation Bit determines whether
page mode is enabled for asynchronous READ
operations. The power-up default state is for page
mode to be disabled.
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ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Ball Except Vcc, VccQ
Relative to Vss..........-0.5V to the lesser of +4V or VccQ+0.3V
Voltage on Vcc Supply Relative to Vss....-0.2V to +2.45V
Voltage on VccQ Supply Relative to Vss.-0.2V to +4.0V
Storage Temperature (plastic).................-55C to +150C
Operating Temperature...........................-25C to +85C
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at
these or any other conditions above those indicated in the oper-
ational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect reliability.
NOTE:
1. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current
required to drive output capacitance expected in the actual system.
2. This device assumes a standby mode if the chip is disabled (CE# HIGH). It will also automatically go into a standby
mode whenever all input signals are quiescent (not toggling), regardless of the state of CE#. In order to achieve low
standby current all inputs must be driven to either V
CC
or V
SS
.
3. I
SB
(max) values measured with PASR set to FULL ARRAY and TCR set to 85C.
TABLE 8: Electrical Characteristics and Operating Conditions
DESCRIPTION
CONDITIONS
SYMBOL
-70 (104MHZ)
-85 (66MHZ)
UNITS NOTES
MIN
MAX
MIN
MAX
Supply Voltage
V
CC
1.70
1.95
1.70
1.95
V
I/O Supply Voltage
VccQ
3.0V
tbd
tbd
tbd
tbd
V
2.5V
tbd
tbd
tbd
tbd
V
1.8V
1.70
2.25
1.70
2.25
V
Input High Voltage
V
IH
1.4
VccQ+
0.2
1.4
VccQ+
0.2
V
Input Low Voltage
V
IL
-0.2
0.4
-0.2
0.4
V
Output High Voltage
IOH = -0.2mA
V
OH
0.8
VccQ
0.8
VccQ
V
Output Low Voltage
IOL = 0.2mA
V
OL
0.2
VccQ
0.2
VccQ
V
Input Leakage Current
VIN = 0 to VCC
I
LI
1
1
A
Output Leakage Current
OE# = VIH or
Chip Disabled
I
LO
1
1
A
READ Operating Current
Asynchronous Random READ
Asynchronous Page READ
Initial Access, Burst READ
Continuous Burst READ
VIN = VCC or 0V
Chip Enabled,
IOUT = 0
I
CC
1
25
15
35
11
25
15
35
11
mA
1,2
Write Operating Current
VIN = VCC or 0V
Chip Enabled
I
CC
2
25
25
mA
1,2
Standby Current
VIN = VCC or 0V
Chip Disabled
I
SB
100
100
A
2,3
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NOTE: I
PASR
(max) values measured with TCR set to 85C.
NOTE: 1.These parameters are verified in device characterization and are not 100% tested.
TABLE 9: Partial Array Self Refresh Specifications and Conditions
DESCRIPTION
CONDITIONS
SYMBOL
ARRAY
PARTITION
TYP
MAX
UNITS
Partial Array Self
Refresh Standby
Current
Vin = Vcc or 0V,
Chip Disabled
I
PASR
Full
100
A
3/4
tbd
A
1/2
tbd
A
1/4
tbd
A
0
50
A
TABLE 10: Temperature Compensated Refresh Specifications and Conditions
DESCRIPTION
CONDITIONS
SYMBOL
MAX
TEMPERATURES
TYP
MAX
UNITS
Temperature Compensated
Refresh Standby Current
V
IN
= V
CC
or 0V
Chip Disabled
I
TCR
85C
70C
45C
15C
100
tbd
tbd
50
A
A
A
A
TABLE 11: Deep Power Down Specifications and Conditions
DESCRIPTION
CONDITIONS
SYMBOL
TYP
MAX
UNITS
Deep Power Down
V
IN
= V
CC
or 0V; +25C
I
ZZ
10
A
TABLE 12: Capacitance
DESCRIPTION
CONDITIONS
SYMBOL
TYP
MAX
UNITS
NOTES
Input Capacitance
TA = 25C; f = 1 MHz;
V
IN
= 0V
C
IN
-
6
pF
1
Input/Output Capacitance (DQ)
C
I/O
-
6
pF
1
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Figure 19: AC Input/Output Reference Waveform
Figure 20: Output Load Circuit
2MEG x 16, 4MEG x
All tests are performed with the outputs configured for full drive strength (BCR[5]=0).
V
CC
V
SS
V
CC
/2
Input
V
CC
Q/2
Output
Test Points
V
CC
Q
DUT
30pF
R1
R2
Test Point
VccQ
R1/R2
1.8V
2.7K
2.5V
3.7K
3.0V
4.5K
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N64T1618CBA
Advance Information
This is an ADVANCE DATASHEET and subject to change without notice.
Stock No. 23250-C 7/03
NOTE:
1. All tests are performed with the outputs configured for full drive strength (BCR[5]=0).
2. See the Application Note at the end of this datasheet.
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 20. The Low-Z timings measure a 100mV transition away
from the High-Z (VccQ/2) level toward either V
OH
or V
OL
.
4. Low-Z to High-Z timings are tested with the circuit shown in Figure 20. The High-Z timings measure a 100mV transition from
either V
OH
or V
OL
toward VccQ/2.
2MEG
TABLE 13: Asynchronous READ Cycle Timing Requirements
PARAMETER
SYMBO
L
-71, 76
-86
UNITS NOTES
MIN
MAX
MIN
MAX
Maximum CE# Pulse Width
t
CEM
10
10
s
2
READ Cycle Time
t
RC
70
85
ns
Page Access Time
t
APA
20
25
ns
Page Cycle Time
t
PC
20
25
ns
Address Access Time
t
AA
70
85
ns
Chip Select Access Time
t
CO
70
85
ns
Output Enable to Valid Output
t
OE
20
20
ns
UB#, LB# Access Time
t
BA
70
85
ns
Chip Enable to Low-Z Output
t
LZ
10
10
ns
3
Output Enable to Low-Z Output
t
OLZ
5
5
ns
3
UB#, LB# Enable to Low-Z Output
t
BLZ
10
10
ns
3
Chip Disable to High-Z Output
t
HZ
0
8
0
8
ns
4
Output Disable to High-Z Output
t
OHZ
0
8
0
8
ns
4
UB#, LB# Disable to High-Z Output
t
BHZ
0
8
0
8
ns
4
Output Hold from Output Disable
t
OH
5
5
ns
Output Hold from Address Change
t
OHA
5
5
ns
Address Setup to ADV# HIGH
t
AVS
10
10
ns
CE# LOW to ADV# HIGH
t
CVS
10
10
ns
ADV# Access Time
t
AADV
70
85
ns
ADV# PULSE WIDTH LOW
t
VP
10
10
ns
ADV# PULSE WIDTH HIGH
t
VPH
10
10
ns
Address Hold from ADV# HIGH
t
AVH
5
5
ns
Address setting time
t
S
10
10
ns
2
CE# HIGH between subsequent Mixed Mode
operation
t
CBHP
5
5
ns
CE# LOW to WAIT Valid
t
CEW
1
7.5
1
7.5
ns
NanoAmp Solutions, Inc.
25
N64T1618CBA
Advance Information
This is an ADVANCE DATASHEET and subject to change without notice.
Stock No. 23250-C 7/03
NOTE:
1. All tests are performed with the outputs configured for full drive strength (BCR[5]=0).
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 20, The High-Z timings measure a 100mV transi-
tion from either V
OH
or V
OL
toward VccQ/2.
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 20. The Low-Z timings measure a 100mV transi-
tion away from the High-Z (VccQ/2) level toward either V
OH
or V
OL
.
4. Clock rates below 50MHz are allowed as long as tCSP specs are satisfied.
TABLE 14: Burst READ Cycle Timing Requirements
1
PARAMETER
SYMBOL
-71
-76, -86
UNITS
NOTES
MIN
MAX
MIN
MAX
CLK period
t
CLK
9.62
20
15
20
ns
4
CLK HIGH or LOW time
t
KP
3
3
ns
CLK rise or fall time
t
KHKL
1.6
1.6
ns
Setup time to active CLK edge
t
SP
3
3
ns
Hold time from active CLK edge
t
HD
1
1
ns
CLK to output delay
t
ACLK
6.5
10
ns
Output hold from CLK
t
KOH
2
2
ns
CLK to WAIT delay
t
KHTL
6.5
10
ns
Burst to READ access time
t
ABA
33
55
ns
CE# Setup time to active CLK edge
t
CSP
4
20
4
20
ns
Chip Disable to High-Z Output
t
HZ
0
8
0
8
ns
2
Output Disable to High-Z Output
t
OHZ
0
8
0
8
ns
2
CLK to High-Z Output
t
KHZ
3
8
3
8
ns
Output Enable to Low-Z Output
t
OLZ
5
5
ns
3
CLK to Low-Z Output
t
KLZ
2
5
2
5
ns
CE# HIGH between subsequent Mixed
Mode operations
t
CBPH
5
5
ns
Address Setup to ADV# High
t
AVS
10
10
ns
Burst OE# LOW to output delay
t
BOE
20
20
ns
CE# LOW to WAIT Valid
t
CEW
1
7.5
1
7.5
ns
NanoAmp Solutions, Inc.
26
N64T1618CBA
Advance Information
This is an ADVANCE DATASHEET and subject to change without notice.
Stock No. 23250-C 7/03
NOTE:
1. See Application Note at end of document.
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 20, The High-Z timings measure a 100mV transi-
tion from either V
OH
or V
OL
toward VccQ/2.
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 20. The Low-Z timings measure a 100mV transi-
tion away from the High-Z (VccQ/2) level toward either V
OH
or V
OL
.
TABLE 15: Asynchronous WRITE Cycle Timing Requirements
PARAMETER
SYMBOL
-71, -76
-86
UNITS
NOTES
MIN
MAX
MIN
MAX
Maximum CE# Pulse Width
t
CEM
10
10
s
1
WRITE Cycle time
t
WC
70
85
ns
Chip Enable to End of Write
t
CW
70
85
ns
Address Valid to End of Write
t
AW
70
85
ns
UB#/LB# Select to End of Write
t
BW
70
85
ns
WRITE Pulse Width
t
WP
46
55
ns
1
WRITE Recovery Time
t
WR
0
0
ns
WRITE to High-Z Output
t
WHZ
0
8
0
8
ns
2
Data to WRITE Time Overlap
t
DW
23
23
ns
1
Data Hold from Write Time
t
DH
0
0
ns
End WRITE to Low-Z Output
t
OW
5
5
ns
3
ADV# Pulse Width
t
VP
10
10
ns
Chip Enable to Low-Z Output
t
LZ
10
10
ns
3
ADV# Setup to end of Write
t
VS
70
85
ns
Address Setup to ADV# going High
t
AVS
10
10
ns
CE# LOW to WAIT Valid
t
CEW
1
7.5
1
7.5
ns
Address Hold from ADV# going High
t
AVH
5
5
ns
WRITE Pulse Width High
t
WPH
10
10
ns
ADV# Pulse Width High
t
VPH
10
10
ns
Address Setup Time
t
AS
0
0
s
1
CE# Low to ADV# High
t
CVS
10
10
ns
Async Address-to-Burst Transition Time
t
CKA
70
85
ns
NanoAmp Solutions, Inc.
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N64T1618CBA
Advance Information
This is an ADVANCE DATASHEET and subject to change without notice.
Stock No. 23250-C 7/03
1. Clock rates below 50MHz are allowed as long as tCSP specs are satisfied.
TABLE 17: Initialization Timing Requirements
16, 4MEG x 16ASYNC / PAGE
Figure 21: Initialization Period
G x 16, 4MEG x 16ASYNC / PAGE /
TABLE 16: Burst WRITE Cycle Timing Requirements
PARAMETER
SYMBOL
-71
-76, -86
UNITS
NOTES
MIN
MAX
MIN
MAX
Clock period
t
CLK
9.62
20
15
20
ns
1
Setup time to activate CLK edge
t
SP
3
3
ns
Hold time from active CLK edge
t
HD
1
1
ns
CE# setup to CLK active edge
t
CSP
4
20
4
20
ns
CE# LOW to WAIT Valid
t
CEW
1
7.5
1
7.5
ns
Clock to WAIT Delay
t
KHTL
6.5
10
ns
CE# HIGH between subsequent
Mixed Mode operations
t
CBPH
5
5
ns
CLK HIGH or LOW time
t
KP
3
3
ns
CLK rise or fall time
t
KHKL
1.6
1.6
ns
PARAMETER
SYMBOL
-71, -76, -86
UNITS
NOTES
MIN
MAX
Initialization period
t
PU
150
s
Vcc,VccQ=1.70V
tPU
VccMIN
Device ready for
normal operation
NanoAmp Solutions, Inc.
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N64T1618CBA
Advance Information
This is an ADVANCE DATASHEET and subject to change without notice.
Stock No. 23250-C 7/03
TIMING DIAGRAMS
Figure 22: ASYNCHRONOUS READ
16, 4MEG x 16ASYNC / PAGE /
OE#
WAIT
DQ0-DQ15
DON'T CARE
WE#
A0-A21
UL#/LB#
CE#
ADV#
V
IH
VALID ADDRESS
High-Z
High-Z
V
IL
t
RC
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t
AA
t
CBPH
t
CO
t
BA
t
HZ
t
BHZ
t
OHZ
t
OE
t
OH
t
OLZ
t
BLZ
t
LZ
t
CEW
High-Z
UNDEFINED
Valid
Output
TABLE 18: Asynchronous READ Timing Parameters
SYMBOL
-71, -76
-86
UNITS
SYMBOL
-71, -76
-86
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
RC
70
85
ns
t
BHZ
0
8
0
8
ns
t
AA
70
85
ns
t
OHZ
0
8
0
8
ns
t
OH
5
5
ns
t
LZ
10
10
ns
t
CEW
1
7.5
1
7.5
ns
t
BLZ
10
10
ns
t
BA
70
85
ns
t
CBPH
5
5
ns
t
CO
70
85
ns
t
OE
20
20
ns
t
OLZ
5
5
ns
t
HZ
0
8
0
8
ns
NanoAmp Solutions, Inc.
29
N64T1618CBA
Advance Information
This is an ADVANCE DATASHEET and subject to change without notice.
Stock No. 23250-C 7/03
Figure 23: Asynchronous READ Using ADV#
TABLE 19: Asynchronous READ Timing Parameters (Using ADV#)
OE#
WAIT
DQ0-DQ15
DON'T CARE
WE#
A0-A21
UB#/LB#
CE#
ADV#
V
IH
VALID ADDRESS
High-Z
High-Z
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t
AA
t
CBPH
t
CO
t
BA
t
HZ
t
BHZ
t
OHZ
t
OE
t
OH
t
OLZ
t
BLZ
t
LZ
t
CEW
High-Z
UNDEFINED
Valid
Output
t
AVH
t
AVS
t
VPH
t
AADV
t
VP
t
CVS
SYMBOL
-71, -76
-86
UNITS
SYMBOL
-71, -76
-86
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
CO
70
85
ns
t
OHZ
0
8
0
8
ns
t
AA
70
85
ns
t
LZ
10
10
ns
t
OH
5
5
ns
t
BLZ
10
10
ns
t
CEW
1
7.5
1
7.5
ns
t
AADV
70
85
ns
t
BA
70
85
ns
t
AVS
10
10
ns
t
OLZ
5
5
ns
t
CVS
10
10
ns
t
CBPH
5
5
ns
t
AVH
5
5
ns
t
OE
20
20
ns
t
VPH
10
10
ns
t
HZ
0
8
0
8
ns
t
VP
10
10
ns
t
BHZ
0
8
0
8
ns
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N64T1618CBA
Advance Information
This is an ADVANCE DATASHEET and subject to change without notice.
Stock No. 23250-C 7/03
Figure 24: Page Mode READ
OE#
WAIT
DQ0-DQ15
DON'T CARE
WE#
A4-A21
UB#/LB#
CE#
ADV#
V
IH
High-Z
High-Z
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t
CO
t
BA
t
HZ
t
BHZ
t
OHZ
t
OE
t
OLZ
t
BLZ
t
LZ
t
CEW
High-Z
UNDEFINED
Valid
Output
VALID ADDRESS
t
RC
A0-A3
V
IH
V
IL
VALID ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
t
AA
t
PC
t
CBPH
t
CBPH
Valid
Output
Valid
Output
Valid
Output
t
OH
t
OHA
t
APA
TABLE 20: Asynchronous READ Timing Parameters (Page Mode Operation)
SYMBOL
-71, -76
-86
UNITS
SYMBOL
-71, -76
-86
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
RC
70
85
ns
t
LZ
10
10
ns
t
AA
70
85
ns
t
OLZ
5
5
ns
t
APA
20
25
ns
t
HZ
0
8
0
8
ns
t
BA
70
85
ns
t
BHZ
0
8
0
8
ns
t
CO
70
85
ns
t
OHZ
0
8
0
8
ns
t
OE
20
20
ns
t
OH
5
5
ns
t
CBPH
5
5
ns
t
OHA
5
5
ns
t
CEW
1
7.5
1
7.5
ns
t
PC
20
25
ns
t
BLZ
10
10
ns
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N64T1618CBA
Advance Information
This is an ADVANCE DATASHEET and subject to change without notice.
Stock No. 23250-C 7/03
.
Figure 25: Single Access Burst READ Operation*
*Non-default BCR settings: Latency Code 2 (3 clocks); WAIT active LOW; Hold Data one clock; WAIT asserted during delay.
CE#
LB#/UB#
WE#
WAIT
DQ0-DQ15
DON'T CARE
OE#
CLK
A0-A21
ADV#
Read Burst Identified
(WE# = HIGH)
Valid
Address
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
High-Z
Valid
Output
High-Z
High-Z
t
CLK
t
KP
t
SP
t
HD
t
AVS
t
SP
t
CSP
t
ABA
t
HD
t
HZ
t
OHZ
t
OLZ
t
HD
t
SP
t
HD
t
SP
t
KOH
t
ACLK
t
KHTL
UNIDENTIFIED
t
BOE
TABLE 21: Burst READ Timing Parameters
SYMBOL
-71
-76, -86
UNITS
SYMBOL
-71
-76, -86
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
AVS
10
10
ns
t
CSP
4
20
4
20
ns
t
HZ
0
8
0
8
ns
t
BOE
20
4
ns
t
OHZ
0
8
0
8
ns
t
ABA
33
55
ns
t
CLK
9.62
20
15
20
ns
t
OLZ
5
5
ns
t
ACLK
6.5
10
ns
t
CEW
1
7.5
1
7.5
ns
t
KOH
2
2
ns
t
KHTL
6.5
10
ns
t
SP
3
3
ns
t
KP
3
3
ns
t
HD
1
1
ns
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N64T1618CBA
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This is an ADVANCE DATASHEET and subject to change without notice.
Stock No. 23250-C 7/03
Figure 26: 4-Word Burst READ Operation*
*Non-default BCR settings: Latency Code 2 (3 clocks); WAIT active LOW; Hold Data one clock; WAIT asserted during delay.
CE#
LB#/UB#
WE#
WAIT
DQ0-DQ15
DON'T CARE
OE#
CLK
A0-A21
ADV#
Read Burst Identified
(WE# = HIGH)
Valid
Address
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
High-Z
High-Z
High-Z
t
CLK
t
KP
t
SP
t
HD
t
AVS
t
SP
t
CSP
t
ABA
t
HD
t
HZ
t
OLZ
t
HD
t
SP
t
HD
t
SPK
t
KOH
t
ACLK
t
KHTL
UNIDENTIFIED
t
CBPH
Valid
Output
Valid
Output
Valid
Output
Valid
Output
t
BOE
t
CEW
t
OHZ
TABLE 22: Burst READ Timing Parameters
SYMBOL
-71
-76, -86
UNITS
SYMBOL
-71
-76, -86
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
AVS
10
10
ns
t
SP
3
3
ns
t
HZ
0
8
0
8
ns
t
HD
1
1
ns
t
OHZ
0
8
0
8
ns
t
CSP
4
20
4
12
ns
t
CLK
9.62
20
15
20
ns
t
OLZ
5
5
ns
t
ACLK
6.5
10
ns
t
CBPH
5
5
ns
t
BOE
20
20
ns
t
KHTL
6.5
10
ns
t
KOH
2
2
ns
t
KP
3
3
ns
t
ABA
33
55
ns
t
CEW
1
7.5
1
7.5
ns
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N64T1618CBA
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Stock No. 23250-C 7/03
Figure 27: READ Burst Suspend*
*Non-default BCR settings: Latency Code 2 (3 clocks); WAIT active LOW; Hold Data one clock; WAIT asserted during delay.
CE#
LB#/UB#
WE#
WAIT
DQ0-DQ15
DON'T CARE
OE#
CLK
A0-A21
ADV#
Valid
Address
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
High-Z
t
CLK
t
KP
t
SP
t
HD
t
AVS
t
SP
t
CSP
t
OLZ
t
HD
t
SP
t
HD
t
SP
t
KOH
t
ACLK
t
KHTL
UNIDENTIFIED
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Address
High-Z
Valid
Output
Valid
Output
High-Z
t
HZ
t
CBPH
t
OHZ
TABLE 23: Burst READ Timing Parameters
SYMBOL
-71
-76, -86
UNITS
SYMBOL
-71
-76, -86
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
HZ
0
8
0
8
ns
t
CSP
4
20
4
12
ns
t
OHZ
0
8
0
8
ns
t
CBPH
5
5
ns
t
CLK
9.62
20
15
20
ns
t
OLZ
5
5
ns
t
ACLK
6.5
10
ns
t
KP
3
3
ns
t
AVS
10
10
ns
t
BOE
20
20
ns
t
SP
3
3
ns
t
KOH
2
2
ns
t
HD
1
1
ns
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Figure 28: Continuous Burst READ Showing an Output Delay with BCR[8] = 0(1)
for End of Row Condition*
*Non-default BCR settings: Latency Code 2 (3 clocks); WAIT active LOW; Hold Data one clock; WAIT asserted during delay.
MEG x 16, 4MEG x 6ASYNC /
PAGE /
CE#
LB#/UB#
WE#
WAIT
DQ0-DQ15
DON'T CARE
OE#
CLK
A0-A21
ADV#
WAIT CONFIG (BCR8)=0
WAIT CONFIG (BCR8)=1
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
t
KP
t
KHKL
t
CLK
UNIDENTIFIED
Valid
Output
Valid
Output
Valid
Output
Valid
Output
t
KHTL
t
KHTL
TABLE 24: Burst READ Timing Parameters
SYMBOL
-71
-76, -86
UNITS
SYMBOL
-71
-76, -86
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
CLK
9.62
20
15
20
ns
t
ACLK
6.5
10
ns
t
KP
3
3
ns
t
KOH
2
2
ns
t
KHKL
1.6
1.6
ns
t
KHTL
6.5
10
ns
NanoAmp Solutions, Inc.
35
N64T1618CBA
Advance Information
This is an ADVANCE DATASHEET and subject to change without notice.
Stock No. 23250-C 7/03
Figure 29: CE# Controlled Asynchronous WRITE
OE#
WAIT
DQ0-DQ15
IN
DON'T CARE
WE#
A0-A21
UL#/LB#
CE#
ADV#
V
IH
VALID ADDRESS
High-Z
High-Z
V
IL
t
WC
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t
AW
t
CEM
t
DW
t
CEW
High-Z
Valid
Input
DQ0-DQ15
OUT
V
IL
t
WR
t
CW
t
AS
t
WP
t
BW
t
WPH
t
DH
t
LZ
t
WHZ
TABLE 25: Asynchronous WRITE Timing Parameters
SYMBOL
-71
-76, -86
UNITS
SYMBOL
-71
-76, -86
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
AS
0
0
ns
t
DW
23
23
ns
t
AW
70
85
ns
t
LZ
10
10
ns
t
BW
70
85
ns
t
WC
70
85
ns
t
CEM
10
10
s
t
WHZ
0
8
0
8
ns
t
CEW
1
7.5
1
7.5
ns
t
WP
46
55
ns
t
CW
70
85
ns
t
WPH
10
10
ns
t
DH
0
0
ns
t
WR
0
0
ns
NanoAmp Solutions, Inc.
36
N64T1618CBA
Advance Information
This is an ADVANCE DATASHEET and subject to change without notice.
Stock No. 23250-C 7/03
Figure 30: LB#/UB# Controlled Asynchronous WRITE
OE#
WAIT
DQ0-DQ15
IN
DON'T CARE
WE#
A0-A21
UL#/LB#
CE#
ADV#
V
IH
VALID ADDRESS
High-Z
High-Z
V
IL
t
WC
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t
AW
t
CEM
t
DW
t
CEW
High-Z
Valid
Input
DQ0-DQ15
OUT
V
IL
t
WR
t
CW
t
AS
t
WP
t
BW
t
WPH
t
DH
t
LZ
t
WHZ
TABLE 26: Asynchronous WRITE Timing Parameters
SYMBOL
-71
-76, -86
UNITS
SYMBOL
-71
-76, -86
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
AS
0
0
ns
t
DW
23
23
ns
t
AW
70
85
ns
t
LZ
10
10
ns
t
BW
70
85
ns
t
WC
70
85
ns
t
CEM
10
10
s
t
WHZ
0
8
0
8
ns
t
CEW
1
7.5
1
7.5
ns
t
WP
46
55
ns
t
CW
70
85
ns
t
WPH
10
10
ns
t
DH
0
0
ns
t
WR
0
0
ns
NanoAmp Solutions, Inc.
37
N64T1618CBA
Advance Information
This is an ADVANCE DATASHEET and subject to change without notice.
Stock No. 23250-C 7/03
Figure 31: WE# Controlled Asynchronous WRITE
OE#
WAIT
DQ0-DQ15
IN
DON'T CARE
WE#
A0-A21
UL#/LB#
CE#
ADV#
V
IH
VALID ADDRESS
High-Z
High-Z
V
IL
t
WC
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t
AW
t
CEM
t
DW
t
CEW
High-Z
Valid
Input
DQ0-DQ15
OUT
V
IL
t
WR
t
CW
t
AS
t
WP
t
BW
t
WPH
t
DH
t
LZ
t
WHZ
t
OW
TABLE 27: Asynchronous WRITE Timing Parameters
SYMBOL
-71
-76, -86
UNITS
SYMBOL
-71
-76, -86
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
AS
0
0
ns
t
LZ
10
10
ns
t
AW
70
85
ns
t
OW
5
5
ns
t
BW
70
85
ns
t
WC
70
85
ns
t
CEM
10
10
s
t
WHZ
0
8
0
8
ns
t
CEW
1
7.5
1
7.5
ns
t
WP
46
55
ns
t
CW
70
85
ns
t
WPH
10
10
ns
t
DH
0
0
ns
t
WR
0
0
ns
t
DW
23
23
ns
NanoAmp Solutions, Inc.
38
N64T1618CBA
Advance Information
This is an ADVANCE DATASHEET and subject to change without notice.
Stock No. 23250-C 7/03
Figure 32: Asynchronous WRITE Using ADV#
MEG x 16, 4MEG x
OE#
WAIT
DQ0-DQ15
IN
DON'T CARE
WE#
A0-A21
UL#/LB#
CE#
ADV#
V
IH
VALID ADDRESS
High-Z
High-Z
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t
AW
t
CEM
t
DW
t
CEW
High-Z
Valid
input
DQ0-DQ15
OUT
V
IL
t
CW
t
VS
t
WP
t
BW
t
WPH
t
DH
t
LZ
t
WHZ
t
AVS
t
AVH
t
VPH
t
VP
t
AS
TABLE 28: Asynchronous WRITE Timing Parameters
SYMBOL
-71
-76, -86
UNITS
SYMBOL
-71
-76, -86
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
AS
0
0
ns
t
DW
23
23
ns
t
AVH
5
5
ns
t
LZ
10
10
ns
t
AVS
10
10
ns
t
OW
5
5
ns
t
AW
70
85
ns
t
VP
10
10
ns
t
BW
70
85
ns
t
VPH
10
10
ns
t
CEM
10
10
s
t
VS
70
85
ns
t
CEW
1
7.5
1
7.5
ns
t
WHZ
0
8
0
8
ns
t
CW
70
85
ns
t
WP
46
55
ns
t
DH
0
0
ns
t
WPH
10
10
ns
NanoAmp Solutions, Inc.
39
N64T1618CBA
Advance Information
This is an ADVANCE DATASHEET and subject to change without notice.
Stock No. 23250-C 7/03
Figure 33: Burst WRITE Operation*
*Non-default BCR settings: Latency Code 2 (3 clocks); WAIT active LOW; Hold Data one clock; WAIT asserted during
delay.
CE#
LB#/UB#
WE#
WAIT
DQ0-DQ15
DON'T CARE
OE#
CLK
A0-A21
ADV#
Write Burst Identified
(WE# = LOW)
Valid
Address
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
High-Z
High-Z
t
CLK
t
SP
t
CSP
t
CEW
t
HD
t
CBPH
D[0]
D[1]
D[2]
D[3]
High-Z
t
SP
t
HD
t
HD
t
SP
t
HD
t
SP
t
HD
t
KHTL
TABLE 29: Burst WRITE Timing Parameters (4-Word Burst WRITE Operation)
SYMBOL
-71
-76, -86
UNITS
SYMBOL
-71
-76, -86
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
CLK
9.62
20
15
20
ns
t
CSP
4
20
4
20
ns
t
SP
3
3
ns
t
CBPH
5
5
ns
t
HD
1
1
ns
t
KHTL
6.5
10
ns
t
CEW
1
7.5
1
7.5
ns
NanoAmp Solutions, Inc.
40
N64T1618CBA
Advance Information
This is an ADVANCE DATASHEET and subject to change without notice.
Stock No. 23250-C 7/03
Figure 34: Continuous Burst WRITE Showing an Output Delay with BCR[8] = 0(1)
for End of Row Condition*
*Non-default BCR settings: Latency Code 2 (3 clocks); WAIT active LOW; Hold Data one clock; WAIT asserted during delay.
CE#
LB#/UB#
OE#
WAIT
DQ0-DQ15
DON'T CARE
WE#
CLK
A0-A21
ADV#
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
t
KP
t
KHKL
t
CLK
Valid
Input
Valid
Input
Valid
Input
Valid
Input
t
KHTL
t
KHTL
t
SP
t
HD
D[n]
D[n+1]
D[n+2]
D[n+3]
TABLE 30: Burst WRITE Timing Parameters
SYMBOL
-71
-76, -86
UNITS
SYMBOL
-71
-76, -86
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
CLK
9.62
20
15
20
ns
t
SP
3
3
ns
t
KP
3
3
ns
t
HD
1
1
ns
t
KHKL
1.6
1.6
ns
t
KHTL
6.5
10
ns
NanoAmp Solutions, Inc.
41
N64T1618CBA
Advance Information
This is an ADVANCE DATASHEET and subject to change without notice.
Stock No. 23250-C 7/03
Figure 35: Burst WRITE Followed by Burst READ*
NOTE:*Non-default BCR settings: Latency Code 2 (3 clocks); WAIT active LOW; Hold Data one clock; WAIT asserted during delay.
1.To allow self-refresh operations to occur between transactions, CE# must remain HIGH for at least 5ns (tCBPH) to schedule the
appropriate internal refresh operation.
CE#
LB#/UB#
WE#
WAIT
DQ0-DQ15
DON'T CARE
OE#
CLK
A0-A20
ADV#
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
t
CLK
t
SP
t
BOE
t
HD
t
SP
t
HD
Valid
Address
Valid
Address
High-Z
High-Z
High-Z
High-Z
UNDEFINED
D[0]
D[1]
D[2]
D[3]
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
t
SP
t
HD
t
CSP
t
HD
t
CBPH
t
ABA
t
CSP
t
SP
t
HD
t
OHZ
t
KOH
t
ACLK
t
SP
t
HD
t
SP
t
HD
TABLE 31: WRITE Timing Parameters
SYMBOL
-71
-76, -86
UNITS
SYMBOL
-71
-76, -86
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
CBPH
5
5
ns
t
CSP
4
20
4
20
ns
t
SP
3
3
ns
t
CLK
9.62
20
15
20
ns
t
HD
1
1
ns
TABLE 32: READ Timing Parameters
SYMBOL
-71
-76, -86
UNITS
SYMBOL
-71
-76, -86
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
OHZ
0
8
0
8
ns
t
CSP
4
20
4
20
ns
t
CLK
9.62
20
15
20
ns
t
BOE
20
20
ns
t
ACLK
6.5
10
ns
t
HD
1
1
ns
t
KOH
2
2
ns
t
OHZ
0
8
0
8
ns
t
ABA
33
55
ns
t
SP
3
3
ns
NanoAmp Solutions, Inc.
42
N64T1618CBA
Advance Information
This is an ADVANCE DATASHEET and subject to change without notice.
Stock No. 23250-C 7/03
Figure 36: Asynchronous WRITE Followed by Burst READ*
NOTE:1.When transitioning between asynchronous and burst operations, CE# must go HIGH. CE# must remain HIGH
for at least 5ns (
t
CBPH) to schedule the appropriate internal refresh operation.
*Non-default BCR settings: Latency Code 2 (3 clocks); WAIT active LOW; Hold Data one clock; WAIT asserted during delay.
CE#
1
LB#/UB#
WE#
WAIT
DQ0-DQ15
DON'T CARE
OE#
CLK
A0-A21
ADV#
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
t
CLK
t
BOE
Valid
Address
High-Z
High-Z
UNDEFINED
D[0]
D[1]
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
t
SP
t
HD
t
CEW
t
OHZ
t
KOH
t
ACLK
Valid Address
Valid Address
t
SP
t
HD
t
WC
t
WC
t
CKA
t
AVS
t
AVH
t
AW
t
WR
t
VP
t
CVS
t
VS
t
BW
t
SP
t
HD
t
ABA
t
CSP
t
CBPH
t
CW
t
WC
t
WPH
t
WP
t
WHZ
t
DH
t
DW
High-Z
t
VPH
TABLE 33: WRITE Timing Parameters
SYMBOL
-71
-76, -86
UNITS
SYMBOL
-71
-76, -86
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tWC
70
85
ns
tWR
0
0
ns
tWP
46
55
ns
tAVH
5
5
ns
tVP
10
10
ns
tWPH
10
10
ns
tDW
20
23
ns
tVPH
10
10
ns
tAW
70
85
ns
tBW
70
85
ns
tCKA
70
85
ns
tWHZ
0
8
0
8
ns
tVS
70
85
ns
tCW
70
85
ns
tCVS
10
10
ns
tAVS
10
10
ns
tDH
0
0
ns
TABLE 34: READ Timing Parameters
SYMBOL
-71
-76, -86
UNITS
SYMBOL
-71
-76, -86
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tCEW
1
7.5
1
7.5
ns
tBOE
20
20
ns
tOHZ
0
8
0
8
ns
tCBPH
5
5
ns
tCLK
9.62
20
15
20
ns
tSP
3
3
ns
tACLK
6.5
10
ns
tHD
1
1
ns
tKOH
2
2
ns
tCSP
4
20
4
12
ns
tABA
33
55
ns
NanoAmp Solutions, Inc.
43
N64T1618CBA
Advance Information
This is an ADVANCE DATASHEET and subject to change without notice.
Stock No. 23250-C 7/03
Figure 37: Asynchronous WRITE Followed By Burst READ - ADV# LOW*
NOTE: 1.When transitioning between asynchronous and burst operations, CE# must go HIGH. CE# must remain
HIGH for at least 5ns (
t
CBPH) to schedule the appropriate internal refresh operation.
*Non-default BCR settings: Latency Code 2 (3 clocks); WAIT active LOW; Hold Data one clock; WAIT asserted during
delay.
Note 1
t
CBPH
CE#
1
LB#/UB#
WE#
WAIT
DQ0-DQ15
DON'T CARE
OE#
CLK
A0-A21
ADV#
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
t
CLK
t
BOE
Valid
Address
High-Z
High-Z
UNDEFINED
D[0]
D[1]
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
t
SP
t
HD
t
OHZ
t
KOH
t
ACLK
Valid Address
Valid Address
t
SP
t
HD
t
WC
t
WC
t
CKA
t
WR
t
BW
t
SP
t
HD
t
ABA
t
CSP
t
CW
t
WC
t
WPH
t
WP
t
WHZ
t
DH
t
DW
High-Z
t
KP
t
AW
t
KTLH
t
SP
TABLE 35: WRITE Timing Parameters
SYMBOL
-71
-76, -86
UNITS
SYMBOL
-71
-76, -86
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tWC
70
85
ns
tWPH
10
10
ns
tWP
46
55
ns
tWHZ
0
8
0
8
ns
tCW
70
85
ns
tAW
70
85
ns
tDW
23
23
ns
tWR
0
0
ns
tCKA
70
85
ns
tDH
0
0
ns
tBW
70
85
ns
TABLE 36: READ Timing Parameters
SYMBOL
-71
-76, -86
UNITS
SYMBOL
-71
-76, -86
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tOHZ
0
8
0
8
ns
tCBPH
5
5
ns
tCLK
9.62
20
15
20
ns
tCEW
1
7.5
1
7.5
ns
tACLK
6.5
10
ns
tKP
3
3
ns
tKOH
2
2
ns
tSP
3
3
ns
tABA
33
55
ns
tHD
1
1
ns
tBOE
20
20
ns
tCSP
4
20
4
20
ns
NanoAmp Solutions, Inc.
44
N64T1618CBA
Advance Information
This is an ADVANCE DATASHEET and subject to change without notice.
Stock No. 23250-C 7/03
Figure 38: Asynchronous WRITE Followed by Asynchronous READ ADV# LOW
NOTE:1.CE# must remain HIGH for at least 5ns (
t
CBPH) to schedule the appropriate internal refresh operation.
t
CBPH
CE#
1
LB#/UB#
WE#
WAIT
DQ0-DQ15
DON'T CARE
OE#
A0-A21
ADV#
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
Valid
Address
High-Z
High-Z
UNDEFINED
DATA
DATA
VALID OUTPUT
t
OHZ
t
OLZ
Valid Address
Valid Address
t
WR
t
BW
t
CEM
t
BLZ
t
CW
t
WC
t
WPH
t
WP
t
WHZ
t
DH
t
DW
t
AW
t
HZ
t
AA
t
S
t
BHZ
t
LZ
t
OE
TABLE 37: WRITE Timing Parameters
SYMBOL
-71
-76, -86
UNITS
SYMBOL
-71
-76, -86
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
WC
70
85
ns
t
DH
0
0
ns
t
WP
46
55
ns
t
WPH
10
10
ns
t
CW
70
85
ns
t
WHZ
0
8
0
8
ns
t
DW
23
23
ns
t
AW
70
85
ns
t
BW
70
85
ns
t
WR
0
0
ns
TABLE 38: READ Timing Parameters
SYMBOL
-71
-76, -86
UNITS
SYMBOL
-71
-76, -86
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
AA
70
85
ns
t
BHZ
0
8
0
8
ns
t
S
10
10
s
t
OHZ
0
8
0
8
ns
t
CBPH
5
5
ns
t
LZ
10
10
ns
t
OE
20
20
ns
t
BLZ
10
10
ns
t
HZ
0
8
0
8
ns
t
OLZ
5
5
ns
t
CEM
10
10
s
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Stock No. 23250-C 7/03
Figure 39: Asynchronous WRITE Followed by Asynchronous READ
NOTE: 1.CE# must remain HIGH for at least 5ns (
t
CBPH) to schedule the appropriate internal refresh operation.
t
CBPH
CE#
1
LB#/UB#
WE#
WAIT
DQ0-DQ15
DON'T CARE
OE#
A0-A21
ADV#
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
Valid
Address
High-Z
High-Z
UNDEFINED
DATA
VALID OUTPUT
t
OHZ
t
OE
Valid Address
Valid Address
t
WR
t
BW
t
CEM
t
BLZ
t
CW
t
WC
t
WPH
t
WP
t
WHZ
t
DH
t
DW
t
AW
t
HZ
t
AA
t
S
t
BHZ
t
LZ
t
AVS
t
AVH
t
VS
t
VP
t
CVS
t
VPH
DATA
TABLE 39: WRITE Timing Parameters
SYMBOL
-71
-76, -86
UNITS
SYMBOL
-71
-76, -86
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tWC
70
85
ns
tWHZ
0
8
0
8
ns
tWP
46
55
ns
tAVH
5
5
ns
tCW
70
85
ns
tCVS
10
10
ns
tDW
23
23
ns
tWPH
10
10
ns
tAW
70
85
ns
tVPH
10
10
ns
tVS
70
85
ns
tVP
10
10
ns
tAVS
10
10
ns
tDH
0
0
ns
tWR
0
0
ns
tBW
70
85
ns
TABLE 40: READ Timing Parameters
SYMBOL
-71
-76, -86
UNITS
SYMBOL
-71
-76, -86
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
AA
70
85
ns
t
BHZ
0
8
0
8
ns
t
S
10
10
s
t
OHZ
0
8
0
8
ns
t
CBPH
5
5
ns
t
LZ
10
10
ns
t
OE
20
20
ns
t
BLZ
10
10
ns
t
HZ
0
8
0
8
ns
t
OLZ
5
5
ns
t
CEM
10
10
s
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Advance Information
This is an ADVANCE DATASHEET and subject to change without notice.
Stock No. 23250-C 7/03
54-Ball FBGA Package Dimensions
NOTE: 1. All dimensions in millimeters MAX/MIN, or typical, as noted.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side
.
Symbol
Description
Min
Nom
Max
A
Package Width
5.90
6.00
6.10
B
Package Length
7.90
8.00
8.10
C
Overall Package Height
1.00
D
Ball Width
0.35
E
Ball Pitch
0.75
F
Package Height
0.625
0.700
0.775
SIDE VIEW
TOP VIEW
BOTTOM VIEW
B
A
Ball A1
C
E
E
D
F
ID
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This is an ADVANCE DATASHEET and subject to change without notice.
Stock No. 23250-C 7/03
Application Note For Extended Timings and Impact on Operation
Introduction
This note describes timing requirements in sys-
tems that perform extended operations. The
N64T1618CBA product uses a DRAM technology
that periodically requires refresh to insure against
data corruption. The device includes on-chip cir-
cuitry that performs the required refresh in a man-
ner that is completely transparent in systems with
normal bus timings. The refresh circuitry imposes
constraints on timings in systems that take longer
than 10s to complete an operation. WRITE opera-
tions are affected if the device is configured for
asynchronous operation. Both READ and WRITE
operations are affected if the device is configured
for burst mode operation.
Asynchronous & Page Mode Operation
The N64T1618CBA product requires that asyn-
chronous WRITE operations must be completed
within 10s. After completing an operation, the
device must either enter standby (by transitioning
CE# HIGH) or else perform a second operation
using a new address. Figures 1a and 1b demon-
strate these constraints as they apply during an
asynchronous (page-mode-disabled) operation.
Either the CE# active period (
t
CEM in Figure 1a) or
the address valid period (
t
TM in Figure 1b) must be
less than 10s during any operation to accommo-
date orderly scheduling of refresh.
Figures 1a & 1b
When a device is configured for page-ode opera-
tion, the address inputs are used to accelerate
read accesses and cannot be used by the on-chip
circuitry to schedule refresh. CE# must return
HIGH upon completion of all WRITE operations
when page mode is enabled (Figure 2). The total
time taken for a WRITE operation should not
exceed 10s to accommodate orderly scheduling
of refresh.
Figure 2
Modified timings are only required during extended
WRITE operations (see Figure 3). An extended
WRITE operation requires that both the WRITE
pulse width (
t
WP) and the data valid period (
t
DW)
will need to be lengthened to at least the minimum
WRITE cycle time (
t
WC (min)). These increased
timings insure that time is available for both a
refresh and a successful completion of the WRITE
operation.
Figure 3
t
CEM
<10 s
t
TM
<10 s
CE#
ADDRESS
CE#
ADDRESS
Timing Constraint When Page Mode is Disabled
t
CEM
<10 s
CE#
Timing Constraint When Page Mode is Enabled
t
CEM
or t
TM
>10 s
ADDRESS
CE#
LB#/UB#
WE#
DATA IN
t
WP
<t
WC
(min)
t
DW
<t
WC
(min)
Extended Asynchronous Write Operation
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Burst Mode Operation
When configured for burst-mode operation, it is
necessary to allow the device to perform a refresh
within any 10s window. One of two conditions will
allow the device to schedule a refresh within 10s.
The first condition is simply to complete all burst
operation within 10s. The burst completes when
the CE# signal is registered HIGH on a positive
(BCR[6] = 1) or negative (BCR[6]=0) clock edge.
The second condition that allows for refresh is a
burst access that crosses a row boundary. The
row-boundary crossing causes WAIT to be
asserted while the next row is accessed and also
allows for the scheduling of refresh.
Summary
The N64T1618CBA is designed to ensure that any
possible asynchronous timings do not cause data
corruption due to lack of refresh. Slow bus timings
will only affect asynchronous WRITE operations
(READs are unaffected). The impact on asynchro-
nous WRITE operations is that some of the timing
parameters (
t
WP and
t
DW) are lengthened. Burst
mode timings must allow the device to perform a
refresh within any 10s period. A burst operation
must either complete (CE# registered HIGH) or
cross a row boundary within 10s to ensure suc-
cessful refresh scheduling. These timing require-
ments are likely to have little or no impact when
interfacing devices to a low-speed memory bus.
2003 Nanoamp Solutions, Inc. All rights reserved.
NanoAmp Solutions, Inc. ("NanoAmp") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice.
NanoAmp does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration pur-
poses only and they vary depending upon specific applications.
NanoAmp makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does NanoAmp assume any liability arising out of the application
or use of any product or circuit described herein. NanoAmp does not authorize use of its products as critical components in any application in which the failure of the NanoAmp
product may be expected to result in significant injury or death, including life support systems and critical medical instruments.
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