NT1GD72S4NB0FU
1GB : 128M x 72
Low Profile Registered DDR SDRAM DIMM
184pin Low Profile Registered DDR SDRAM MODULE
Based on 64Mx4 DDR SDRAM
Features
128Mx72 Low Profile Registered DDR DIMM based on 64Mx4
DDR SDRAM
JEDEC Standard 184-pin Dual In-Line Memory Module
Error Check Correction (ECC) Support
Phase-lock loop (PLL) clock driver to reduce loading
Registered inputs with one-clock delay
Performance:
PC2100
Speed Sort
-75B
DIMM
CAS
Latency
*
3.5
Unit
f
CK
Clock Frequency
133
MHz
t
CK
Clock Cycle
7.5
ns
f
DQ
DQ Burst Frequency
266
MHz
Intended for 133 MHz applications
Inputs and outputs are SSTL-2 compatible
V
DD
= 2.5Volt
0.2, V
DDQ
= 2.5Volt 0.2
SDRAMs have 4 internal banks for concurrent operation
Differential clock inputs
Data is read or written on both clock edges
Bi-directional data strobe with one clock cycle preamble and
one-half clock post-amble
Address and control signals are fully synchronous to positive
clock edge
Programmable Operation:
- Device
CAS
Latency: 2, 2.5
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
Auto Refresh (CBR) and Self Refresh Modes
Automatic and controlled precharge commands
13/11/2 Addressing (row/column/bank)
7.8 s Max. Average Periodic Refresh Interval
Serial Presence Detect
Gold contacts
SDRAMs in 60-ball FBGA Package
*
One clock cycle added for registered DIMMs to account for input register.
D
escription
NT1GD72S4NB0FU is a Low Profile Registered 184-Pin 1U Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module
(DIMM), organized as a dual-bank 128Mx72 high-speed memory array. The module uses 36 64Mx4 DDR SDRAMs in BGA packages.
These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common
design files minimizes electrical variation between suppliers. All NANYA DDR SDRAM DIMMs provide a high-performance, flexible 8-byte
interface in a 5.25" long space-saving footprint.
The DIMM is intended for use in applications operating up to 133 MHz clock speeds and achieves high-speed data transfer rates of up to
266 MHz. Prior to any access operation, the device
CAS
latency and burst type/ length/operation type must be programmed into the
DIMM by address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of
serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
O
rdering Information
Part Number
Speed Organization
Leads
Power
133MHz (7.5ns @ CL= 2.5)
NT1GD72S4NB0FU-75B
100MHz (10ns @ CL = 2)
DDR266B
PC2100 128Mx72 Gold 2.5V
REV 0.2 (Preliminary)
1
05/2003
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT1GD72S4NB0FU
1GB : 128M x 72
Low Profile Registered DDR SDRAM DIMM
Pin Description
CK0,
CK0
Differential Clock Inputs
DQ0-DQ63
Data input/output
CKE0, CKE1
Clock Enable
CB0-CB7
Check Bit Data Input/Output
RAS
Row Address Strobe
DQS0-DQS17
Bidirectional data strobes
CAS
Column Address Strobe
V
DD
Power
(2.5V)
WE
Write Enable
V
DDQ
Supply voltage for DQs (2.5V)
S0
,
S1
Chip
Selects
V
SS
Ground
A0-A9, A11, A12 Address Inputs
NC
No Connect
A10/AP Address
Input/Autoprecharge
SCL
Serial Presence Detect Clock Input
BA0, BA1
SDRAM Bank Address Inputs
SDA
Serial Presence Detect Data input/output
RESET
Reset pin
SA0-2
Serial Presence Detect Address Inputs
V
REF
Ref. Voltage for SSTL_2 inputs
V
DDID
V
DD
Identification flag.
V
DDSPD
Serial EEPROM positive power supply
(2.5V)
P
inout
Pin Front Pin Front Pin Front Pin
Back Pin
Back Pin Back
1 V
REF
32 A5 62 V
DDQ
93 V
SS
124
V
SS
154
RAS
2 DQ0 33 DQ24
63
WE
94 DQ4 125
A6 155 DQ45
3 V
SS
34 V
SS
64 DQ41 95 DQ5 126
DQ28 156 V
DDQ
4 DQ1 35 DQ25
65
CAS
96 V
DDQ
127
DQ29 157
S0
5 DQS0 36 DQS3 66 V
SS
97 DQS9
128
V
DDQ
158
S1
6
DQ2 37
A4
67 DQS5 98 DQ6 129
DQS12 159 DQS14
7 V
DD
38 V
DD
68 DQ42 99 DQ7 130
A3 160 V
SS
8 DQ3 39 DQ26
69 DQ43
100
V
SS
131
DQ30 161 DQ46
9 NC 40
DQ27
70 V
DD
101
NC 132
V
SS
162 DQ47
10
RESET
41 A2 71 NC 102
NC 133
DQ31
163 NC
11 V
SS
42 V
SS
72 DQ48
103
NC 134
CB4 164
V
DDQ
12 DQ8 43 A1 73 DQ49
104
V
DDQ
135
CB5 165 DQ52
13 DQ9 44 CB0 74 V
SS
105
DQ12 136
V
DDQ
166 DQ53
14 DQS1 45 CB1 75 NC 106
DQ13 137
CK0 167 NC
15 V
DDQ
46 V
DD
76 NC 107
DQS10
138
CK0
168 V
DD
16 NC 47
DQS8
77 V
DDQ
108
V
DD
139
V
SS
169
DQS15
17 NC 48 A0 78
DQS6
109
DQ14
140
DQS17
170
DQ54
18 V
SS
49 CB2 79 DQ50 110
DQ15 141
A10 171 DQ55
19 DQ10 50 V
SS
80 DQ51 111
CKE1 142
CB6 172 V
DDQ
20 DQ11 51 CB3 81 V
SS
112
V
DDQ
143
V
DDQ
173 NC
21 CKE0 52 BA1 82 V
DDID
113
NC 144
CB7 174 DQ60
22 V
DDQ
KEY
83
DQ56
114
DQ20 KEY
175
DQ61
23 DQ16 53 DQ32 84 DQ57 115
A12 145
V
SS
176 V
SS
24 DQ17 54 V
DDQ
85 V
DD
116
V
SS
146
DQ36 177
DQS16
25 DQS2 55 DQ33 86 DQS7 117
DQ21 147
DQ37 178 DQ62
26 V
SS
56 DQS4 87 DQ58
118
A11 148
V
DD
179 DQ63
27
A9
57 DQ34 88 DQ59 119
DQS11 149
DQS13 180 V
DDQ
28 DQ18 58 V
SS
89 V
SS
120
V
DD
150
DQ38 181 SA0
29 A7 59 BA0 90 NC 121
DQ22 151
DQ39 182 SA1
30 V
DDQ
60 DQ35 91 SDA 122
A8 152
V
SS
183 SA2
31 DQ19 61 DQ40 92 SCL 123
DQ23 153
DQ44 184
V
DDSPD
REV 0.2 (Preliminary)
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05/2003
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT1GD72S4NB0FU
1GB : 128M x 72
Low Profile Registered DDR SDRAM DIMM
Input/Output Functional Description
Symbol
Type
Polarity
Function
CK0
(SSTL)
Positive
Edge
The positive line of the differential pair of system clock inputs which drives the input to
the on-DIMM PLL. All the DDR SDRAM address and control inputs are sampled on the
rising edge of their associated clocks.
CK0
(SSTL)
Negative
Edge
The negative line of the differential pair of system clock inputs which drives the input to
the on-DIMM PLL.
CKE0, CKE1
(SSTL)
Active
High
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode.
S0
,
S1
(SSTL)
Active
Low
Enables the associated SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue.
RAS
,
CAS
,
WE
(SSTL)
Active
Low
When sampled at the positive rising edge of the clock,
RAS
,
CAS
,
WE
define the
operation to be executed by the SDRAM.
V
REF
Supply
Reference voltage for SSTL-2 inputs
V
DDQ
Supply
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
BA0, BA1
(SSTL) -
Selects which SDRAM bank is to be active.
A0 - A9
A10/AP
A11, A12
(SSTL) -
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9, A11 defines the column address
(CA0-CA10) when sampled at the rising clock edge. In addition to the column address,
AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write
cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be
precharged. If AP is low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to
pre-charge.
DQ0 - DQ63
(SSTL) -
Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.
DQ0 DQ63
CB0 CB7
(SSTL)
Active
High
Data and Check Bit Input/Output pins. Check bits are only applicable on the x72 DIMM
configurations.
V
DD,
V
SS
Supply
Power and ground for the DDR SDRAM input buffers and core logic
DQS0 DQS17
(SSTL)
Negative
and
Positive
Edge
Data strobe for input and output data
RESET
(LVC-MOS)
Active
Low
SA0 SA2
-
Address inputs. Connected to either V
DD
or V
SS
on the system board to configure the
Serial Presence Detect EEPROM address.
SDA
-
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
DD
to act as a pullup.
SCL
-
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V
DD
to act as a pullup.
V
DDSPD
Supply
Serial EEPROM positive power supply.
REV 0.2 (Preliminary)
3
05/2003
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT1GD72S4NB0FU
1GB : 128M x 72
Low Profile Registered DDR SDRAM DIMM
Functional Block Diagram
(2 Bank, 64Mx4 DDR SDRAMs)
REV 0.2 (Preliminary)
4
05/2003
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT1GD72S4NB0FU
1GB : 128M x 72
Low Profile Registered DDR SDRAM DIMM
Serial Presence Detect --
Part 1 of 2
128Mx72 2 BANK REGISTERED DDR SDRAM DIMM based on 64Mx4, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
Note
Byte Description
DDR266
-75B
DDR266
-75B
0
Number of Serial PD Bytes Written during Production
128
80
1
Total Number of Bytes in Serial PD device
256
08
2
Fundamental Memory Type
SDRAM DDR
07
3
Number of Row Addresses on Assembly
13
0D
4
Number of Column Addresses on Assembly
11
0B
5
Number of DIMM Bank
2
02
6
Data Width of Assembly
X72
48
7
Data Width of Assembly (cont')
X72
00
8
Voltage Interface Level of this Assembly
SSTL 2.5V
04
9
DDR SDRAM Device Cycle Time at CL=2.5
7.5ns
75
10
DDR SDRAM Device Access Time from Clock at CL=2.5
0.75ns
75
11
DIMM Configuration Type
ECC
02
12 Refresh
Rate/Type
SR/1x(7.8us)
82
13
Primary DDR SDRAM Width
X4
04
14
Error Checking DDR SDRAM Device Width
X4
04
15
DDR SDRAM Device Attr: Min CLK Delay, Random Col
Access
1 Clock
01
16
DDR SDRAM Device Attributes: Burst Length Supported
2,4,8
0E
17
DDR SDRAM Device Attributes: Number of Device Banks
4
04
18
DDR SDRAM Device Attributes: CAS Latencies Supported
2/2.5
0C
19
DDR SDRAM Device Attributes: CS Latency
0
01
20
DDR SDRAM Device Attributes: WE Latency
1
02
21
DDR SDRAM Device Attributes:
Differential Clock, PLL,
REGISTER
26
22
DDR SDRAM Device Attributes: General
+/-0.2V Voltage Tolerance
00
23
Minimum Clock Cycle at CL=2
10ns
A0
24
Maximum Data Access Time from Clock at CL=2
0.75ns
75
25
Minimum Clock Cycle Time at CL=1
N/A
00
26
Maximum Data Access Time from Clock at CL=1
N/A
00
27
Minimum Row Precharge Time (t
RP
) 20ns
50
28
Minimum Row Active to Row Active delay (t
RRD
) 15ns
3C
29
Minimum RAS to CAS delay (t
RCD
) 20ns
50
30
Minimum RAS Pulse Width (t
RAS
) 45ns
2D
31
Module Bank Density
512MB
80
32
Address and Command Setup Time Before Clock
0.9ns
90
33
Address and Command Hold Time After Clock
0.9ns
90
34
Data Input Setup Time Before Clock
0.5ns
50
35
Data Input Hold Time After Clock
0.5ns
50
36-61 Reserved
Undefined
00
62 SPD
Revision
Initial
00
63 Checksum
Data
11
REV 0.2 (Preliminary)
5
05/2003
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT1GD72S4NB0FU
1GB : 128M x 72
Low Profile Registered DDR SDRAM DIMM
Serial Presence Detect --
Part 2 of 2
128Mx72 2 BANK REGISTERED DDR SDRAM DIMM based on 64Mx4, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
Byte Description
DDR266
-75B
DDR266
-75B
Note
64-71 Manufacturer's JEDEC ID Code
NANYA
7F7F7F0B00000000
72
Module Manufacturing Location
N/A
00
73-90 Module Part number
N/A
00
91-92 Module
Revision
Code
N/A
00
93-94 Module Manufacturing Data
Year/Week Code
yy/ww
1, 2
95-98 Module Serial Number
Serial Number
00
99-255 Reserved
Undefined
00
yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex)
ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex)
REV 0.2 (Preliminary)
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05/2003
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT1GD72S4NB0FU
1GB : 128M x 72
Low Profile Registered DDR SDRAM DIMM
Absolute Maximum Ratings
Symbol Parameter
Rating
Units
V
IN
, V
OUT
Voltage on I/O pins relative to Vss
-0.5 to V
DDQ
+0.5 V
V
IN
Voltage on Input relative to Vss
-0.5 to +2.7
V
V
DD
Voltage on VDD supply relative to Vss
-0.5 to +2.7
V
V
DDQ
Voltage on VDDQ supply relative to Vss
-0.5 to +2.7
V
T
A
Operating Temperature (Ambient)
0 to +70
C
T
STG
Storage Temperature (Plastic)
-55 to +150
C
P
D
Power Dissipation
36 W
I
OUT
Short Circuit Output Current
50 mA
Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Capacitance
Parameter Symbol
Max.
Units
Notes
Input Capacitance: CK0,
CK0
C
I1
TBD pF 1
Input Capacitance: A0-A12, BA0, BA1,
WE
,
RAS
,
CAS
,
CKE0,
S0
C
I2
TBD pF 1
Input Capacitance:
RESET
C
I3
TBD pF 1
Input Capacitance: SA0-SA2, SCL
C
I4
TBD pF 1
Input/Output Capacitance DQ0-63; DQS0-17, CB0-7
C
IO1
TBD pF 1,
2
Input/Output Capacitance: SDA
C
IO3
TBD pF
1. V
DDQ
= V
DD
= 2.5V 0.2V, f = 100 MHz, T
A
= 25 C, V
OUT
(DC) = V
DDQ
/2, V
OUT
(Peak to Peak) = 0.2V.
2.
DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching
at the board level.
REV 0.2 (Preliminary)
7
05/2003
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT1GD72S4NB0FU
1GB : 128M x 72
Low Profile Registered DDR SDRAM DIMM
DC Electrical Characteristics and Operating Conditions
(TA = 0 C ~ 70 C; V
DDQ
= 2.5V 0.2V; V
DD
= 2.5V 0.2V, See AC Characteristics)
Symbol Parameter Min
Max
Units
Notes
V
DD
Supply
Voltage
2.3
2.7
V
1
V
DDQ
I/O Supply Voltage
2.3
2.7
V
1
V
SS,
V
SSQ
Supply Voltage, I/O Supply Voltage
0
0
V
V
REF
I/O Reference Voltage
0.49 x
V
DDQ
0.51 x
V
DDQ
V 1,
2
V
TT
I/O Termination Voltage (System)
V
REF
- 0.04
V
REF
+ 0.04
V
1, 3
V
IH (DC)
Input High (Logic1) Voltage
V
REF
+ 0.15
V
DDQ
+ 0.3
V
1
V
IL (DC)
Input Low (Logic0) Voltage
-0.3
V
REF
- 0.15
V
1
V
IN (DC)
Input Voltage Level, CK and
CK
Inputs
-0.3
V
DDQ
+ 0.3
V
1
V
ID (DC)
Input Differential Voltage, CK and
CK
Inputs
0.30
V
DDQ
+ 0.6
V
1, 4
I
I
Input Leakage Current
Any input 0V
V
IN
V
DD;
(All other pins not under test = 0V)
-5 5
uA
1
I
OZ
Output Leakage Current
(DQs are disabled; 0V
V
out
V
DDQ
-5 5
uA
1
I
OH
Output High Current
(V
OUT =
V
DDQ
-0.373V, min V
REF,
min V
TT)
-16.8 -
mA
1
I
OL
Output Low Current
(V
OUT
= 0.373, max V
REF,
max V
TT)
16.8 -
mA
1
1.
Inputs are not recognized as valid until V
REF
stabilizes.
2. V
REF
is expected to be equal to 0.5 V
DDQ
of the transmitting device, and to track variations in the DC level of the same.
Peak-to-peak noise on V
REF
may not exceed 2% of the DC value.
3. V
TT
is not applied directly to the DIMM. V
TT
is a system supply for signal termination resistors, is expected to be set equal to V
REF,
and must track variations in the DC level of V
REF
.
4. V
ID
is the magnitude of the difference between the input level on CK and the input level on
CK
.
REV 0.2 (Preliminary)
8
05/2003
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT1GD72S4NB0FU
1GB : 128M x 72
Low Profile Registered DDR SDRAM DIMM
AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, Operating,
Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.)
1. All voltages referenced to V
SS
.
2. Tests for AC timing, I
DD
, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but
the related specifications and device operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.
4. AC timing and I
DD
tests may use a V
IL
to V
IH
swing of up to 1.5V in the test environment, but input timing is still referenced to V
REF
(or
to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use
conditions. The minimum slew rate for the input signals is 1V/ns in the range between V
IL (AC)
and V
IH (AC)
unless otherwise specified.
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the
signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW
(HIGH) level.
AC Output Load Circuits
Timing Reference Point
V
TT
50 ohms
30 pF
Output
V
OUT
AC Operating Conditions
(TA = 0 C ~ 70 C; V
DDQ
= 2.5V 0.2V; V
DD
= 2.5V 0.2V, See AC Characteristics)
Symbol
Parameter/Condition
Min
Max
Unit
Notes
V
IH (AC)
Input High (Logic 1) Voltage
V
REF
+ 0.31 - V
1, 2
V
IL (AC)
Input Low (Logic 0) Voltage -
V
REF
- 0.31
V
1, 2
V
ID (AC)
Input Differential Voltage, CK and
CK
Inputs
0.7
V
DDQ
+ 0.6
V
1, 2, 3
V
IX (AC)
Input Differential Pair Cross Point Voltage, CK and
CK
Inputs
0.5 x V
DDQ
- 0.2
0.5 x V
DDQ
+ 0.2
V
1, 2, 4
1.
Input slew rate = 1V/ ns.
2.
Inputs are not recognized as valid until V
REF
stabilizes.
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on
CK
.
4.
The value of V
IX
is expected to equal 0.5 x V
DDQ
of the transmitting device and must track variations in the DC level of the same.
REV 0.2 (Preliminary)
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05/2003
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT1GD72S4NB0FU
1GB : 128M x 72
Low Profile Registered DDR SDRAM DIMM
Operating, Standby, and Refresh Currents
(TA = 0 C ~ 70 C; V
DDQ
= 2.5V 0.2V; V
DD
= 2.5V 0.2V, See AC Characteristics)
Symbol
Parameter/Condition
PC2100
(-75B)
Unit
Notes
I
DD0
Operating Current: one bank; active/precharge; t
RC
= t
RC (MIN);
t
CK
= t
CK
(MIN);
DQ, DM, and DQS inputs changing twice per clock cycle; address
and control inputs changing once per clock cycle
TBD mA
1,
2
I
DD1
Operating Current: one bank; active/read/precharge; Burst = 2; t
RC
= t
RC
(MIN);
CL=2.5; t
CK
= t
CK (MIN);
I
OUT
= 0mA; address and control inputs
changing once per clock cycle
TBD mA
1,
2
I
DD2P
Precharge Power-Down Standby Current: all banks idle; power-down
mode; CKE
V
IL (MAX);
t
CK
= t
CK (MIN)
TBD mA
1,
2
I
DD2N
Idle Standby Current: CS
V
IH (MIN);
all banks idle; CKE
V
IH (MIN)
; t
CK
=
t
CK (MIN);
address and control inputs changing once per clock cycle
TBD mA
1,
2
I
DD3P
Active Power-Down Standby Current: one bank active; power-down mode;
CKE
V
IL (MAX);
t
CK
= t
CK (MIN)
TBD mA
1,
2
I
DD3N
Active Standby Current: one bank; active/precharge; CS
V
IH (MIN);
CKE
V
IH (MIN);
t
RC
= t
RAS (MAX)
; t
CK
= t
CK (MIN)
; DQ, DM, and DQS inputs
changing twice per clock cycle; address and control inputs changing once
per clock cycle
TBD mA
1,
2
I
DD4R
Operating Current: one bank; Burst = 2; reads; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS outputs
changing twice per clock cycle; CL = 2.5; t
CK
= t
CK (MIN);
I
OUT
= 0mA
TBD mA
1,
2
I
DD4W
Operating Current: one bank; Burst = 2; writes; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS inputs
changing twice per clock cycle; CL=2.5; t
CK
= t
CK (MIN)
TBD mA
1,
2
I
DD5
Auto-Refresh Current: t
RC
= t
RFC (MIN)
TBD
mA
1, 2, 4
I
DD6
Self-Refresh Current: CKE
0.2V
TBD mA
1,
2
I
DD7
Operating Current: four bank; four bank interleaving with BL = 4, address
and control inputs randomly changing; 50% of data changing at every
transfer; t
RC
= t
RC
(min); I
OUT
= 0mA.
TBD mA
1,
2
1. I
DD
specifications are tested after the device is properly initialized.
2.
Input slew rate = 1V/ ns.
3.
Enables on-chip refresh and address counters.
4.
Current at 7.8 s is time-averaged value of I
DD5
at t
RFC (MIN)
and I
DD2P
over 7.8 s.
REV 0.2 (Preliminary)
10
05/2003
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT1GD72S4NB0FU
1GB : 128M x 72
Low Profile Registered DDR SDRAM DIMM
AC Timing Specifications for DDR SDRAM Devices Used on Module
(TA = 0 C ~ 70 C; V
DDQ
= 2.5V 0.2V; V
DD
= 2.5V 0.2V, See AC Characteristics) (Part 1 of 2)
-75B
Symbol Parameter
Min. Max.
Unit
Notes
t
AC
DQ output access time from CK/
CK
-0.75
+0.75
ns
1-4
t
DQSCK
DQS output access time from CK/
CK
-0.75
+0.75
ns
1-4
t
CH
CK high-level width
0.45
0.55
t
CK
1-4
t
CL
CK low-level width
0.45
0.55
t
CK
1-4
t
CK
CL=2.5
7.5
12
ns
1-4
t
CK
Clock cycle time
CL=2 10
12
ns
1-4
t
DH
DQ and DM input hold time
0.5
ns
1-4, 15,
16
t
DS
DQ and DM input setup time
0.5
ns
1-4, 15,
16
t
DIPW
DQ and DM input pulse width (each input)
1.75
ns
1-4
t
HZ
Data-out high-impedance time from CK/
CK
-0.75
+0.75
ns
1-4,
5
t
LZ
Data-out low-impedance time from CK/
CK
-0.75
+0.75
ns
1-4,
5
t
DQSQ
DQS-DQ skew (DQS & associated DQ signals)
0.5
ns
1-4
t
HP
Minimum half clk period for any given cycle;
defined by clk high (t
CH)
or clk low (t
CL
) time
t
CH
or
t
CL
t
CK
1-4
t
QH
Data output hold time from DQS
t
HP
-
t
QHS
t
CK
1-4
t
QHS
Data hold Skew Factor
0.75ns
t
CK
1-4
t
DQSS
Write command to 1st DQS latching transition
0.75
1.25
t
CK
1-4
t
DQSL,H
DQS input low (high) pulse width
(write cycle)
0.35
t
CK
1-4
t
DSS
DQS falling edge to CK setup time
(write cycle)
0.2
t
CK
1-4
t
DSH
DQS falling edge hold time from CK
(write cycle)
0.2
t
CK
1-4
t
MRD
Mode register set command cycle time
2
t
CK
1-4
t
WPRES
Write preamble setup time
0
ns
1-4, 7
t
WPST
Write
postamble
0.40
0.60
t
CK
1-4,
6
t
WPRE
Write
preamble
0.25
t
CK
1-4
t
IH
Address and control input hold time
(fast slew rate)
0.9
ns
2-4, 9,
11, 12
t
IS
Address and control input setup time
(fast slew rate)
0.9
ns
2-4, 9,
11, 12
t
IH
Address and control input hold time
(slow slew rate)
1.0
ns
2-4, 10,
11, 12,
14
REV 0.2 (Preliminary)
11
05/2003
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT1GD72S4NB0FU
1GB : 128M x 72
Low Profile Registered DDR SDRAM DIMM
AC Timing Specifications for DDR SDRAM Devices Used on Module
(TA = 0 C ~ 70 C; V
DDQ
= 2.5V 0.2V; V
DD
= 2.5V 0.2V, See AC Characteristics) (Part 2 of 2)
-75B
Symbol Parameter
Min. Max.
Unit
Notes
t
IS
Address and control input setup time
(slow slewrate)
1.0
ns
2-4,
10-12, 14
t
IPW
Input pulse width
2.2
ns
2-4, 12
t
RPRE
Read
preamble
0.9
1.1
t
CK
1-4
t
RPST
Read
postamble
0.40
0.60
t
CK
1-4
t
RAS
Active to Precharge command
45
120,000
ns
1-4
t
RC
Active to Active/Auto-refresh command period
65
ns
1-4
t
RFC
Auto-refresh to Active/Auto-refresh command
period
75
ns
1-4
t
RCD
Active to Read or Write delay
20
ns
1-4
t
RAP
Active to Read Command with Autoprecharge
20
ns
1-4
t
RP
Precharge command period
20
ns
1-4
t
RRD
Active bank A to Active bank B command
15
ns
1-4
t
WR
Write recovery time
15
ns
1-4
t
DAL
Auto precharge write recovery + precharge time
(t
WR
/t
CK
) +
(t
RP
/t
CK
)
t
CK
1-4,
13
t
WTR
Internal write to read command delay
1
t
CK
1-4
t
PDEX
Power down exit time
7.5
ns
1-4
t
XSNR
Exit self-refresh to non-read command
75
ns
1-4
t
XSRD
Exit self-refresh to read command
200
t
CK
1-4
t
REFI
Average Periodic Refresh Interval
7.8
s 1-4,
8
REV 0.2 (Preliminary)
12
05/2003
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT1GD72S4NB0FU
1GB : 128M x 72
Low Profile Registered DDR SDRAM DIMM
AC Timing Specification Notes
1. Input slew rate = 1V/ns.
2. The CK/
CK
input reference level (for timing reference to CK/CK) is the point at which CK and
CK
cross: the input reference level for
signals other than CK/
CK
is V
REF
.
3. Inputs are not recognized as valid until V
REF
stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V
TT.
5. t
HZ
and t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a
specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid
transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in
progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW,
or transitioning from high to low at this time, depending on tDQSS.
8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device.
9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between V
OH
(AC) and V
OL
(AC).
10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between V
OH
(AC) and V
OL
(AC).
11. CK/
CK
slew rates are >= 1.0 V/ns.
12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by
design or tester characterization.
13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t CK is equal to the actual system
clock cycle time. For example, for PC2100 at CL= 2.5, t DAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5.
14. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew rate is below 0.5 V/ns.
Input Slew Rate
Delta (tIS
)
Delta
(tIH
)
Unit
Note
0.5 V/ns
0
0
ps
1, 2
0.4 V/ns
+50
0
ps
1, 2
0.3 V/ns
+100
0
ps
1, 2
1.
Input slew rate is based on the lesser of the slew rates determined by either V
IH (AC)
to V
IL (AC)
or V
IH (DC)
to V
IL (DC),
similarly for
rising transitions.
2.
These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
15. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below 0.5 V/ns.
Input Slew Rate
Delta (tDS
)
Delta
(tDH
)
Unit
Note
0.5 V/ns
0
0
ps
1, 2
0.4 V/ns
+75
+75
ps
1, 2
0.3 V/ns
+150
+150
ps
1, 2
1.
I/O slew rate is based on the lesser of the slew rates determined by either V
IH (AC)
to V
IL (AC)
or V
IH (DC)
to V
IL (DC),
similarly for
rising transitions.
2.
These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
16. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH in the case where DQ, DM, and DQS slew rates differ.
Delta Rise and Fall Rate
Delta (tDS
)
Delta
(tDH
)
Unit
Note
0.0 ns/V
0
0
ps
1-4
0.25 ns/V
+50
+50
ps
1-4
0.5 ns/V
+100
+100
ps
1-4
1.
Input slew rate is based on the lesser of the slew rates determined by either V
IH (AC)
to V
IL (AC)
or V
IH (DC)
to V
IL (DC),
similarly for
rising transitions.
2.
Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.
3.
The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]
For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V
Using the table above, this would result in an increase in t
DS
and t
DH
of 100 ps.
4.
These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
REV 0.2 (Preliminary)
13
05/2003
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT1GD72S4NB0FU
1GB : 128M x 72
Low Profile Registered DDR SDRAM DIMM
Package Dimensions
FRONT
1.80
Detail A
0.050
Detail B
1.00 Width
BACK
0.071
3.
8
0
0.
1
5
0
.
157
4.
0
0
0.039
1.27 Pitch
SIDE
3.99
(Front)
4.50
1.27
0.157 max.
0.177
0.050
Detail A
Detail B
0.098
2.5
10.0
0.394
133.35
131.35
128.95
5.250
5.171
5.077
Register
17.80
2.3
0.091
0.700
30.48
1.200
(2X
)
4.00
0.157
Register
PLL
Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated.
Units: Millimeters (Inches)
REV 0.2 (Preliminary)
14
05/2003
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT1GD72S4NB0FU
1GB : 128M x 72
Low Profile Registered DDR SDRAM DIMM
REV 0.2 (Preliminary)
15
05/2003
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Revision Log
Rev Date
Modification
0.1 04/2003
Preliminary
Release
0.2
05/2003
Updated Functional Block Diagram
PDF 
ZIP