NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM

Preliminary

08 / 2001

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

184pin One Bank Unbuffered DDR SDRAM MODULE

Based on DDR266/200 32Mx8 SDRAM

Features

184-Pin Unbuffered 8-Byte Dual In-Line Memory Module

· 32Mx64 Double Data Rate (DDR) SDRAM DIMM
· Performance :

PC1600

PC2100

Speed Sort

- 8B

- 75B

- 7K

DIMM CAS Latency

2.5

Unit

Clock Frequency

100

133

MHz

Clock Cycle

7.5

DQ Burst Frequency

200

266

MHz

· Intended for 100 MHz and 133 MHz applications

· Inputs and outputs are SSTL-2 compatible
· V

= 2.5Volt ±

0.2, V

DDQ

= 2.5Volt ± 0.2

· Single Pulsed RAS interface
· SDRAMs have 4 internal banks for concurrent operation
· Module has one physical bank

· Differential clock inputs
· Data is read or written on both clock edges

· DRAM D

aligns DQ and DQS transitions with clock transitions.

Also aligns QFC transitions with clock during Read cycles

· Address and control signals are fully synchronous to positive

clock edge

· Programmable Operation:

- DIMM CAS Latency: 2, 2.5
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write

· Auto Refresh (CBR) and Self Refresh Modes
· Automatic and controlled precharge commands
·

13/10/2 Addressing (row/column/bank)

· 7.8 µs Max. Average Periodic Refresh Interval
· Serial Presence Detect
· Gold contacts
· SDRAMs in 66-pin TSOP Type II Package

Description

NT256D64S88A0G is an unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),

organized as a one-bank high-speed memory array. The 32Mx64 module is a single-bank DIMM that uses eight 32Mx8 DDR

SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 266MHz. The DIMM is intended for use

in applications operating from 100 MHz to 133 MHz clock speeds with data rates of 200 to 266 MHz. Clock enable CKE0 controls all

devices on the DIMM.

Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by

address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle.

These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common

design files minimizes electrical variation between suppliers.

The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD

data are programmed and locked during module assembly. The last 128 bytes are available to the customer.

All NANYA 184 DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint.

Ordering Information

Part Number

Speed

Organization

Leads

Power

143MHz (7ns @ CL = 2.5 )

NT256D64S88A0G-7K

133MHz (7.5ns @ CL= 2 )

PC2100

133MHz (7.5ns @ CL= 2.5 )

NT256D64S88A0G 75B

100MHz (10ns @ CL = 2 )

PC2100

125MHz (8ns @ CL = 2.5 )

NT256D64S88A0G 8B

100MHz (10ns @ CL = 2 )

PC1600

32Mx64

Gold

2.5V

NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM

Preliminary

08 / 2001

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Pin Description

CK0, CK1, CK2

CK0 , CK1 , CK2

Differential Clock Inputs

DQ0-DQ63

Data input/output

CKE0

Clock Enable

RAS

Row Address Strobe

DQS0-DQS7,

DQS9-DQS16

Bidirectional data strobes

CAS

Column Address Strobe

Power (2.5V)

Write Enable

DDQ

Supply voltage for DQs(2.5V)

Chip Selects

Ground

A0-A9, A11,A12

Address Inputs

No Connect

A10/AP

Address Input/Autoprecharge

SCL

Serial Presence Detect Clock Input

BA0, BA1

SDRAM Bank Address Inputs

SDA

Serial Presence Detect Data input/output

REF

Ref. Voltage for SSTL_2 inputs

SA0-2

Serial Presence Detect Address Inputs

DDID

Identification flag.

DDSPD

Serial EEPROM positive power supply(2.5V)

Pinout

Front

Back

Front

Back

Front

Back

REF

124

DDQ

154

RAS

DQ0

DQ4

DQ24

125

155

DQ45

DQ5

126

DQ28

DQ41

156

DDQ

DQ1

DDQ

DQ25

127

DQ29

CAS

157

DQS0

DQS9

DQS3

128

DDQ

158

DQ2

DQ6

129

DQS12

DQS5

159

DQS14

DQ7

130

DQ42

160

DQ3

100

DQ26

131

DQ30

DQ43

161

DQ46

101

DQ27

132

162

DQ47

102

133

DQ31

163

103

134

DQ48

164

DDQ

DQ8

104

DDQ

135

DQ49

165

DQ52

DQ9

105

DQ12

136

DDQ

166

DQ53

DQS1

106

DQ13

137

CK0

CK2

167

DDQ

107

DQS10

138

CK0

CK2

168

CK1

108

139

DDQ

169

DQS15

CK1

109

DQ14

140

DQS6

170

DQ54

110

DQ15

141

A10

DQ50

171

DQ55

DQ10

111

142

DQ51

172

DDQ

DQ11

112

DDQ

143

DDQ

173

CKE0

113

BA1

144

DDID

174

DQ60

DDQ

114

DQ20

KEY

DQ56

175

DQ61

DQ16

115

A12

DQ32

145

DQ57

176

DQ17

116

DDQ

146

DQ36

177

DQS16

DQS2

117

DQ21

DQ33

147

DQ37

DQS7

178

DQ62

118

A11

DQS4

148

DQ58

179

DQ63

119

DQS11

DQ34

149

DQS13

DQ59

180

DDQ

DQ18

120

150

DQ38

181

SA0

121

DQ22

BA0

151

DQ39

182

SA1

DDQ

122

DQ35

152

SDA

183

SA2

DQ19

123

DQ23

DQ40

153

DQ44

SCL

184

DDSPD

Note: All pin assignments are consistent for all 8-byte unbuffered versions.

NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM

Preliminary

08 / 2001

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Input/Output Functional Description

Symbol

Type

Polarity

Function

CK0 , CK1, CK2

(SSTL)

Positive

Edge

The positive line of the differential pair of system clock inputs which drives the input to the
on-DIMM PLL. All the DDR SDRAM address and control inputs are sampled on the rising
edge of their associated clocks.

CK0 , CK1 , CK2

(SSTL)

Negative

Edge

The negative line of the differential pair of system clock inputs which drives the input to the
on-DIMM PLL.

CKE0

(SSTL)

Active

High

Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode.

(SSTL)

Active

Low

Enables the associated SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored
but previous operations continue.

RAS

CAS

(SSTL)

Active

Low

When sampled at the positive rising edge of the clock, RAS

CAS

WE define the

operation to be executed by the SDRAM.

REF

Supply

Reference voltage for SSTL-2 inputs

DDQ

Supply

Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity

BA0, BA1

(SSTL)

Selects which SDRAM bank is to be active.

A0 - A9

A10/AP

A11,A12

(SSTL)

During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,
autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.

DQ0 - DQ63,

(SSTL)

Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.

DQS0 - DQS7

DQS9 - DQS16

(SSTL)

Active

High

Data strobes: Output with read data, input with write data. Edge aligned with read data,
centered on write data. Used to capture write data.

, V

Supply

Power and ground for the DDR SDRAM input buffers and core logic

SA0 SA2

Address inputs. Connected to either V

or V

on the system board to configure the

Serial Presence Detect EEPROM address.

SDA

This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V

to act as a pullup.

SCL

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V

to act as a pullup.

DDSPD

Supply

Serial EEPROM positive power supply.

NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM

Preliminary

08 / 2001

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Functional Block Diagram

( 1 Bank, 32Mx8 DDR SDRAMs )

DQS9

DQ0
DQ1
DQ2

DQ7

DQ4

DQ6

DQ5

DQ3

DQ8
DQ9

DQ10

DQ15

DQ12

DQ14

DQ13

DQ11

A0-A12

RAS

BA0-BA1

CS : SDRAMs D0 -D7

BA0 - BA1 : SDRAMs D0 -D7

A0 - A12: SDRAMs D0 -D7

RAS : SDRAMs D0 -D7

DQ16
DQ17
DQ18

DQ23

DQ20

DQ22

DQ21

DQ19

DQ24
DQ25
DQ26

DQ31

DQ28

DQ30

DQ29

DQ27

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

VDDQ

VSS

D0 - D7

Serial PD

SCL

SDA

SA0

SA2

SA1

DQS0

DQS13

DQS4

DQS

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

DQS10

DQS1

DQS

DQS11

DQS2

DQS12

DQS3

DQS

DQ32
DQ33
DQ34

DQ39

DQ36

DQ38

DQ37

DQ35

DQ40
DQ41
DQ42

DQ47

DQ44

DQ46

DQ45

DQ43

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

DQS5

DQS14

DQ48
DQ49
DQ50

DQ55

DQ52

DQ54

DQ53

DQ51

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

DQ56
DQ57
DQ58

DQ63

DQ60

DQ62

DQ61

DQ59

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

DQS6

DQS15

DQS7

DQS16

CKE0

CAS

CAS : SDRAMs D0 -D7

CKE0 : SDRAMs D0 -D7

WE : SDRAMs D0 -D7

120 ohm

SDRAM x 2

CK0

120 ohm

SDRAM x 3

CK1

120 ohm

SDRAM x 3

CK2

D0 - D7
D0 - D7
D0 - D7

VDD

VREF

VDDID

Notes :

1. DQ-to-I/O wring may be changed within a byte.

2. DQ/DQS/DM/CKE/S relationships are maintained as shown.

3. DQ/DQS/DM/DQS resistors are 22 Ohms.
4. VDDID strap connections (for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD is not equal to VDDQ.

Strap: see Note 4

NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM

Preliminary

08 / 2001

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Serial Presence Detect --

Part 1 of 2

32Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD

SPD Entry Value

Serial PD Data Entry (Hexadecimal) Note

Byte

Description

DDR266A

-7K

DDR266B

-75B

DDR200

-8B

DDR266A

-7K

DDR266B

-75

DDR200

-8B

Number of Serial PD Bytes Written during
Production

128

Total Number of Bytes in Serial PD device

256

Fundamental Memory Type

SDRAM DDR

Number of Row Addresses on Assembly

Number of Column Addresses on Assembly

Number of DIMM Bank

Data Width of Assembly

X64

Data Width of Assembly (cont')

X64

Voltage Interface Level of this Assembly

SSTL 2.5V

DDR SDRAM Device Cycle Time at CL=2.5

7ns

7.5ns

8ns

DDR SDRAM Device Access Time from
Clock at CL=2.5

0.75ns

0.8ns

DIMM Configuration Type

Non-Parity

Refresh Rate/Type

SR/1x(7.8us)

Primary DDR SDRAM Width

Error Checking DDR SDRAM Device Width

N/A

DDR SDRAM Device Attr: Min CLk Delay,
Random Col Access

1 Clock

DDR SDRAM Device Attributes:
Burst Length Supported

2,4,8

DDR SDRAM Device Attributes: Number of
Device Banks

DDR SDRAM Device Attributes: CAS
Latencies Supported

2/2.5

DDR SDRAM Device Attributes: CS Latency

DDR SDRAM Device Attributes: WE Latency

DDR SDRAM Device Attributes:

Differential Clock

DDR SDRAM Device Attributes: General

+/-0.2V Voltage Tolerance

Minimum Clock Cycle at CL=2

7.5ns

10ns

Maximum Data Access Time from Clock at
CL=2

0.75ns

0.8ns

Minimum Clock Cycle Time at CL=1

N/A

Maximum Data Access Time from Clock at
CL=1

N/A

Minimum Row Precharge Time(t

)

20ns

Minimum Row Active to Row Active delay
(t

RRD

)

15ns

Minimum RAS to CAS delay (t

RCD

)

20ns

Minimum RAS Pulse Width (t

RAS

)

45ns

50ns

Module Bank Density

256MB

Address and Command Setup Time Before
Clock

0.9ns

1.1ns

Address and Command Hold Time After
Clock

0.9ns

1.1ns

Data Input Setup Time Before Clock

0.5ns

0.6ns

Data Input Hold Time After Clock

0.5ns

0.6ns

36-61 Reserved

Undefined

SPD Revision

Initial

Checksum Data

NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM

Preliminary

08 / 2001

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Serial Presence Detect --

Part 2 of 2

32Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD

SPD Entry Value

Serial PD Data Entry (Hexadecimal)

Byte

Description

DDR266A

-7K

DDR266B

-75B

DDR200

-8B

DDR266A

-7K

DDR266B

-75

DDR200

-8B

Note

64-71 Manufacturer's JEDED ID Code

7F7F7F0B00000000

Module Manufacturing Location

N/A

73-90 Module Part number

N/A

91-92 Module Revision Code

N/A

93-94 Module Manufacturing Data

Year/Week Code

yy/ww

1,2

95-98 Module Serial Number

Serial Number

99-255 Reserved

Undefined

yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex)

ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex)

NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM

Preliminary

08 / 2001

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Absolute Maximum Ratings

Symbol

Parameter

Rating

Units

, V

OUT

Voltage on I/O pins relative to Vss

-0.5 to V

DDQ

+0.5

Voltage on Input relative to Vss

-0.5 to +3.6

Voltage on VDD supply relative to Vss

-0.5 to +3.6

DDQ

Voltage on VDDQ supply relative to Vss

-0.5 to +3.6

Operating Temperature (Ambient)

0 to+70

°C

STG

Storage Temperature (Plastic)

-55 to +150

°C

Power Dissipation

OUT

Short Circuit Output Current

Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Capacitance

Parameter

Symbol

Max.

Units

Notes

Input Capacitance: CK0, CK0 , CK1, CK1 , CK2, CK2

Input Capacitance: A0-A11, BA0, BA1,

WE , RAS , CAS

CKE0, S0

Input Capacitance: SA0-SA2, SCL

Input/Output Capacitance DQ0-63; DQS0-7, 9-16

IO1

1,2

Input/Output Capacitance: SDA

IO3

1. V

DDQ

= V

= 2.5V ± 0.2V, f = 100 MHz, T

= 25 °C, V

OUT

(DC) = V

DDQ

/2, V

OUT

(Peak to Peak) = 0.2V.

2. DQS inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at

the board level.

NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM

Preliminary

08 / 2001

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

DC Electrical Characteristics and Operating Conditions

( T

= 0 °C ~ 70 °C ; V

DDQ

= 2.5V ± 0.2V; V

= 2.5V ± 0.2V, See AC Characteristics)

Symbol

Parameter

Min

Max

Units

Notes

Supply Voltage

2.3

2.7

DDQ

I/O Supply Voltage

2.3

2.7

, V

SSQ

Supply Voltage, I/O Supply Voltage

REF

/O Reference Voltage

0.49 x

DDQ

0.51 x

DDQ

1,2

I/O Termination Voltage (System)

REF

0.04

REF

+ 0.04

1,3

IH(DC)

Input High (Logic1) Voltage

REF

+ 0.15

DDQ

+ 0.3

IL(DC)

Input Low (Logic0) Voltage

-0.3

REF

- 0.15

IN(DC)

Input Voltage Level, CK and

Inputs

-0.3

DDQ

+ 0.3

ID(DC)

Input Differential Voltage, CK and

Inputs

0.30

DDQ

+ 0.6

1,4

Input Leakage Current

Any input 0V

DD;

(All other pins not under test = 0V)

-5

Output Leakage Current

(DQs are disabled; 0V

out

DDQ

-5

Output High Current

OUT =

DDQ

-0.373V, min V

REF

, min V

)

-16.8

Output Low Current

OUT

= 0.373, max V

REF

, max V

)

16.8

1. Inputs are not recognized as valid until V

REF

stabilizes.

2. V

REF

is expected to be equal to 0.5 V

DDQ

of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak

noise on V

REF

may not exceed 2% of the DC value.

3. V

is not applied directly to the DIMM. V

is a system supply for signal termination resistors, is expected to be set equal to V

REF

and must track variations in the DC level of V

REF

4. V

is the magnitude of the difference between the input level on CK and the input level on

NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM

Preliminary

08 / 2001

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

AC Characteristics

(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating
Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.)
1. All voltages referenced to V SS .
2. Tests for AC timing, IDD , and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but

the related specifications and device operation are guaranteed for the full voltage range specified.

3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.
4. AC timing and I DD tests may use a V

to V

swing of up to 1.5V in the test environment, but input timing is still referenced to V

REF

(or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use
conditions. The minimum slew rate for the input signals is 1V/ns in the range between V

IL(AC)

and V

IH(AC)

unless otherwise specified.

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the

signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW
(HIGH) level.

AC Output Load Circuits

Timing Reference Point

50 ohms

30 pF

Output

OUT

AC Operating Conditions

( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)

Symbol

Parameter/Condition

Min

Max

Unit

Notes

IH(AC)

Input High (Logic 1) Voltage.

REF

+ 0.31

1, 2

IL(AC)

Input Low (Logic 0) Voltage.

REF

?
- 0.31

1, 2

ID(AC)

Input Differential Voltage, CK and

Inputs

0.62

DDQ

+ 0.6

1, 2, 3

IX(AC)

Input Differential Pair Cross Point Voltage, CK and

Inputs

(0.5*V

DDQ

) - 0.2

(0.5*V

DDQ

) +? 0.2

1, 2, 4

1. Input slew rate = 1V/ ns .
2. Inputs are not recognized as valid until V

REF

stabilizes.

3. V

is the magnitude of the difference between the input level on CK and the input level on CK.

4. The value of V

is expected to equal 0.5*V

DDQ

of the transmitting device and must track variations in the DC level of the same.

NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM

Preliminary

08 / 2001

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Operating, Standby, and Refresh Currents

( T

= 0 °C ~ 70 °C ; V

DDQ

= 2.5V ± 0.2V; V

= 2.5V ± 0.2V, See AC Characteristics)

Symbol

Parameter/Condition

PC1600

PC2100

Unit

Notes

DD0

Operating Current : one bank; active / precharge; t

= t

RC (MIN)

;

= t

CK (MIN)

; DQ, DM, and DQS inputs changing twice per clock cycle;

address and control inputs changing once per clock cycle

600

680

1,2

DD1

Operating Current : one bank; active / read / precharge; Burst = 2;
t

= t

RC (MIN)

; CL=2.5; t

= t

CK (MIN)

; I

OUT

= 0mA;

address and control inputs changing once per clock cycle

720

880

1,2

DD2P

Precharge Power-Down Standby Current :
all banks idle; power-down mode; CKE

IL (MAX)

; t

= t

CK (MIN)

120

1,2

DD2N

Idle Standby Current : CS

IH (MIN)

; all banks idle; CKE

IH(MIN)

;

= t

CK (MIN)

; address and control inputs changing once per clock cycle

240

280

1,2

DD3P

Active Power-Down Standby Current : one bank active;
power-down mode; CKE

IL (MAX)

; t

= t

CK (MIN)

120

1,2

DD3N

Active Standby Current : one bank; active / precharge; CS

IH (MIN)

;

CKE

IH (MIN)

; t

= t

RAS (MAX)

; t

= t

CK (MIN)

; DQ, DM, and DQS

inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle

400

480

1,2

DD4R

Operating Current : one bank; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
DQ and DQS outputs changing twice per clock cycle; CL = 2.5;
t

= t

CK (MIN)

; I

OUT

= 0mA

1040

1320

1,2

DD4W

Operating Current : one bank; Burst = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
DQ and DQS inputs changing twice per clock cycle; CL=2.5;
t

= t

CK (MIN)

920

1200

1,2

= t

RFC (MIN)

1280

1360

1,2

DD5

Auto-Refresh Current :

= 7.8 µs

132

1,2,4

DD6

Self-Refresh Current : CKE

?0.2V

1,2,3

1. I

specifications are tested after the device is properly initialized.

2. Input slew rate = 1V/ ns .
3. Enables on-chip refresh and address counters.
4. Current at 7.8 µs is time averaged value of I

DD5

at t

RFC (MIN)

and I

DD2P

over 7.8 µs.

NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM

Preliminary

08 / 2001

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

AC Timing Specifications for DDR SDRAM Devices Used on Module

( T

= 0 °C ~ 70 °C ; V

DDQ

= 2.5V ± 0.2V; V

= 2.5V ± 0.2V, See AC Characteristics)

(Part 1 of 2)

-7K

-75B

-8B

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Notes

DQ output access time from CK/ CK

-0.75

+0.75

-0.75

+0.75

-0.8

+0.8

1,2,3,4

DQSCK

DQS output access time from CK/ CK

-0.75

+0.75

-0.75

+0.75

-0.8

+0.8

1,2,3,4

CK high-level width

0.45

0.55

0.45

0.55

0.45

0.55

1,2,3,4

CK low-level width

0.45

0.55

0.45

0.55

0.45

0.55

1,2,3,4

CL=2.5

7.5

1,2,3,4

Clock cycle time

CL=2

7.5

1,2,3,4

DQ and DM input hold time

0.5

0.6

1,2,3,4

,15,16

DQ and DM input setup time

0.5

0.6

1,2,3,4

,15,16

DIPW

DQ and DM input pulse width (each input)

1.75

1,2,3,4

Data-out high-impedance time from
CK/ CK

-0.75

+0.75

-0.75

+0.75

-0.8

+0.8

1, 2, 3,

4, 5

Data-out low-impedance time from
CK/ CK

-0.75

+0.75

-0.75

+0.75

-0.8

+0.8

1, 2, 3,

4, 5

DQSQ

DQS-DQ skew (DQS & associated DQ
signals)

0.5

0.6

1,2,3,4

DQSQA

DQS-DQ skew (DQS & all DQ signals)

0.5

0.6

1,2,3,4

Minimum half clk period for any given
cycle; defined by clk high(t

)

or clk low (t

) time

1,2,3,4

Data output hold time from DQS

0.75ns

1.0ns

1,2,3,4

DQSS

Write command to 1st DQS latching
transition

0.75

1.25

0.75

1.25

0.75

1.25

1,2,3,4

DQSL,H

DQS input low (high) pulse width
(write cycle)

0.35

1,2,3,4

DSS

DQS falling edge to CK setup time
(write cycle)

0.2

1,2,3,4

DSH

DQS falling edge hold time from CK
(write cycle)

0.2

1,2,3,4

MRD

Mode register set command cycle time

1,2,3,4

WPRES

Write preamble setup time

1, 2, 3,

4, 7

WPST

Write postamble

0.40

0.60

0.40

0.60

0.40

0.60

1, 2, 3,

4, 6

WPRE

Write preamble

0.25

1,2,3,4

Address and control input hold time
(fast slew rate)

0.9

1.1

2, 3, 4,

9, 11,

Address and control input setup time
(fast slew rate)

0.9

1.1

2, 3, 4,

9, 11,

Address and control input hold time
(slow slew rate)

1.0

1.1

2, 3, 4,
10, 11,

12,

NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM

Preliminary

08 / 2001

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

AC Timing Specifications for DDR SDRAM Devices Used on Module

( T

= 0 °C ~ 70 °C ; V

DDQ

= 2.5V ± 0.2V; V

= 2.5V ± 0.2V, See AC Characteristics)

(Part 2 of 2)

-7K

-75B

-8B

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Notes

Address and control input setup time

(slow slewrate)

1.0

1.1

2, 3, 4,
10, 11,

12, 14

IPW

Input pulse width

2.2

2, 3, 4,

RPRE

Read preamble

0.9

1.1

0.9

1.1

0.9

1.1

1,2,3,4

RPST

Read postamble

0.40

0.60

0.40

0.60

0.40

0.60

1,2,3,4

RAS

Active to Precharge command

120,000

1,2,3,4

Active to Active/Auto-refresh

command period

1,2,3,4

RFC

Auto-refresh to Active/Auto-refresh

command period

1,2,3,4

RCD

Active to Read or Write delay

1,2,3,4

RAP

Active to Read Command with

Autoprecharge

1,2,3,4

Precharge command period

1,2,3,4

RRD

Active bank A to Active bank B

command

1,2,3,4

Write recovery time

1,2,3,4

DAL

Auto precharge write recovery +

precharge time

)

1, 2, 3,

4, 13

WTR

Internal write to read command delay

1,2,3,4

XSNR

Exit self-refresh to non-read

command

1,2,3,4

XSRD

Exit self-refresh to read command

200

1,2,3,4

REFI

Average Periodic Refresh Interval

7.8

µs

1, 2, 3,

4, 8

NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM

Preliminary

08 / 2001

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

AC Timing Specification Notes

1. Input slew rate = 1V/ns.
2. The CK/ CK input reference level (for timing reference to CK/ CK ) is the point at which CK and CK cross: the input reference level for

signals other than CK/ CK , is V

REF

3. Inputs are not recognized as valid until V

REF

stabilizes.

4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V

5. t

and t

transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a

specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system

performance (bus turnaround) degrades accordingly.

7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid

transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in
progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW,
or transitioning from high to low at this time, depending on tDQSS .

8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device.
9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between V

(AC) and V

(AC).

10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between V

(AC) and V

(AC).

11. CK/ CK slew rates are >= 1.0 V/ns.
12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by

design or tester characterization.

13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t CK is equal to the actual system

clock cycle time. For example, for PC2100 at CL= 2.5, t DAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5.

14. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew rate is below 0.5 V/ns.

Input Slew Rate

?
Delta ( t

IS )

Delta ( t

IH )

Unit

Note

0.5 V/ns

1,2

0.4 V/ns

+50

1,2

0.3 V/ns

+100

1,2

1. Input slew rate is based on the lesser of the slew rates determined by either V

IH (AC)

to V

IL (AC)

or V

IH (DC)

to V

IL (DC)

, similarly

for rising transitions.

2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.

15. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below 0.5 V/ns.

Input Slew Rate

Delta ( t

DS )

Delta ( t

DH )

Unit

Note

0.5 V/ns

1,2

0.4 V/ns

+75

1,2

0.3 V/ns

+150

1,2

1. I/O slew rate is based on the lesser of the slew rates determined by either V

IH (AC)

to V

IL (AC)

or V

IH (DC)

to V

IL (DC)

, similarly for

rising transitions.

2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.

16. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH in the case where DQ, DM, and DQS slew rates differ.

Delta Rise and Fall Rate

Delta ( t

DS )

Delta ( t

DH )

Unit

Note

0.0 ns/V

1,2,3,4

0.25 ns/V

+50

1,2,3,4

0.5 ns/V

+100

1,2,3,4

1. Input slew rate is based on the lesser of the slew rates determined by either V

IH (AC)

to V

IL (AC)

or V

IH (DC)

to V

IL (DC)

, similarly

for rising transitions.

2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.
3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]

For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V
Using the table above, this would result in an increase in t

and t

of 100 ps.

4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each

device.

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