NT256S64VH8A0GM
256MB : 32M x 64
SDRAM SODIMM

PRELIMINARY

08 / 2001

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

32Mx64 bit Two Bank Small Outline SDRAM Module

based on 16Mx16, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD

Features

144 Pin JEDEC Standard, 8 Byte Small Outline Dual-In-line

Memory Module

32Mx64 Synchronous DRAM SO DIMM

Inputs and outputs are LVTTL (3.3V) compatible

10 Ohm Resistors on DQs

Single 3.3V

0.3V Power Supply

Single Pulsed RAS interface

SDRAMs have four internal banks

Fully Synchronous to positive Clock Edge

Data Mask for Byte Read/Write control

Auto Refresh (CBR) and Self Refresh

Automatic and controlled Precharge Commands

Programmable Operation:

- CAS Latency: 2, 3

- Burst Type: Sequential or Interleave

- Burst Length: 1, 2, 4, 8,

- Operation: Burst Read and Write or Multiple Burst Read with

Single Write

Suspend Mode and Power Down Mode

13/9/2 Addressing (Row/Column/Bank)

8192 refresh cycles distributed across 64ms

Serial Presence Detect

Gold contacts

Description

NT256S64VH8A0GM is a 144-pin Synchronous DRAM Small Outline Dual In-line Memory Module (SO DIMM) that is organized as a 32Mx64
high-speed memory array. The SO DIMM uses eight 16Mx16 SDRAMs in 400mil TSOP II packages and achieves high-speed data transfer
rates of up to 133 MHz by employing a prefetch / pipeline hybrid architecture that supports the JEDEC 1N rule while allowing very low burst
power.

All control, address, and data input/output circuits are synchronized with the positive edge of the externally supplied clock inputs. All inputs are
sampled at the positive edge of the externally supplied clock (CK0,CK1). Internal operating modes are defined by combinations of the

RAS , CAS , WE , S0 , S1, DQMB, and CKE0, CKE1signals. A command decoder initiates the necessary timings for each operation.

Prior to any access operation, the CAS latency, burst type, burst length, and burst operation type must be programmed into the SO DIMM by
address inputs A0-A9 during the mode register set cycle. The SO DIMM uses serial presence detects implemented via a serial EEPROM using
the two pin IIC protocol. The first 128 bytes of serial PD data are used by the DIMM manufacturer. The last 128 bytes are available to the
customer.

All Nanya 144-pin SO DIMMs provide a high performance, flexible 8-byte interface in a 2.66" long space-saving footprint.

Ordering Information

Speed

Part Number

MHz.

t RCD

t RP

Organization

Leads

Power

143MHz

NT256S64VH8A0GM-7K

133MHz

NT256S64VH8A0GM-75B

100MHz

125MHz

NT256S64VH8A0GM-8B

100MHz

32Mx64

Gold

3.3V

* CL =

CAS Latency

NT256S64VH8A0GM
256MB : 32M x 64
SDRAM SODIMM

PRELIMINARY

08 / 2001

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Pin Description

CK0,CK1

Clock Inputs

DQ0-DQ63

Data input/output

CKE0,CKE1

Clock Enable

DQMB0-DQMB7

Data Mask

RAS

Row Address Strobe

Power (3.3V)

CAS

Column Address Strobe

Ground

Write Enable

No Connect

S0 , S1

Chip Selects

SCL

Serial Presence Detect Clock Input

A0-A9, A11,A12

Address Inputs

SDA

Serial Presence Detect Data input/output

A10 / AP

Address Input/Autoprecharge

Don't use

BA0, BA1

SDRAM Bank Address

Pinout

Front

Back

Front

Back

Front

Back

DQ14

DQ46

DQ21

DQ53

DQ0

DQ32

DQ15

DQ47

DQ22

DQ54

DQ1

DQ33

DQ23

100

DQ55

DQ2

DQ34

101

102

DQ3

DQ35

103

104

105

106

BA0

DQ4

DQ36

107

108

DQ5

DQ37

Voltage Key

109

110

BA1

DQ6

DQ38

CK0

CKE0

111

A10/ AP

112

A11

DQ7

DQ39

113

114

RAS

CAS

115

DQMB2

116

DQMB6

DQMB0

DQMB4

CKE1

117

DQMB3

118

DQMB7

DQMB1

DQMB5

A12

119

120

121

DQ24

122

DQ56

CK1

123

DQ25

124

DQ57

125

DQ26

126

DQ58

127

DQ27

128

DQ59

129

130

DQ8

DQ40

131

DQ28

132

DQ60

DQ9

DQ41

DQ16

DQ48

133

DQ29

134

DQ61

DQ10

DQ42

DQ17

DQ49

135

DQ30

136

DQ62

DQ11

DQ43

DQ18

DQ50

137

DQ31

138

DQ63

DQ19

DQ51

139

140

DQ12

DQ44

141

SDA

142

SCL

DQ13

DQ45

DQ20

DQ52

143

144

Note: All pin assignments are consistent for all 8-byte versions.

NT256S64VH8A0GM
256MB : 32M x 64
SDRAM SODIMM

PRELIMINARY

08 / 2001

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

SDRAM DIMM Block Diagram

(2 Bank, 16Mx16 SDRAMs)

DQMB0

LDQM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQMB4

LDQM

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQMB1

UDQM

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQMB5

UDQM

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

RAS

CAS

CKE0

A0-A12

BA0

BA1

SDRAMs D0-D7

SDRAMs D0-D3

SDRAMs D0-D7

SDRAMs D0-D7
SDRAMs D0-D7

SDRAMs D0-D7

SPD

SCL

D0 - D7

SDA

CK0 / CK1

CK1

10pF

DQMB2

LDQM

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQMB6

LDQM

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQMB3

UDQM

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQMB7

UDQM

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

10ohm

D0 / D4

D1 / D5

D2 / D6

D3 / D7

DQn

Every DQ pin of SDRAM

LDQM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

UDQM

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

LDQM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

UDQM

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

LDQM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

UDQM

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

LDQM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

UDQM

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

CKE1

SDRAMs D4-D7

NT256S64VH8A0GM
256MB : 32M x 64
SDRAM SODIMM

PRELIMINARY

08 / 2001

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Input/Output Functional Description

Symbol

Type

Signal

Polarity

Function

CK0, CK1

Input

Pulse

Positive

Edge

The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of

their associated clock.

CKE0, CKE1

Input

Level

Active

High

Activates the SDRAM CK0 and CK1 signals when high and deactivates them when low.

By deactivating the clocks, CKE0 low initiates the Power Down mode, Suspend mode, or

the Self-Refresh mode.

S0 , S1

Input

Pulse

Active

Low

Enables the associated SDRAM command decoder when low and disables the

command decoder when high. When the command decoder is disabled, new commands

are ignored but previous operations continue.

RAS

CAS

Input

Pulse

Active

Low

When sampled at the positive rising edge of the clock, RAS

CAS

WE define the

operation to be executed by the SDRAM.

BA0, BA1

Input

Level

Selects which SDRAM bank is to be active.

A0 - A9

A10/AP

A11, A12

Input

Level

During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)

when sampled at the rising clock edge.

During a Read or Write command cycle, A0-A8 defines the column address (CA0-CA8)

when sampled at the rising clock edge. In addition to the column address, AP is used to

invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,

autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,

autoprecharge is disabled.

During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control

which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the

state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to

pre-charge.

DQ0 - DQ63

Input

/Output

Level

Data and Check Bit input/output pins operate in the same manner as on conventional

DRAMs.

DQMB0 -DQMB7

Input

Pulse

Active

High

The Data input/output mask places the DQ buffers in a high impedance state when

sampled high. In Read mode, DQM has a latency of two clock cycles and controls the

output buffers like an output enable. In Write mode, DQM has a latency of zero and

operates as a byte mask by allowing input data to be written if it is low but blocks the

Write operation if DQM is high.

SDA

Input

/Output

Level

Serial Data. Bi-directional signal used to transfer data into and out of the Serial Presence

Detect EEPROM. Since the SDA signal is Open Drain/Open Collector at the EEPROM, a

pull-up resistor is required on the system board.

SCL

Input

Pulse

Serial Clock. Used to clock all Serial Presence Detect data into and out of the EEPROM.

Since the SCL signal is inactive in the "high" state, a pull-up resistor is recommended on

the system board.

, V

Supply

Power and ground for the module.

NT256S64VH8A0GM
256MB : 32M x 64
SDRAM SODIMM

PRELIMINARY

08 / 2001

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Absolute Maximum Ratings

Symbol

Parameter

Rating

Units

Notes

DD,

DDQ

Voltage on V

relative to V

-0.3 to +4.6

IN,

OUT

Voltage on Any Pin to V

-0.3 to V

+ 0.3

Operating Temperature (ambient)

0 to +70

°C

STG

Storage Temperature

-55 to +125

°C

Power Dissipation

OUT

Short Circuit Output Current

1.1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Recommended DC Operating Conditions

=0 to 70

°C)

Rating

Symbol

Parameter

Min.

Typ.

Max.

Units

Notes

Power Voltage

3.0

3.3

3.6

Input High Voltage

2.0

+ 0.3

1,2

Input Low Voltage

-0.3

0.8

1,3

Output High Voltage

2.4

Output Low Voltage

0.4

Input Leakage current

-10

µA

1. All voltages referenced to V

2. V

(max) = V

/ V

DDQ

+ 1.2V for pulse width

5ns

(min) = V

/ V

SSQ

- 1.2V for pulse width

5ns .

Capacitance

=25 °C , f =1MHz, V

=3.3 ± 0.3V)

Symbol

Parameter

Max.

Unit

Input Capacitance (A0-A9, A10/AP, A11, A12, BA0, BA1, RAS

CAS

WE )

Input Capacitance (CKE0,CKE1)

Input Capacitance ( S0 , S1)

Input Capacitance (CK0,CK1 )

Input Capacitance (DQMB0 - DQMB7)

Input Capacitance (SCL)

IO1

Input/Output Capacitance (DQ0 - DQ63)

IO2

Input/Output Capacitance (SDA)

DC Output Load Circuit

VOH(DC) = 2.4V,IOH= -2mA

VOL(DC) = 0.4V,IOL= -2mA

3.3 V

1200 ohms

870 ohms

50 pF

Output

NT256S64VH8A0GM
256MB : 32M x 64
SDRAM SODIMM

PRELIMINARY

08 / 2001

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Operating, Standby, and Refresh Currents

=0 to 70 °C, V

=3.3 ± 0.3V)

Speed

Parameter

Symbol

Test condition

- 7K

- 75B

- 8B

Unit

Note

Operating current

CC1

1 bank operation , t

= t

(mim), t

= min

Active-Precharge Command cycling

without burst operation

1040

960

920

1, 2

CC2P

CKE

(max), t

= min,

S0 , S1= V

(min)

Precharge

standby current

in power-down mode

CC2PS

CKE

(max), t

=oo ,

S0 , S1= V

(min)

CC2N

CKE

(min), t

= min

S0 , S1= V

(min)

240

160

Precharge

standby current in non

power-down mode

CC2NS

CKE

(min), t

=oo,

S0 , S1= V

(min)

CC3P

CKE

(max), t

=min.

S0 , S1= V

(min) , (Power Down Mode)

No Operating current

( Active state : 4 bank)

CC3N

CKE

(min), t

=min

S0 , S1= V

(min)

480

360

Operating current

( Burst mode )

CC4

=min , Read/ Write command cycling,

Multiple banks active, gapless data, BL=4

960

720

2, 6

Auto(CBR)

refresh current

CC5

=min, CBR command cycling

1400

1320

Self refresh current

CC6

CKE

0.2V

1. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t

and t

. Input

signals are changed up to three times during t

(min).

2. The specified values are obtained with the output open.
3. Input signals are changed once during three clock cycles.
4. Input signals are stable.
5. Active standby current will be higher if Clock Suspend is entered during a Burst Read cycle (add 1mA per DQ).
6. Input signals are changed once during tCK(min) .
7. V

=3.3V

NT256S64VH8A0GM
256MB : 32M x 64
SDRAM SODIMM

PRELIMINARY

08 / 2001

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

AC Characteristics

=0 to 70 °C , V

=3.3 ± 0.3V)

1. An initial pause of 200µs,with DQMB0-7 and CKE held high, is required after power-up. A Precharge All Banks command must be given

followed by a minimum of eight Auto (CBR) Refresh cycles before or after the Mode Register Set operation.

2. The Transition time is measured between

and

(or between V

and

3. In addition to meeting the transition rate specification, the CLK and CKE signals must transit between V

and V

(or between V

and V

)

in a monotonic manner.

4. AC timing tests have V

=0.8V and V

= 2.0 V with the timing referenced to the 1.40V cross over point.

5. AC measurements assume t T =1.2 ns.

AC Output Load Circuits

Clock

Input

Output

HOLD

SETUP

CKL

CKH

1.4V

tOH

1.4V

Output

Zo = 50 ohm

50 pF

AC Output Load Circuit

NT256S64VH8A0GM
256MB : 32M x 64
SDRAM SODIMM

PRELIMINARY

08 / 2001

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

AC Timing Parameters
Clock and Clock Enable Parameters

- 7K

- 75B

- 8B

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Note

tCK3

Clock Cycle Time, CAS Latency = 3

1000

7.5

1000

tCK2

Clock Cycle Time, CAS Latency = 2

7.5

1000

tAC3(B)

Clock Access Time, CAS Latency = 3

5.4

tAC2(B)

Clock Access Time, CAS Latency = 2

5.4

tCKH

Clock High Pulse Width

2.5

tCKL

Clock Low Pulse Width

2.5

tCES

Clock Enable Set-up Time

1.5

tCEH

Clock Enable Hold Time

0.8

tSB

Power down mode Entry Time

7.5

Transition Time (Rise and Fall)

0.5

Access time is measured at 1.4V. In AC Characteristics section, see notes.

CKH

is the pulse width of CLK measured from the positive edge to the negative edge referenced to V

(min). t

CKL

is the pulse width of

CLK measured from the negative edge to the positive edge referenced to V

(max).

Common Parameters

- 7K

- 75B

- 8B

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Note

tCS

Command Setup Time

1.5

tCH

Command Hold Time

0.8

tAS

Address and Bank Select Set-up Time

1.5

tAH

Address and Bank Select Hold Time

0.8

tRCD

RAS to CAS Delay

tRC

Bank Cycle Time

67.5

tRFC

Auto Refresh to Active/Auto Refresh

67.5

tRAS

Active Command Period

100K

tRP

Precharge Time

tRRD

Bank to Bank Delay Time

tCCD

CAS to CAS Delay Time

CLK

These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:

the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).

Mode Register Set Cycle

- 7K

- 75B

- 8B

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Note

tRSC

Mode Register Set Cycle Time

CLK

These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:

the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).

NT256S64VH8A0GM
256MB : 32M x 64
SDRAM SODIMM

PRELIMINARY

08 / 2001

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Read Cycle

- 7K

- 75B

- 8B

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Note

2.5

tOH

Data Out Hold Time

2.7

tLZ

Data Out to Low Impedance Time

tHZ3

Data Out to High Impedance Time

5.4

tDQZ

DQM Data Out Disable Latency

CLK

1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.

Refresh Cycle

- 7K

- 75B

- 8B

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Note

tREF

Refresh Period

tSREX

Self Refresh Exit Time

Write Cycle

- 7K

- 75B

- 8B

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Note

tDS

Data In Set-up Time

1.5

tDH

Data In Hold Time

0.8

tDPL

Data input to Precharge

tDAL3

Data In to Active Delay

CAS Latency = 3

CLK

tDAL2

Data In to Active Delay

CAS Latency = 2

CLK

tDQW

DQM Write Mask Latency

NT256S64VH8A0GM
256MB : 32M x 64
SDRAM SODIMM

PRELIMINARY

08 / 2001

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Serial Presence Detect --

Part 1 of 2

32Mx64 SDRAM SODIMM based on 16Mx16, 4Banks, 8K Refresh, 3.3V SDRAMs with SPD

SPD Entry Value

Serial PD Data Entry

(Hexadecimal)

Byte

Description

-7K

-75B

-8B

-7K

-75

-8B

Note

Number of Serial PD Bytes Written during Production

128

Total Number of Bytes in Serial PD device

256

Fundamental Memory Type

SDRAM

Number of Row Addresses on Assembly

Number of Column Addresses on Assembly

Number of DIMM Bank

Data Width of Assembly

X64

Data Width of Assembly (cont')

X64

Voltage Interface Level of this Assembly

LVTTL

SDRAM Device Cycle Time at CL=3

7ns

7.5ns

8ns

SDRAM Device Access Time from Clock at CL=3

5.4ns

6ns

DIMM Configuration Type

Non-Parity

Refresh Rate/Type

7.8µs / SR

Primary SDRAM Width

X16

Error Checking SDRAM Device Width

N/A

SDRAM Device Attributes :
Minimum Clock Delay, Random Column Access

1 Clock

SDRAM Device Attributes: Burst Length Supported

1,2,4,8

SDRAM Device Attributes: Number of Device Banks

SDRAM Device Attributes: CAS Latency

2, 3

SDRAM Device Attributes: CS Latency

SDRAM Device Attributes:

WE Latency

SDRAM Module Attributes

Unbuffered

SDRAM Device Attributes: General

Wr-1/Rd Burst, Precharge All,

Auto-Precharge, V

+/-

10%

Minimum Clock Cycle at CL=2

7.5ns

10ns

Maximum Data Access Time from Clock at CL=2

5.4ns

6ns

Minimum Clock Cycle Time at CL=1

N/A

Maximum Data Access Time from Clock at CL=1

N/A

Minimum Row Precharge Time (t

)

15ns

20ns

Minimum Row Active to Row Active delay (t

RRD

)

15ns

20ns

Minimum RAS to CAS delay (t

RCD

)

15ns

20ns

Minimum RAS Pulse Width (t

RAS

)

45ns

50ns

Module Bank Density

128MB

Address and Command Setup Time Before Clock

1.5ns

2ns

Address and Command Hold Time After Clock

0.8ns

1ns

Data Input Setup Time Before Clock

1.5ns

2ns

Data Input Hold Time After Clock

0.8ns

1ns

36-61 Reserved

Undefined

SPD Revision

1.2

Checksum for bytes 0 - 62

NT256S64VH8A0GM
256MB : 32M x 64
SDRAM SODIMM

PRELIMINARY

08 / 2001

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Serial Presence Detect --

Part 2 of 2

32Mx64 SDRAM SODIMM based on 16Mx16, 4Banks, 8K Refresh, 3.3V SDRAMs with SPD

SPD Entry Value

Serial PD Data Entry

(Hexadecimal)

Byte

Description

-7K

-75B

-8B

-7K

-75B

-8B

Note

64-71 Manufacturer's JEDED ID Code

NANYA

7F7F7F0B00000000

Module Manufacturing Location

N/A

73-90 Module Part number

N/A

91-92 Module Revision Code

N/A

93-94 Module Manufacturing Data

Year/Week Code

yy/ww

1,2

95-98 Module Serial Number

Serial Number

99-125 Reserved

Undefined

126

Modules Supports this Clock Frequency

100MHz

127

Attributes for Clock Frequency defined in byte 126

CK0, CK1, CK2,CK3,

CL3, CL2

Concurrent AP

128-255 Open for customer Use

Undefined

yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex)

ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex)

NANYA 11decimal (bank four) 0000 1011 binary 0B Hex.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: NT256S64VH8A0GM-75B

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: NT256S64VH8A0GM-75B