NT512D64S8HABG
512MB : 64M x 64
PC2700 Unbuffered DIMM

184pin Two Bank

Unbuffered DDR SDRAM MODULE

Based on DDR333 64Mx8 SDRAM

Features

184-Pin Unbuffered 8-Byte Dual In-Line Memory Module

· 64Mx64 Double Data Rate (DDR) SDRAM DIMM
· Performance:

PC2700

Speed Sort

-6

DIMM CAS Latency

2.5

Unit

Clock Frequency

166

133

MHz

Clock Cycle

7.5

DQ Burst Frequency

333

266

MHz

· Intended for 100 MHz and 133 MHz applications

· Inputs and outputs are SSTL-2 compatible
· V

= 2.5Volt ±

0.2, V

DDQ

= 2.5Volt ± 0.2

· SDRAMs have 4 internal banks for concurrent operation
· Module has two physical banks

· Differential clock inputs
· Data is read or written on both clock edges

· DRAM D

aligns DQ and DQS transitions with clock

transitions.

· Address and control signals are fully synchronous to positive

clock edge

· Programmable Operation:

- DIMM CAS Latency: 2, 2.5
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write

· Auto-Refresh (CBR) and Self-Refresh Modes
· Automatic and controlled precharge commands
· 13/10/2 Addressing (row/column/bank)
· 7.8

µs Max. Average Periodic Refresh Interval

· Serial Presence Detect
· Gold contacts
· SDRAMs in 66-pin TSOP Type II Package

Description

NT512D64S8HABG is an unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),

organized as a two-bank high-speed memory array. The 64Mx64 module is a dual-bank DIMM that uses sixteen 32Mx8 DDR

SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 266MHz. The DIMM is intended for use

in applications operating from 100 MHz to 133 MHz clock speeds with data rates of 200 to 266 MHz. Clock enable CKE0 and/or CKE1

controls all devices on the DIMM.

Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by

address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle.

These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common

design files minimizes electrical variation between suppliers.

The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD

data are programmed and locked during module assembly. The last 128 bytes are available to the customer.

All NANYA 184 DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint.

Ordering Information

Part Number

Speed Organization

Leads

Power

166MHz (6ns @ CL = 2.5)

NT512D64S8HABG-6

133MHz (7.5ns @ CL= 2)

PC2700 64Mx64 Gold

2.5V

REV 1.1

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© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT512D64S8HABG
512MB : 64M x 64
PC2700 Unbuffered DIMM

Pin Description

CK0, CK1, CK2

Differential Clock Inputs

DQ0-DQ63

Data input/output

CKE0, CKE1

Clock Enable

RAS Row

Address

Strobe

DQS0-DQS7,

DQS9-DQS16

Bi-directional data strobes

CAS Column

Address

Strobe V

Power

(2.5V)

WE Write

Enable V

DDQ

Supply voltage for DQs (2.5V)

S0, S1 Chip

Selects V

Ground

A0-A9, A11, A12

Address Inputs

No Connect

A10/AP Address

Input/Auto-precharge

SCL Serial Presence Detect Clock Input

BA0, BA1

SDRAM Bank Address Inputs

SDA

Serial Presence Detect Data input/output

REF

Ref. Voltage for SSTL_2 inputs

SA0-2

Serial Presence Detect Address Inputs

DDID

Identification flag.

DDSPD

Serial EEPROM positive power supply (2.5V)

Pinout

Pin Front Pin Back Pin Front Pin

Back Pin

Front Pin Back

1 V

REF

93 V

32 A5 124

62 V

DDQ

154 RAS

2 DQ0 94 DQ4 33 DQ24

125

A6 63 WE 155 DQ45

3 V

95 DQ5 34 V

126

DQ28 64 DQ41 156 V

DDQ

4 DQ1 96 V

DDQ

35 DQ25 127

DQ29 65 CAS 157 S0

5 DQS0 97 DQS9 36 DQS3 128

DDQ

66 V

158 S1

6 DQ2 98 DQ6 37 A4 129

DQS12

DQS5

159

DQS14

7 V

99 DQ7 38 V

130

A3 68 DQ42 160 V

8 DQ3

100 V

39 DQ26 131

DQ30 69 DQ43 161 DQ46

9 NC

101 NC 40

DQ27

132

70 V

162 DQ47

10 NC 102 NC 41 A2 133

DQ31

71 NC 163 NC

11 V

103 NC 42 V

134

NC 72 DQ48 164 V

DDQ

12 DQ8 104 V

DDQ

43 A1 135

NC 73 DQ49 165 DQ52

13 DQ9 105 DQ12 44 NC 136

DDQ

74 V

166 DQ53

14 DQS1 106 DQ13 45 NC 137

CK0 75 CK2 167 NC

15 V

DDQ

107 DQS10 46 V

138

CK0 76 CK2 168 V

16 CK1 108 V

47 NC 139

77 V

DDQ

169 DQS15

CK1 109 DQ14 48 A0 140

NC 78 DQS6 170 DQ54

18 V

110 DQ15 49 NC 141

A10 79 DQ50 171 DQ55

19 DQ10 111 CKE1 50 V

142

NC 80 DQ51 172 V

DDQ

20 DQ11 112 V

DDQ

51 NC 143

DDQ

81 V

173 NC

21 CKE0 113 NC 52 BA1 144

NC 82 V

DDID

174 DQ60

22 V

DDQ

114 DQ20

KEY

83 DQ56 175 DQ61

23 DQ16 115 A12 53 DQ32 145

84 DQ57

176 V

24 DQ17 116 V

54 V

DDQ

146

DQ36 85 V

177

DQS16

25 DQS2 117 DQ21 55 DQ33 147

DQ37 86 DQS7 178 DQ62

26 V

118 A11 56 DQS4 148

87 DQ58

179

DQ63

27 A9 119 DQS11 57 DQ34 149

DQS13 88 DQ59 180 V

DDQ

28 DQ18 120 V

58 V

150

DQ38 89 V

181 SA0

29 A7 121 DQ22 59 BA0 151

DQ39 90 NC 182 SA1

30 V

DDQ

122 A8 60 DQ35 152

91 SDA 183 SA2

31 DQ19 123 DQ23 61 DQ40 153

DQ44 92 SCL 184

DDSPD

Note: NC=No Connect; NU = Not Useable; DU = Do Not Use.
All pin assignments are consistent for all 8-byte unbuffered versions.

REV 1.1

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NT512D64S8HABG
512MB : 64M x 64
PC2700 Unbuffered DIMM

Input/Output Functional Description

Symbol

Type

Polarity

Function

CK0, CK1, CK2

(SSTL)

Positive

Edge

The positive line of the differential pair of system clock inputs. All the DDR SDRAM
address and control inputs are sampled on the rising edge of their associated clocks.

CK0, CK1, CK2 (SSTL)

Negative

Edge

The negative line of the differential pair of system clock inputs.

CKE0, CKE1

(SSTL)

Active

High

Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self-Refresh
mode.

S0, S1

(SSTL)

Active

Low

Enables the associated SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored
but previous operations continue.

RAS

CAS

(SSTL)

Active

Low

When sampled at the positive rising edge of the clock, RAS

CAS

WE define the operation

to be executed by the SDRAM.

REF

Supply

Reference voltage for SSTL-2 inputs

DDQ

Supply

Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity

BA0, BA1

(SSTL)

Selects which SDRAM bank is to be active.

A0 - A9

A10/AP

A11, A12

(SSTL)

During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke Auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high,
auto-precharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,
auto-precharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.

DQ0 - DQ63

(SSTL)

Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.

DQS0 - DQS7

DQS9 - DQS16

(SSTL)

Active

High

Data strobes: Output with read data, input with write data. Edge aligned with read data,
centered on write data. Used to capture write data.

DD,

Supply

Power and ground for the DDR SDRAM input buffers and core logic

SA0 SA2

Address inputs. Connected to either V

or V

on the system board to configure the

Serial Presence Detect EEPROM address.

SDA

This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V

to act as a pullup.

SCL

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V

to act as a pullup.

DDSPD

Supply

Serial EEPROM positive power supply.

REV 1.1

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT512D64S8HABG
512MB : 64M x 64
PC2700 Unbuffered DIMM

Functional Block Diagram

(2 Bank, 32Mx8 DDR SDRAMs)

Serial PD

SCL

SDA

SA0

SA2

SA1

A0-A13

RAS

BA0-BA1

BA0-BA1 : SDRAMs D0-D15

A0-A13 : SDRAMs D0-D15

RAS : SDRAMs D0-D15

CKE0

CAS

CAS : SDRAMs D0-D15

CKE : SDRAMs D0-D7

CKE : SDRAMs D8-D15

WE : SDRAMs D0-D15

CKE1

DDSPD

REF

DDID

DDQ

Strap: see Note 4

SPD
D0-D15
D0-D15
D0-D15

DQS9

DQ0
DQ1
DQ2

DQ7

DQ4

DQ6

DQ5

DQ3

DQ8
DQ9

DQ10

DQ15

DQ12

DQ14

DQ13

DQ11

DQ16
DQ17
DQ18

DQ23

DQ20

DQ22

DQ21

DQ19

DQ24
DQ25
DQ26

DQ31

DQ28

DQ30

DQ29

DQ27

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS0

DQS13

DQS4

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS10

DQS1

DQS

DQS11

DQS2

DQS12

DQS3

DQS

DQ32
DQ33
DQ34

DQ39

DQ36

DQ38

DQ37

DQ35

DQ40
DQ41
DQ42

DQ47

DQ44

DQ46

DQ45

DQ43

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

DQS5

DQS14

DQ48
DQ49
DQ50

DQ55

DQ52

DQ54

DQ53

DQ51

DQ56
DQ57
DQ58

DQ63

DQ60

DQ62

DQ61

DQ59

DQS6

DQS15

DQS7

DQS16

DQS

I/O 0
I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

DQS

I/O 0
I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

DQS

I/O 0
I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D10

DQS

I/O 0
I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D11

DQS

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

I/O 7
I/O 6

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 2

DQS

I/O 0
I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D12

DQS

I/O 0
I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D13

DQS

I/O 0
I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D14

DQS

I/O 0
I/O 1

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 5

D15

DQS

* Wire per Clock Loading Table/

Wiring Diagrams

* Clock Wiring

Clock Input

SDRAMs

*CK0/CK0
*CK1/CK1
*CK2/CK2

4 SDRAMs
6 SDRAMs
6 SDRAMs

Notes :

1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
4. V

DDID

strap connections (for memory device V

, V

DDQ

STRAP OUT (OPEN): V

= V

DDQ

STRAP IN (V

): V

is not equal to V

DDQ

REV 1.1

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© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT512D64S8HABG
512MB : 64M x 64
PC2700 Unbuffered DIMM

Serial Presence Detect --

Part 1 of 2

SPD Entry Value

Serial PD Data Entry (Hexadecimal) Note

Byte

Description

DDR333

-6

DDR333

-6

Number of Serial PD Bytes Written during
Production

128 80

Total Number of Bytes in Serial PD device

256

Fundamental Memory Type

SDRAM DDR

Number of Row Addresses on Assembly

Number of Column Addresses on Assembly

Number of DIMM Bank

Data Width of Assembly

X64

Data Width of Assembly (cont')

X64

Voltage Interface Level of this Assembly

SSTL 2.5V

DDR SDRAM Device Cycle Time at CL=2.5

6ns

DDR SDRAM Device Access Time from Clock
at CL=2.5

0.7ns 70

11 DIMM

Configuration

Type

Non-Parity

12 Refresh

Rate/Type

SR/1x(7.8

µs) 82

Primary DDR SDRAM Width

Error Checking DDR SDRAM Device Width

N/A

DDR SDRAM Device Attr: Min CLK Delay,
Random Col Access

1 Clock

DDR SDRAM Device Attributes:
Burst Length Supported

2,4,8 0E

DDR SDRAM Device Attributes: Number of
Device Banks

4 04

DDR SDRAM Device Attributes: CAS Latencies
Supported

2/2.5 0C

DDR SDRAM Device Attributes: CS Latency

DDR SDRAM Device Attributes: WE Latency

21 DDR

SDRAM

Device

Attributes: Differential

Clock 20

DDR SDRAM Device Attributes: General

+/-0.2V Voltage Tolerance

Minimum Clock Cycle at CL=2

7.5ns

Maximum Data Access Time from Clock at
CL=2

0.7ns 70

Minimum Clock Cycle Time at CL=1

N/A

Maximum Data Access Time from Clock at
CL=1

N/A 00

Minimum Row Precharge Time (t

) 18ns

Minimum Row Active to Row Active delay
(t

RRD

)

12ns 30

Minimum RAS to CAS delay (t

RCD

) 18ns

Minimum RAS Pulse Width (t

RAS

) 42ns

Module Bank Density

256MB

Address and Command Setup Time Before
Clock

0.75ns 75

Address and Command Hold Time After Clock

0.75ns

Data Input Setup Time Before Clock

0.45ns

Data Input Hold Time After Clock

0.45ns

36-61 Reserved

Undefined

62 SPD

Revision

Initial

63 Checksum

Data

REV 1.1

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© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT512D64S8HABG
512MB : 64M x 64
PC2700 Unbuffered DIMM

Absolute Maximum Ratings

Symbol

Parameter

Rating

Units

, V

OUT

Voltage on I/O pins relative to Vss

-0.5 to V

DDQ

+0.5

Voltage on Input relative to Vss

-0.5 to +3.6

Voltage on VDD supply relative to Vss

-0.5 to +3.6

DDQ

Voltage on VDDQ supply relative to Vss

-0.5 to +3.6

Operating Temperature (Ambient)

0 to+70

STG

Storage Temperature (Plastic)

-55 to +150

Power

Dissipation

OUT

Short Circuit Output Current

50 mA

Note

: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is

stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Capacitance

Parameter

Symbol Max. Units Notes

Input Capacitance: CK0, CK0, CK1, CK1, CK2, CK2

24 pF 1

Input Capacitance: A0-A12, BA0, BA1, WE, RAS, CAS

60 pF 1

Input Capacitance: CKE0, CKE1, S0, S1

30 pF 1

Input Capacitance: SA0-SA2, SCL

9 pF 1

Input/Output Capacitance DQ0-63; DQS0-7, 9-16

IO1

14 pF 1,

Input/Output Capacitance: SDA

IO3

11 pF

1. V

DDQ

= V

= 2.5V ± 0.2V, f = 100 MHz, T

= 25

C, V

OUT

(DC) = V

DDQ

/2, V

OUT

(Peak to Peak) = 0.2V.

2. DQS inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at

the board level.

REV 1.1

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NT512D64S8HABG
512MB : 64M x 64
PC2700 Unbuffered DIMM

DC Electrical Characteristics and Operating Conditions

(TA = 0 °C ~ 70 °C; V

DDQ

= 2.5V ± 0.2V; V

= 2.5V ± 0.2V, See AC Characteristics)

Symbol Parameter Min

Max

Units

Notes

Supply Voltage

2.3

2.7

DDQ

I/O Supply Voltage

2.3

2.7

SS,

SSQ

Supply Voltage, I/O Supply Voltage

REF

I/O Reference Voltage

0.49 x

DDQ

0.51

DDQ

V 1,

I/O Termination Voltage (System)

REF

0.04

REF

+ 0.04

1, 3

IH (DC)

Input High (Logic1) Voltage

REF

+ 0.15

DDQ

+ 0.3

IL (DC)

Input Low (Logic0) Voltage

-0.3

REF

- 0.15

IN (DC)

Input Voltage Level, CK and CK Inputs

-0.3

DDQ

+ 0.3

ID (DC)

Input Differential Voltage, CK and CK Inputs

0.30

DDQ

+ 0.6

1, 4

Input Leakage Current

Any input 0V

DD;

(All other pins not under test = 0V)

-10 10

Output Leakage Current

(DQs are disabled; 0V

out

DDQ

-10 10

Output High Current

OUT =

DDQ

-0.373V, min V

REF,

min V

TT)

-16.8 -

Output Low Current

OUT

= 0.373, max V

REF,

max V

TT)

16.8 -

1. Inputs are not recognized as valid until V

REF

stabilizes.

2. V

REF

is expected to be equal to 0.5 V

DDQ

of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak

noise on V

REF

may not exceed 2% of the DC value.

3. V

is not applied directly to the DIMM. V

is a system supply for signal termination resistors, is expected to be set equal to V

REF,

and must track variations in the DC level of V

REF

4. V

is the magnitude of the difference between the input level on CK and the input level on CK.

REV 1.1

08/2002

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT512D64S8HABG
512MB : 64M x 64
PC2700 Unbuffered DIMM

AC Characteristics

(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating
Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.)
1. All voltages referenced to V

2. Tests for AC timing, I

, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but

the related specifications and device operation are guaranteed for the full voltage range specified.

3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.
4. AC timing and I

tests may use a V

to V

swing of up to 1.5V in the test environment, but input timing is still referenced to V

REF

(or

to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use
conditions. The minimum slew rate for the input signals is 1V/ns in the range between V

IL (AC)

and V

IH (AC)

unless otherwise specified.

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the

signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW
(HIGH) level.

AC Output Load Circuits

Timing Reference Point

50 ohms

30 pF

Output

OUT

AC Operating Conditions

(TA = 0 °C ~ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)

Symbol

Parameter/Condition

Min

Max

Unit

Notes

IH (AC)

Input High (Logic 1) Voltage.

REF

+ 0.31

1, 2

IL (AC)

Input Low (Logic 0) Voltage.

REF

- 0.31

1, 2

ID (AC)

Input Differential Voltage, CK and CK Inputs

0.62

DDQ

+ 0.6

1-3

IX (AC)

Input Differential Pair Cross Point Voltage, CK and CK Inputs

(0.5*V

DDQ)

- 0.2

(0.5*V

DDQ)

+ 0.2

1, 2, 4

1. Input slew rate = 1V/ ns.
2. Inputs are not recognized as valid until V

REF

stabilizes.

3. V

is the magnitude of the difference between the input level on CK and the input level on CK.

4. The value of V

is expected to equal 0.5*V

DDQ

of the transmitting device and must track variations in the DC level of the same.

REV 1.1

08/2002

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT512D64S8HABG
512MB : 64M x 64
PC2700 Unbuffered DIMM

Operating, Standby, and Refresh Currents

(TA

= 0 °C ~ 70 °C; V

DDQ

= 2.5V ± 0.2V; V

= 2.5V ± 0.2V, See AC Characteristics)

Symbol

Parameter/Condition

PC2700

Unit

Notes

DD0

Operating Current : one bank; active / precharge; t

= t

RC (MIN)

;

= t

CK (MIN)

; DQ, DM, and DQS inputs changing twice per clock cycle;

address and control inputs changing once per clock cycle

1160 mA 1,

DD1

Operating Current : one bank; active / read / precharge; Burst = 2;
t

= t

RC (MIN)

; CL=2.5; t

= t

CK (MIN)

; I

OUT

= 0mA;

address and control inputs changing once per clock cycle

TBD mA 1,

DD2P

Precharge Power-Down Standby Current :
all banks idle; power-down mode; CKE

IL (MAX)

; t

= t

CK (MIN)

400 mA 1,

DD2N

Idle Standby Current :

IH (MIN)

; all banks idle; CKE

IH(MIN)

;

= t

CK (MIN)

; address and control inputs changing once per clock cycle

560 mA 1,

DD3P

Active Power-Down Standby Current : one bank active;
power-down mode; CKE

IL (MAX)

; t

= t

CK (MIN)

400 mA 1,

DD3N

Active Standby Current : one bank; active / precharge; CS

IH (MIN)

;

CKE

IH (MIN)

; t

= t

RAS (MAX)

; t

= t

CK (MIN)

; DQ, DM, and DQS

inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle

960 mA 1,

DD4R

Operating Current :

one bank; Burst = 2; reads; continuous burst;

address and control inputs changing once per clock cycle;
DQ and DQS outputs changing twice per clock cycle; CL = 2.5;
t

= t

CK (MIN)

; I

OUT

= 0mA

1800 mA 1,

DD4W

Operating Current : one bank; Burst = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
DQ and DQS inputs changing twice per clock cycle; CL=2.5;
t

= t

CK (MIN)

1680 mA 1,

= t

RFC (MIN)

2400 mA 1,

DD5

Auto-Refresh Current :

= 7.8 µs

264

1, 2, 4

DD6

Self-Refresh Current : CKE

0.2V

48 mA

1-3

DD7

Operating Current: four bank; four bank interleaving with BL = 4, address
and control inputs randomly changing; 50% of data changing at every
transfer; t

= t

(min); I

OUT

= 0mA.

TBD mA 1

1. I

specifications are tested after the device is properly initialized.

2. Input slew rate = 1V/ ns.
3. Enables on-chip refresh and address counters.
4. Current at 7.8 µs is time averaged value of I

DD5

at t

RFC (MIN)

and I

DD2P

over 7.8 µs.

REV 1.1

08/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT512D64S8HABG
512MB : 64M x 64
PC2700 Unbuffered DIMM

AC Timing Specifications for DDR SDRAM Devices Used on Module

(TA = 0 °C ~ 70 °C; V

DDQ

= 2.5V ± 0.2V; V

= 2.5V ± 0.2V, See AC Characteristics)

(Part 1 of 2)

-6

Symbol Parameter

Min. Max.

Unit

Notes

DQ output access time from CK/CK -0.7

+0.7

1-4

DQSCK

DQS output access time from CK/CK -0.7

+0.7

1-4

CK high-level width

0.45

0.55

1-4

CK low-level width

0.45

0.55

1-4

CL=2.5

1-4

Clock cycle time

CL=2 7.5

1-4

DQ and DM input hold time

0.45

1-4, 15, 16

DQ and DM input setup time

0.45

1-4, 15, 16

DIPW

DQ and DM input pulse width (each input)

1.75

1-4

Data-out high-impedance time from CK/CK -0.7

+0.7

1-5

Data-out low-impedance time from CK/CK -0.7

+0.7

1-5

DQSQ

DQS-DQ skew (DQS & associated DQ signals)

0.4

1-4

DQSQA

DQS-DQ skew (DQS & all DQ signals)

0.4

1-4

Minimum half clk period for any given cycle;
defined by clk high (t

) or clk low (t

) time

min

CH,

CL)

1-4

QHS

Data Hold Skew Factor

0.55

Data output hold time from DQS

- t

QHS

1-4

DQSS

Write command to 1st DQS latching transition

0.75

1.25

1-4

DQSL,H

DQS input low (high) pulse width (write cycle)

0.35

1-4

DSS

DQS falling edge to CK setup time (write cycle)

0.2

1-4

DSH

DQS falling edge hold time from CK (write cycle)

0.2

1-4

MRD

Mode register set command cycle time

1-4

WPRES

Write preamble setup time

1-4, 7

WPST

Write

postamble

0.40

0.60 t

1-4, 6

WPRE

Write

preamble

0.25

1-4

Address and control input hold time (fast slew
rate)

0.75

2-4, 9, 11,

Address and control input setup time (fast slew
rate)

0.75

2-4, 9, 11,

Address and control input hold time (slow slew
rate)

0.8

2-4, 10-12,

Address and control input setup time (slow slew
rate)

0.8

2-4, 10-12,

REV 1.1

08/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT512D64S8HABG
512MB : 64M x 64
PC2700 Unbuffered DIMM

AC Timing Specifications for DDR SDRAM Devices Used on Module

(TA = 0 °C ~ 70 °C; V

DDQ

= 2.5V ± 0.2V; V

= 2.5V ± 0.2V, See AC Characteristics)

(Part 2 of 2)

-6

Symbol Parameter

Min. Max.

Unit

Notes

IPW

Input pulse width

2.2

2-4, 12

RPRE

Read

preamble

0.9

1.1 t

1-4

RPST

Read

postamble

0.40 0.60 t

1-4

RAS

Active to Precharge command

120,000

1-4

Active to Active/Auto-refresh command period

1-4

RFC

Auto-refresh to Active/Auto-refresh command
period

1-4

RCD

Active to Read or Write delay

1-4

RAP

Active to Read Command with Auto-precharge

1-4

Precharge command period

1-4

RRD

Active bank A to Active bank B command

1-4

Write recovery time

1-4

DAL

Auto precharge write recovery + recharge time

) +

)

1-4, 13

WTR

Internal write to read command delay

1-4

XSNR

Exit self-refresh to non-read command

1-4

XSRD

Exit self-refresh to read command

200

1-4

REFI

Average Periodic Refresh Interval

7.8

µs

1-4, 8

REV 1.1

08/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT512D64S8HABG
512MB : 64M x 64
PC2700 Unbuffered DIMM

AC Timing Specification Notes

1. Input slew rate = 1V/ns.
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for

signals other than CK/CK is V

REF

3. Inputs are not recognized as valid until V

REF

stabilizes.

4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V

TT.

5. t

and t

transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a

specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system

performance (bus turnaround) degrades accordingly.

7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid

transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in
progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW,
or transitioning from high to low at this time, depending on tDQSS.

8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device.
9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between V

(AC) and V

(AC).

10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between V

(AC) and V

(AC).

11. CK/CK slew rates are >= 1.0 V/ns.
12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by

design or tester characterization.

13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t CK is equal to the actual system

clock cycle time. For example, for PC2100 at CL= 2.5, t DAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5.

14. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew rate is below 0.5 V/ns.

Input Slew Rate

Delta (tIS

)

Delta

(tIH

)

Unit

Note

0.5 V/ns

1, 2

0.4 V/ns

+50

1, 2

0.3 V/ns

+100

1, 2

1. Input slew rate is based on the lesser of the slew rates determined by either V

IH (AC)

to V

IL (AC)

or V

IH (DC)

to V

IL (DC),

similarly

for rising transitions.

2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.

15. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below 0.5 V/ns.

Input Slew Rate

Delta (tDS

)

Delta

(tDH

)

Unit

Note

0.5 V/ns

1, 2

0.4 V/ns

+75

1, 2

0.3 V/ns

+150

1, 2

1. I/O slew rate is based on the lesser of the slew rates determined by either V

IH (AC)

to V

IL (AC)

or V

IH (DC)

to V

IL (DC),

similarly for

rising transitions.

2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.

16. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH in the case where DQ, DM, and DQS slew rates differ.

Delta Rise and Fall Rate

Delta (tDS

)

Delta

(tDH

)

Unit

Note

0.0 ns/V

1-4

0.25 ns/V

+50

1-4

0.5 ns/V

+100

1-4

1. Input slew rate is based on the lesser of the slew rates determined by either V

IH (AC)

to V

IL (AC)

or V

IH (DC)

to V

IL (DC),

similarly

for rising transitions.

2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.
3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]

For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V
Using the table above, this would result in an increase in t

and t

of 100 ps.

4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each

device.

REV 1.1

08/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: NT512D64S8HABG-6

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: NT512D64S8HABG-6