1998
Document No. D16161EJ1V0DS00 (1st edition)
Date Published April 2002 N CP(K)
Printed in Japan
COMPOUND TRANSISTOR
AA1F4Z
on-chip resistor NPN silicon epitaxial transistor
For mid-speed switching
DATA SHEET
2002
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
FEATURES
On-chip bias resistor
(R
1
= 22 k
)
Complementary transistor with AN1F4Z
ABSOLUTE MAXIMUM RATINGS (Ta = 25
C)
Parameter
Symbol
Ratings
Unit
Collector to base voltage
V
CBO
60
V
Collector to emitter voltage
V
CEO
50
V
Emitter to base voltage
V
EBO
5
V
Collector current (DC)
I
C(DC)
100
mA
Collector current (Pulse)
I
C(pulse)
*
200
mA
Total power dissipation
P
T
250
mW
Junction temperature
T
j
150
C
Storage temperature
T
stg
-55 to +150
C
* PW
10 ms, duty cycle 50 %
PACKAGE DRAWING (UNIT: mm)
ELECTRICAL CHARACTERISTICS (Ta = 25
C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Collector cutoff current
I
CBO
V
CB
= 50 V, I
E
= 0
100
nA
DC current gain
h
FE1
**
V
CE
= 5.0 V, I
C
= 5.0 mA
135
330
600
-
DC current gain
h
FE2
**
V
CE
= 5.0 V, I
C
= 50 mA
100
290
-
Collector saturation voltage
V
CE(sat)
**
I
C
= 5.0 mA, I
B
= 0.25 mA
0.04
0.2
V
Low level input voltage
V
IL
**
V
CE
= 5.0 V, I
C
= 100
A
0.55
0.5
V
High level input voltage
V
IH
**
V
CE
= 0.2 V, I
C
= 5.0 mA
3.0
1.05
V
Input resistance
R
1
15.4
22
28.6
k
Turn-on time
t
on
0.2
s
Storage time
t
stg
5.0
s
Turn-off time
t
off
V
CC
= 5.0 V, R
L
= 1.0 k
V
I
= 5.0 V, PW = 2.0
s
duty cycle
2 %
6.0
s
** Pulse test PW
350
s, duty cycle 2 %
h
FE
CLASSIFICATION
Marking
Q
P
K
h
FE1
135 to 270
200 to 400
300 to 600
AA1F4Z
M8E 00. 4
The information in this document is current as of July, 2001. The information is subject to change
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