NEC Electronics Inc.

CMOS-8L

3-VOLT, 0.50-MICRON
CMOS GATE ARRAYS

Preliminary

October 1993

Description

NEC's 3-volt CMOS-8L family consists of ultra-high per-
formance, sub-micron gate arrays, targeted for
applications requiring extensive integration and high
speeds. The device processing includes a true 3-volt,
0.5-micron (drawn) silicon-gate CMOS technology and
two or three-layer metalization. This technology features
channelless (sea-of-gates) architecture with an internal
gate delay of 131 ps (F/O = 1; L = 0 mm).

The µPD658xx series of 3-volt devices consists of 30
masters, offered in densities of 11K gates to 627K gates.
Usable gates range from 6,547 to 439,129 gates. These
gate arrays are ideal for use in engineering workstations,
high-end PCs, mainframes and LAN products, where
extensive integration and high speed are primary design
goals. CMOS-8L gate arrays are also well-suited for all
battery-operated applications where high performance
and low-power consumption are critical; and feasible
only with a truly optimized 3-volt CMOS process.

The µPD658xx series are fully supported by NEC's
advanced ASIC design technology. NEC's OpenCAD

integration system lets the designer choose the most
powerful design tools and services available.

Features

Internal gate delays of 131 ps (F/O = 1; L = 0 mm)

Channelless, 0.50 µm CMOS architecture

Power (typ.) = 1.24 (3.3V) = 0.80 (3.0V)

Process technology designed for 3V operation

I/Os interface directly to 5V logic

48mA GTL I/O buffers are in development

Phase Locked Loop (PLL) for chip-to-chip
clock synchronization in development

Automated generation of clock network for skew

minimization

High pad to gate ratio optimizes silicon usage

Fully configurable high-speed RAM compiler

Advanced package options include TAB/QFP,

TQFP, PQFP, PGA and TAB

Libraries characterized at 3V±10% and 3.3V±0.3V

Variable output drive: 3, 6, 9, 12, 18, 24 or 48 mA

Slew-rate controlled output buffers

Figure 1. Various CMOS-8L Packages

Features (Cont'd)

Supports scan test methodology

Powerful block library with more than 500 macros

Single/Dual-Port RAM and ROM memory blocks

® OpenCAD is a registered trademark of NEC Electronics Inc.

Table 1 Gate Array Sizes

Device

µPD658xx

Available Usable Gates

Total

2LM

3LM

Gates

2LM

3LM

Pads

-40

-60

10,912

6,547

7,638

164

-41

-61

20,832

12,499

14,582

204

-42

-62

30,192

18,115

21,134

212

-43

-63

40,592

24,355

28,414

244

-45

-65

52,528

31,516

36,769

276

-46

-66

61,904

37,142

43,332

300

-48

-68

81,984

49,190

57,388

340

-49

-69

102,272

61,363

71,590

380

-50

-70

120,768

72,460

84,537

412

-51

-71

148,256

88,953

103,779

452

-52

-72

202,752

121,651

141,926

524

-53

-73

255,744

153,446

179,020

588

-55

-75

342,000

205,200

239,400

676

-58

-78

488,720

293,232

342,104

804

-59

-79

627,328

376,396

439,129

908

Notes: 1. Actual gate utilitization varies on circuit implementation.

Utilization is 70% for 3-layer metal; 60% for 2-layer metal.

2. Depending on package and circuit specification, some pads

used for V

and GND are unavailable as signal pads.

70140-2

CMOS-8L

Figure 3. Cell Configured as a Two-Input NAND

Circuit Architecture

CMOS-8L products are built with NEC's 0.50-micron
(drawn) channelless gate array architecture. As shown in
figure 2, CMOS gate array chips are divided into I/O and
internal cell areas. The I/O cell area contains input and
output buffers that isolate the internal cells from high-
energy external signals. The internal cell area is an array
of basic cells, each composed of two p-channel MOS
transistors and two n-channel MOS transistors, as well
as four additional n-channel MOS transistors for
compact RAM design. A cell configured as a two-input
NAND gate is shown in figure 3. These p-channel and
n-channel transistors are sized to offer a superb ratio of
speed to silicon area.

Output Slew-Rate Selection

Fast rise and fall times of CMOS output buffers can
cause system noise and signal overshoot. When an
unterminated line is being driven by a buffer, the
maximum line length is determined by the rise and fall
time of the output buffers and the round-trip signal delay
of the line.

As a general rule, the round-trip delay of the line should
not exceed the rise or fall time of the driving signal.
Transmission lines that are longer than those deter-
mined by this rule can degrade system performance due
to reflections and ringing. One benefit of slew-rate
output buffers is that longer interconnections on a PC
board and routing flexibility are possible.

ASIC designers, therefore, can slow down the output
edge-rate by using a slew-rate output buffer and thus
accomodate longer transmission lines on PC boards.

Slew-rate buffers also inject less noise into the internal
power and ground busses of the device, than their non-
slew-rate counterparts. As a consequence, slew-rate
buffers require fewer power/ground pairs for simul-
taneous switching outputs.

Packaging and Test

CMOS-8L gate arrays support automatic test generation
through a scan-test methodology, which allows higher
fault coverage, easier testing and quicker development
time. NEC also offers advanced packaging solutions
including (butt-lead) PGAs and flat packages. These
packages give CMOS-8L devices a distinct performance
edge in high-integration applications.

Publications

This data sheet contains preliminary specifications,
package information, and operational data for the
CMOS-8L gate array families. Additional design
information will be available in NEC's CMOS-8L Block
Library and CMOS-8L Design Manual. Contact your
local NEC Design Center or the NEC Literature Center
for further ASIC design information; see the back of this
data sheet for locations and phone numbers.

Figure 2. Chip Layout and Internal Cell

Configuration

O = A · B

Internal
Cell Area

I/O Cell
Area

Basic Cell

83DC-6225A

N-Channel

P-Channel

RAM

Logic

CMOS-8L

Recommended Operating Conditions

= 3.3V ± 0.3V

Parameter

Symbol

Min

Max

Unit

Power supply voltage

2.7

3.6

Ambient temperature

+85

°C

Low-level input voltage, 3V

0.3 V

High-level input voltage, 3V

0.7 V

Low-level input voltage, 5V

0.8

High-level input voltage, 5V

2.2

Input rise or fall time

, t

200

Input rise or fall time, Schmitt

, t

Positive Schmitt-trigger voltage

TBD

Negative Schmitt-trigger voltage

TBD

Hysteresis voltage

TBD

Input/Output Capacitance

= V

= 0 V; f = 1 MHz

Terminal

Symbol

Typ

Max

Unit

Input

Output

OUT

I/O

Note: (1) Values include package pin capacitance.

Absolute Maximum Ratings

Power supply voltage, V

0.5 to +4.6 V

3V interface I/O voltage, V

, V

0.5 V to V

+ 0.5 V

5V interface I/O voltage, V

, V

0.5 V to V

+ 3.0 V

Latch-up current, I

LATCH

>1 A (typ)

Operating temperature, T

OPT

40 to +85°C

Storage temperature, T

STG

65 to +150°C

Caution: Exposure to absolute maximum ratings for extended
periods may affect device reliability; exceeding the ratings could cause
permanent damage. The device should not be operated outside the
recommended operating conditions.

Power Consumption at V

= 3.3V ± 0.3V

Description

Limits

Unit

Internal cell

1.24

µW/MHz

Input block (FI01)

10.0

µW/MHz

Output block

0.181

mW/MHz

AC Characteristics at V

= 3.3V ± 0.3V; T

= 40°C to +125°C

Parameter

Symbol

Min

Typ

Max

Unit

Conditions

Toggle frequency

TOG

175

MHz

D -F/F; F/O = 2

Delay time, 2-input NAND gate

Standard gate (F302)

131

F/O = 1; L = 0 mm

243

F/O = 2; L = 1 mm

Low power gate (L302)

149

F/O = 1; L = 0 mm

371

F/O = 2; L = 1 mm

Delay time, buffer

Input (FI01)

276

F/O = 1; L = 0 mm @ V

= 3.3 V

Output (FO06)

1.45

= 15 pF @ V

= 3.3V

Output rise time (FO06)

1.1

= 15 pF @ V

= 3.3V

Output fall time (FO06)

1.1

= 15 pF @ V

= 3.3V

CMOS-8L

DC Characteristics at V

= 3.3V ± 0.3V

= 3.3 V ± 0.3 V or 3 V ± 10%; T

= 40°C to +125°C

Parameter

Symbol

Min

Typ

Max

Unit

Conditions

Quiescent current (Note 1)

TBD

µA

= V

or GND

Input leakage current

Regular

-5

µA

= V

or GND

50 k

pull-up

TBD

µA

= GND

5 k

pull-up

TBD

= GND

50 k

pull-down

TBD

µA

= V

Off-state output leakage current

TBD

µA

= V

or GND

Input clamp voltage

TBD

= 18 mA

Output short circuit current (Note 2)

TBD

= 0 V

Low-level output current, 3V buffers

3 mA

= 0.4 V

6 mA

= 0.4 V

9 mA

= 0.4 V

12 mA

= 0.4 V

18 mA

= 0.4 V

24 mA

= 0.4 V

48 mA

= 0.4 V

Low-level output current, 5V buffers

3 mA

= 0.4 V

6 mA

= 0.4 V

9 mA

= 0.4 V

12 mA

= 0.4 V

18 mA

= 0.4 V

High-level output current, 3V buffers

3 mA

-3

= 2.4 V

6 mA

-6

= 2.4 V

9 mA

-9

= 2.4 V

12 mA

-12

= 2.4 V

18 mA

-18

= 2.4 V

24 mA

-24

= 2.4 V

48 mA

-48

= 2.4 V

High-level output current, 5V buffers

3 mA

-3

= 2.4 V

6 mA

-3

= 2.4 V

9 mA

-3

= 2.4 V

12 mA

-6

= 2.4 V

18 mA

-6

= 2.4 V

Low-level output voltage, 3V and 5V

0.1

= 0 mA

High-level output voltage, 3V and 5V

0.1

= -0.2 mA

Notes:

(1)

The maximum value reflects the use of pull-up/pull-down resistors and oscillator blocks. Contact an NEC ASIC Design Center for
assistance in calculation.

(2)

Rating is for only one output operating in this mode for less than 1 second.

CMOS-8L

Recommended Operating Conditions

= 3.0V ± 10%

Parameter

Symbol

Min

Max

Unit

Power supply voltage

2.7

3.6

Ambient temperature

+85

°C

Low-level input voltage,3V

0.3 V

High-level input voltage,3V

0.7 V

Low-level input voltage,5V

0.8

High-level input voltage,5V

2.2

Input rise or fall time

, t

200

Input rise or fall time, Schmitt

, t

Positive Schmitt-trigger voltage

TBD

Negative Schmitt-trigger voltage

TBD

Hysteresis voltage

TBD

Power Consumption at V

= 3.0V ± 10%

Description

Limits

Unit

Internal cell

0.80

µW/MHz

Input block (FI01)

8.0

µW/MHz

Output block

0.164

mW/MHz

Absolute Maximum Ratings

Power supply voltage, V

0.5 to +4.6 V

3V interface I/O voltage, V

, V

0.5 V to V

+ 0.5 V

5V interface I/O voltage, V

0.5 V to V

+ 3.0 V

Latch-up current, I

LATCH

>1 A (typ)

Operating temperature, T

OPT

40 to +85°C

Storage temperature, T

STG

65 to +150°C

Input/Output Capacitance

= V

= 0 V; f = 1 MHz

Terminal

Symbol

Typ

Max

Unit

Input

Output

OUT

I/O

AC Characteristics at V

= 3.0V ± 10%; T

= 40°C to +125°C

Parameter

Symbol

Min

Typ

Max

Unit

Conditions

Toggle frequency

TOG

175

MHz

D -F/F; F/O = 2

Delay time, 2-input NAND gate

Standard gate (F302)

147

F/O = 1; L = 0 mm

272

F/O = 2; L = 1 mm

Low power gate (L302)

167

F/O = 1; L = 0 mm

416

F/O = 2; L = 1 mm

Delay time, buffer

Input (FI01)

309

F/O = 1; L = 0 mm @ V

= 3.0 V

Output (FO06)

1.62

= 15 pF @ V

= 3.0V

Output rise time (FO06)

TBD

= 15 pF @ V

= 3.0V

Output fall time (FO06)

TBD

= 15 pF @ V

= 3.0V

CMOS-8L

DC Characteristics at V

= 3.0V± 10%

= 3.3V ± 0.3V or 3V ± 10%; T

= 40°C to +125°C

Parameter

Symbol

Min

Typ

Max

Unit

Conditions

Quiescent current (Note 1)

TBD

µA

= V

or GND

Input leakage current

Regular

-5

µA

= V

or GND

50 k

pull-up

TBD

µA

= GND

5 k

pull-up

TBD

= GND

50 k

pull-down

TBD

µA

= V

Off-state output leakage current

TBD

µA

= V

or GND

Input clamp voltage

TBD

= 18 mA

Output short circuit current (Note 2)

TBD

= 0 V

Low-level output current, 3V buffers

3 mA

= 0.4 V

6 mA

= 0.4 V

9 mA

= 0.4 V

12 mA

= 0.4 V

18 mA

= 0.4 V

24 mA

= 0.4 V

48 mA

= 0.4 V

Low-level output current, 5V buffers

3 mA

= 0.4 V

6 mA

= 0.4 V

9 mA

= 0.4 V

12 mA

= 0.4 V

18 mA

= 0.4 V

High-level output current, 3V buffers

3 mA

-3

= 2.4 V

6 mA

-6

= 2.4 V

9 mA

-9

= 2.4 V

12 mA

-12

= 2.4 V

18 mA

-18

= 2.4 V

24 mA

-24

= 2.4 V

48 mA

-48

= 2.4 V

High-level output current, 5V buffers

3 mA

-2

= 2.2 V

6 mA

-2

= 2.2 V

9 mA

-2

= 2.2 V

12 mA

-4

= 2.2 V

18 mA

-4

= 2.2 V

Low-level output voltage, 3V and 5V

0.1

= 0 mA

High-level output voltage, 3V

0.1

= 0 mA

High-level output voltage, 5V

0.2

= 0 mA

Notes: (1) The maximum value reflects the use of pull-up/pull-down resistors and oscillator blocks. Contact an NEC ASIC Design Center for

assistance.

(2) Rating is for only one output operating in this mode for less than 1 second.

CMOS-8L

Table 2 CMOS-8 Package Options

Master Slice µPD65xxx

Maximum

Package Dimensions

-840

-841

-842

-843

-845

-846

-848

I/O Pins

Body Size Pitch

Height

-860

-861

-862

-863

-865

-866

-868

Plastic Quad Flatpack (PQFP)

120-pin

28 mm

0.8 mm

3.7 mm

136-pin

28 mm

0.65 mm 3.7 mm

160-pin

28 mm

0.65 mm 3.7 mm

160-pin (H/S)

28 mm

0.65 mm 3.2 mm

184-pin

32 mm

0.65 mm 3.2 mm

Plastic Quad Flatpack (PQFP-FP)

100-pin

14 mm

0.5 mm

1.45 mm

120-pin

20 mm

0.5 mm

2.7 mm

144-pin

20 mm

0.5 mm

2.7 mm

160-pin

24 mm

0.5 mm

2.7 mm

160-pin (H/S)

24 mm

0.5 mm

2.7 mm

176-pin

24 mm

0.5 mm

2.7 mm

176-pin (H/S)

24 mm

0.5 mm

2.7 mm

208-pin

28 mm

0.5 mm

3.2 mm

208-pin (H/S)

28 mm

0.5 mm

3.2 mm

240-pin

32 mm

0.5 mm

3.2 mm

256-pin

28 mm

0.4 mm

3.2 mm

272-pin

36 mm

0.5 mm

3.2 mm

304-pin

40 mm

0.5 mm

3.7 mm

Thin Quad Flatpack (TQFP) PRELIMINARY

64-pin

10 mm

0.5 mm

1.0 mm

80-pin

12 mm

0.5 mm

1.05 mm

100-pin

14 mm

0.5 mm

1.0 mm

120-pin

14 mm

0.4 mm

1.0 mm

144-pin

20 mm

0.5 mm

1.4 mm

160-pin

24 mm

0.5 mm

1.4 mm

176-pin

24 mm

0.5 mm

1.4 mm

208-pin

28 mm

0.5 mm

1.4 mm

Ceramic Pin Grid Array (CPGA)

72-pin

1.1 in.

100 mils 4.57 mm

132-pin

1.4 in.

100 mils 4.57 mm

176-pin

1.5 in.

100 mils 4.57 mm

208-pin

1.7 in.

100 mils 5.08 mm

280-pin

1.9 in.

100 mils 4.57 mm

364-pin

1.7 in.

50 mils

3.0 mm

Ceramic Pin Grid Array (CPGA) Butt-Lead

288-pin

1.1 in.

50 mils

5.58 mm

528-pin

1.9 in.

50 mils

10.6 mm

Notation: A = Available; P = Planned; D = In Development; "" = Unavailable; H/S = Heat Spreader.
Note: NEC reserves the right to alter the package plan based on the results of qualification. For current package availability, please contact
your local NEC Design Center.

CMOS-8L

Table 2 CMOS-8 Package Options (cont)

Master Slice µPD65xxx

Maximum

Package Dimensions

-849

-850

-851

-852

-853

-855

-858

-859

I/O Pins

Body Size

Pitch

Height

-869

-870

-871

-872

-873

-875

-878

-879

Plastic Quad Flatpack (PQFP)

120-pin

28 mm

0.8 mm

3.7 mm

136-pin

28 mm

0.65 mm 3.7 mm

160-pin

28 mm

0.65 mm 3.7 mm

160-pin (H/S)

28 mm

0.65 mm 3.2 mm

184-pin

32 mm

0.65 mm 3.2 mm

Plastic Quad Flatpack (PQFP-FP)

100-pin

14 mm

0.5 mm

1.45 mm

120-pin

20 mm

0.5 mm

2.7 mm

144-pin

20 mm

0.5 mm

2.7 mm

160-pin

24 mm

0.5 mm

2.7 mm

160-pin (H/S)

24 mm

0.5 mm

2.7 mm

176-pin

24 mm

0.5 mm

2.7 mm

176-pin (H/S)

24 mm

0.5 mm

2.7 mm

208-pin

28 mm

0.5 mm

3.2 mm

208-pin (H/S)

28 mm

0.5 mm

3.2 mm

240-pin

32 mm

0.5 mm

3.2 mm

256-pin

28 mm

0.4 mm

3.2 mm

272-pin

36 mm

0.5 mm

3.2 mm

304-pin

40 mm

0.5 mm

3.7 mm

Thin Quad Flatpack (TQFP) PRELIMINARY

64-pin

10 mm

0.5 mm

1.0 mm

80-pin

12 mm

0.5 mm

1.05 mm

100-pin

14 mm

0.5 mm

1.0 mm

120-pin

14 mm

0.4 mm

1.0 mm

144-pin

20 mm

0.5 mm

1.4 mm

160-pin

24 mm

0.5 mm

1.4 mm

176-pin

24 mm

0.5 mm

1.4 mm

208-pin

28 mm

0.5 mm

1.4 mm

Ceramic Pin Grid Array (CPGA)

72-pin

1.1 in.

100 mils 4.57 mm

132-pin

1.4 in.

100 mils 4.57 mm

176-pin

1.5 in.

100 mils 4.57 mm

208-pin

1.7 in.

100 mils 5.08 mm

280-pin

1.9 in.

100 mils 4.57 mm

364-pin

1.7 in.

50 mils

3.0 mm

Ceramic Pin Grid Array (CPGA) Butt-Lead

288-pin

1.1 in.

50 mils

5.58 mm

528-pin

1.9 in.

50 mils

10.6 mm

CMOS-8L

their design effort at a higher level of abstraction, specify-
ing, modeling, and simulating their designs at a systems
level. This leaves the details of the gate-level implementa-
tion to the synthesis tools. After verification confirms the
design's functionality, designers are then free to explore
various functional and architectural trade-offs, and can
optimize chip performance while minimizing chip area. An
engineer can evaluate several architectures and select the
best solution before committing the design to silicon.

The more traditional method of design entry, schematic
capture, figure 5, is available with a wide variety of third-
party tools. The supported tools are described in Table 3,
and provide the designer with a productive way to manage
the hierarchical elements of a CMOS-8 design, utilizing the
macro symbol library provided by NEC. For those design-
ers who are experienced and already well-versed with
graphical design entry, this provides an efficient migration
path for ASIC development.

One of the key benefits of NEC's ASIC design flow is that post
place-and-route simulation can be accomplished at the
customer's site, since NEC offers designers a choice of
simulators within the "golden simulator" category. Golden
simulator status means that upon receiving post place-and-
route simulation results from a customer, NEC can then
proceed directly to photomask production, bypassing any
additional post-simulation steps. This can save a lot of time.

NEC's ASIC Design System

NEC supports its ASIC products with a comprehensive
CAD system that significantly reduces the time and ex-
pense usually associated with the development of semi-
custom devices. Designers can choose from today's most
popular third-party software tools, shown in the table on the
adjacent page. NEC's OpenCAD

Design System is a

front-end to back-end ASIC design package that merges
several advanced CAE/CAD tools into a single structure.
Designers can now choose a single CAE platform, or mix
and match tools from a variety of third-party vendors. The
design flow combines tools for floorplanning, logic synthe-
sis, automatic test generation, accelerated fault-grading,
full timing simulation, and advanced place-and-route algo-
rithms. This flexible design environment thereby ensures
accurate, on schedule designs.

There are two basic methods for design entry, the first is by
HDL specification, figure 4; the second is via schematic
capture, figure 5. Note that after the initial EDIF netlist is
generated, there is little difference in the basic design flow
for either method. Figure 6 shows the location of the
CrossCheck tools in the design flow.

A top-down modeling methodology is possible using the
HDL specification approach. Designers can concentrate

Figure 4. HDL Specification Design Flow

HDL Netlist

EDIF 2.0.0

Netlist

DRC

SDF

Gate Level Sim.

Pre P&R Sim.

Post FP Sim.

Post P&R Sim.

Delay

Calculator

Floorplanner

DRC

Tester

CUSTOMER

NEC

Behavioral Sim.

ECO Option

ATPRG

DEF

Fault Simulation

Timing Analyzer

Test Synthesis

ATPG

Test Vector

ATPG

Test Vector

Simulator

Logic Synthesis

HDL

SDF

DEF

Place

CTS

Route

Changed

Netlist

Test

Program

Fabrication

Test

Vector

Test Vector

Output

CMOS-8L

Sample design kits are available at no charge to qualified
users. A software license agreement is required. For more
information, contact your nearest NEC ASIC Design Cen-
ter, listed on the back of this data sheet.

Table 3 Third-Party Supported Tools

The floorplanner tool provides realistic estimates of wire
length by grouping hierarchical blocks into specific physical
locations on the chip. This minimizes critical path intercon-
nect delays for more accurate simulation. The floorplanner
also provides graphical I/O assignment capabilities and
generates a delay file for post-floorplanner simulation.

The ECO (Engineering Change Order) option in figures 4
and 5 allows the designer to make minor corrections in the
design without requiring an entirely new placement and
routing of the device. This tool improves turnaround by
ensuring that relatively small changes, such as connectiv-
ity changes, will not greatly impact the current design
timing.

NEC also incorporates proprietary tools to facilitate the
design process. A single delay calculator is used for all CAE
platforms to ensure consistent timing and simulation re-
sults. A comprehensive design rule check (DRC) program
reports design rule violations as well as chip utilization
statistics for the design netlist. The generated report con-
tains such information as net-count calculation, total pin-
count and cell-count use, and usage rate calculations.
Unused input pins, violations in pin naming conventions
and fan-out limits, are examples of the design rule viola-
tions reported by this program.

Figure 5. Schematic-Based Design Flow

Synthesis

Cadence

Mentor

Viewlogic

Synopsys

IKOS

Zycad

Intelligen

NEC

ATPG

Fault

Simulation

Place

and Route

Floorplanner

Static Timing

Analysis

Simulation

Tools

CAD
Company

Schematic

Entry

Key:

indicates "Golden Simulator" status.

indicates planned support-check with local Design Center for
exact availability.

indicates function is available via software library, and software
support is through third-party vendor.

83YL-9164B

Symbol

Library

Test

Vector

Test Vector

Output

Functional Sim.

Pre P&R Sim.

Post FP Sim.

Post P&R Sim.

Schematic

Capture

EDIF Netlist

Writer

EDIF 2.0.0

Netlist

DRC

Floorplanner

Wire Length

DEF

Changed

Netlist

Test

Program

ATPRG

Tester

CUSTOMER

NEC

Place

CTS

Route

Fabrication

Fault Simulation

Timing Analyzer

Simulator

SDF

Delay

Calculator

SDF

Wire Length

ECO Option

DEF

CMOS-8L

Block Library List

The CMOS-8L family offers a variety of blocks, including
gates, flip-flop circuits, and shift registers. The functions
of these blocks are designed to be compatible with those
of the CMOS-8, CMOS-7 and CMOS-6 families. In
addition, memory blocks such as RAM and ROM will be
provided, and low-power gates are available. The low-
power blocks are designed for gate count reduction; the
number of cells are fewer than that of the standard block,
contributing to lower power consumption and higher
efficiency. Another feature is the I/Os can directly interface
to 5V logic.

Block List

Block

Description

Cells

Name

(mA)

Block

Description

Cells

Name

(mA)

Interface Blocks

3V CMOS Input Buffers

FI01

3V CMOS input

1 (3)

FID1

3V CMOS input, 50 k

pull-down

1 (3)

FIU1

3V CMOS in, 50 k

pull-up

1 (3)

FIW1

3V CMOS in, 5 k

pull-up

1 (3)

FIS1

3V CMOS Schmitt input

1 (8)

FDS1

3V CMOS Schmitt input, 50 k

pull-down

1 (8)

FUS1

3V CMOS Schmitt input, 50 k

pull-up

1 (8)

FWS1 3V CMOS Schmitt input, 5 k

pull-up

1 (8)

FIB1

3V CMOS input, high fanout for clock driver

1 (24)

FDB1

3V CMOS input, high fanout for clock driver,

1 (24)

50 k

pull-down

FUB1

3V CMOSinput, high fanout for clock driver,

1 (24)

50 k

pull-up

FWB1 3V CMOS input, high fanout for clock driver,

1 (24)

5 k

pull-up

3V CMOS Input Buffers without Protection Diode up to V

FIA1

3V CMOS input

1 (3)

FDA1

3V CMOS input, 50 k

pull-down

1 (3)

FUA1

3V CMOS input, 50 k

pull-up

1 (3)

FWA1 3V CMOS input, 5 k

pull-up

1 (3)

FIE1

3V CMOS Schmitt input

1 (8)

FDE1

3V CMOS Schmitt input, 50 k

pull-down

1 (8)

FUE1

3V CMOS Schmitt input, 50 k

pull-up

1 (8)

FWE1 3V CMOS Schmitt input, 5 k

pull-up

1 (8)

FIH1

3V CMOS input, high fanout for clock driver

1 (24)

FDH1

3V CMOS input, high fanout for clock driver,

1 (24)

50 k

pull-down

FUH1

3V CMOS input, high fanout for clock driver,

1 (24)

50 k

pull-up

FWH1 3V CMOSinput, high fanout for clock driver,

1 (24)

5 k

pull-up

5V CMOS Input Buffers

FIV1

5V CMOS input

1 (3)

FDV1

5V CMOS input, 50 k

pull-down

1 (3)

FIF1

5V CMOS Schmitt input

1 (8)

FDF1

5V CMOS Schmitt input, 50 k

pull-down

1 (8)

FIG1

5V CMOS input, high fanout for clock driver

1 (24)

FDG1

5V CMOS input, high fanout for clock driver,

1 (24)

50 k

pull-down

Interface Blocks (Cont.)

3V CMOS Output Buffers

FO0A

3V CMOS output

1.0

1 (4)

FO0B

3V CMOS output

2.0

1 (4)

FO09

3V CMOS output

3.0

1 (4)

FO04

3V CMOS output

6.0

1 (4)

FO01

3V CMOS output

9.0

1 (4)

FO02

3V CMOS output

12.0

1 (4)

FO03

3V CMOS output

18.0

1 (8)

FO06

3V CMOS output

24.0

1 (8)

FO0C

3V CMOS output

48.0

2 (8)

3V CMOS Slew-Rate Output Buffers

FE02

3V CMOS output, low noise

12.0

1 (3)

FE03

3V CMOS output, low noise

18.0

1 (3)

FE06

3V CMOS output, low noise

24.0

1 (3)

FE0C

3V CMOS output, low noise

48.0

2 (3)

5V CMOS Output Buffers

FV0A

5V CMOS output

1.0

1 (4)

FV0B

5V CMOS output

2.0

1 (4)

FV09

5V CMOS output

3.0

1 (4)

FV04

5V CMOS output

6.0

1 (4)

FV01

5V CMOS output

9.0

1 (8)

FV02

5V CMOS output

12.0

2 (8)

FV03

5V CMOS output

18.0

2 (8)

FV06

5V CMOS output

24.0

3 (8)

5V CMOS Slew-Rate Output Buffers

FW02

5V CMOS output, low noise

12.0

2 (3)

FW02

5V CMOS output, low noise

18.0

2 (3)

FW06

5V CMOS output, low noise

24.0

3 (3)

3V CMOS Three-State Output Buffers

B00T

3V CMOS output

3.0

1 (6)

B0DT

3V CMOS output, 50 k

pull-down

3.0

1 (6)

B0UT

3V CMOS output, 50 k

pull-up

3.0

1 (6)

B0WT 3V CMOS output, 5 k

pull-up

3.0

1 (6)

B00E

3V CMOS output

6.0

1 (6)

B0DE

3V CMOS output, 50 k

pull-down

6.0

1 (6)

B0UE

3V CMOS output, 50 k

pull-up

6.0

1 (6)

B0WE 3V CMOS output, 5 k

pull-up

6.0

1 (6)

B008

3V CMOS output

9.0

1 (6)

B0D8

3V CMOS output, 50 k

pull-down

9.0

1 (6)

B0U8

3V CMOS output, 50 k

pull-up

9.0

1 (6)

B0W8 3V CMOS output, 5 k

pull-up

9.0

1 (6)

B007

3V CMOS output

12.0

1 (6)

B0D7

3V CMOS output, 50 k

pull-down

12.0

1 (6)

B0U7

3V CMOS output, 50 k

pull-up

12.0

1 (6)

B0W7 3V CMOS output, 5 k

pull-up

12.0

1 (6)

B009

3V CMOS output

18.0

1 (9)

B0D9

3V CMOS output, 50 k

pull-down

18.0

1 (9)

B0U9

3V CMOS output, 50 k

pull-up

18.0

1 (9)

B0W9 3V CMOS output, 5 k

pull-up

18.0

1 (9)

B00H

3V CMOS output

24.0

1 (9)

B0DH 3V CMOS output, 50 k

pull-down

24.0

1 (9)

B0UH 3V CMOS output, 50 k

pull-up

24.0

1 (9)

B0WH 3V CMOS output, 5 k

pull-up

24.0

1 (9)

Note: Number of internal cells required is shown in parentheses.

CMOS-8L

Block

Description

Cells

Name

(mA)

Block

Description

Cells

Name

(mA)

Interface Blocks (Cont.)

Note: Number of internal cells required is shown in parentheses.

* Indicates I

3V CMOS Three-State Output Buffers (Cont.)

B00J

3V CMOS output

48.0

2 (9)

B0DJ

3V CMOS output, 50 k

pull-down

48.0

2 (9)

B0UJ

3V CMOS output, 50 k

pull-up

48.0

2 (9)

B0WJ

3V CMOS output, 5 k

pull-up

2 (9)

3V CMOS Slew-Rate Three-State Output Buffers

BE07

3V CMOS output

12.0

1 (5)

BED7

3V CMOS output, 50 k

pull-down

12.0

1 (5)

BEU7

3V CMOS output, 50 k

pull-up

12.0

1 (5)

BEW7 3V CMOS output, 5 k

pull-up

12.0

1 (5)

BE09

3V CMOS output

18.0

1 (5)

BED9

3V CMOS output, 50 k

pull-down

18.0

1 (5)

BEU9

3V CMOS output, 50 k

pull-up

18.0

1 (5)

BEW9 3V CMOS output, 5 k

pull-up

18.0

1 (5)

BE0H

3V CMOS output

24.0

1 (5)

BEDH 3V CMOS output, 50 k

pull-down

24.0

1 (5)

BEUH 3V CMOS output, 50 k

pull-up

24.0

1 (5)

BEWH 3V CMOS output, 5 k

pull-up

24.0

1 (5)

BE0J

3V CMOS output

48.0

2 (5)

BEDJ

3V CMOS output, 50 k

pull-down

48.0

2 (5)

BEUJ

3V CMOS output, 50 k

pull-up

48.0

2 (5)

BEWJ 3V CMOS output, 5 k

pull-down

48.0

2 (5)

5V CMOS Three-State Output Buffers

BV0Q

5V CMOS output

1.0

1 (16)

BVDQ 5V CMOS output, 50 k

pull-down

1.0

1 (16)

BV0M 5V CMOS output

2.0

1 (16)

BVDM 5V CMOS output, 50 k

pull-down

2.0

1 (16)

BV0T

5V CMOS output

3.0

1 (16)

BVDT 5V CMOS output, 50 k

pull-down

3.0

1 (16)

BVOE 5V CMOS output

6.0

1 (16)

BVDE 5V CMOS output, 50 k

pull-down

6.0

1 (16)

BV08

5V CMOS output

9.0

1 (19)

BVD8

5V CMOS output, 50 k

pull-down

9.0

1 (19)

BV07

5V CMOS output

12.0

2 (19)

BVD7

5V CMOS output, 50 k

pull-down

12.0

2 (19)

BV09

5V CMOS output

18.0

2 (19)

BVD9

5V CMOS output, 50 k

pull-down

18.0

2 (19)

BV0H

5V CMOS output

24.0

3 (19)

BVDH 5V CMOS output, 50 k

pull-down

24.0

3 (19)

5V CMOS Slew-Rate Three-State Output Buffers

BY07

5V CMOS output

12.0 2 (15)

BYD7

5V CMOS output, 50 k

pull-down

12.0 2 (15)

BY09

5V CMOS output

18.0 2 (15)

BYD9

5V CMOS output, 50 k

pull-down

18.0 2 (15)

BY0H

5V CMOS ouputt

24.0 3 (15)

BYDH 5V CMOS output, 50 k

pull-down

24.0 3 (15)

3V CMOS Open Drain Output Buffers

EXTH 3V N-ch open drain

3.0

1 (4)

EXUH 3V N-ch open drain, 50 k

pull-up

3.0

1 (4)

EXWH 3V N-ch open drain, 5 k

pull-up

3.0

1 (4)

EXTJ

3V N-ch open drain

6.0

1 (4)

EXUJ

3V N-ch open drain, 50 k

pull-up

6.0

1 (4)

EXWJ 3V N-ch open drain, 5 k

pull-up

6.0

1 (4)

3V CMOS Open Drain Output Buffers (Cont.)

EXT1

3V N-ch open drain

9.0

1 (4)

EXT3

3V N-ch open drain, 50 k

pull-up

9.0

1 (4)

EXW3 3V N-ch open drain, 5 k

pull-up

9.0

1 (4)

EXT9

3V N-ch open drain

12.0

1 (4)

EXTB

3V N-ch open drain, 50 k

pull-up

12.0

1 (4)

EXWB 3V N-ch open drain, 5 k

pull-up

12.0

1 (4)

EXT5

3V N-ch open drain

18.0

1 (8)

EXT7

3V N-ch open drain, 50 k

pull-up

18.0

1 (8)

EXW7 3V N-ch open drain, 5 k

pull-up

18.0

1 (8)

EXTD 3V N-ch open drain

24.0

1 (8)

EXTF

3V N-ch open drain, 50 k

pull-up

24.0

1 (8)

EXWF 3V N-ch open drain, 5 k

pull-up

24.0

1 (8)

EXTL

3V N-ch open drain

48.0

2 (2)

EXUL

3V N-ch open drain, 50 k

pull-up

48.0

2 (8)

EXWL 3V N-ch open drain, 5 k

pull-up

48.0

2 (8)

EXTQ 3V P-ch open drain

*3.0

1 (4)

EXDQ 3V P-ch open drain, 50 k

pull-down

*3.0

1 (4)

EXTR 3V P-ch open drain

*6.0

1 (4)

EXDR 3V P-ch open drain, 50 k

pull-down

*6.0

1 (4)

EXT2

3V P-ch open drain

*9.0

1 (4)

EXT4

3V P-ch open drain, 50 k

pull-down

*9.0

1 (4)

EXTA

3V P-ch open drain

*12.0

1 (4)

EXTC 3V P-ch open drain, 50 k

pull-down

*12.0

1 (4)

EXT6

3V P-ch open drain

*18.0

1 (4)

EXT8

3V P-ch open drain, 50 k

pull-down

*18.0

1 (4)

EXTE

3V P-ch open drain

*24.0

1 (8)

EXTG 3V P-ch open drain, 50 k

pull-down

*24.0

1 (8)

EXTS

3V P-ch open drain

*48.0

2 (8)

EXDS 3V P-ch open drain, 50 k

pull-down

*48.0

2 (8)

3V CMOS Slew-Rate Open Drain Output Buffers

EET9

3V N-ch open drain

12.0

1 (2)

EETB

3V N-ch open drain, 50 k

pull-up

12.0

1 (2)

EEWB 3V N-ch open drain, 50 k

pull-up

12.0

1 (2)

EET5

3V N-ch open drain

18.0

1 (2)

EET7

3V N-ch open drain, 50 k

pull-up

18.0

1 (2)

EEW7 3V N-ch open drain, 5 k

pull-up

18.0

1 (2)

EETD 3V N-ch open drain

24.0

1 (2)

EETF

3V N-ch open drain, 50 k

pull-up

24.0

1 (2)

EEWF 3V N-ch open drain, 5 k

pull-up

24.0

1 (2)

EETL

3V N-ch open drain

48.0

2 (2)

EEUL

3V N-ch open drain, 50 k

pull-up

48.0

2 (2)

EEWL 3V N-ch open drain, 5 k

pull-up

48.0

2 (2)

EETA

3V P-ch open drain

*12.0

1 (2)

EETC 3V P-ch open drain, 50 k

pull-down

*12.0

1 (2)

EET6

3V P-ch open drain

*18.0

1 (2)

EET8

3V P-ch open drain, 50 k

pull-down

*18.0

1 (2)

EETE

3V P-ch open drain

*24.0

1 (2)

EETG 3V P-ch open drain, 50 k

pull-down

*24.0

1 (2)

EETS

3V P-ch open drain

*48.0

2 (2)

EEDS 3V P-ch open drain, 50 k

pull-down

*48.0

2 (2)

CMOS-8L

Block

Description

Cells

Name

(mA)

Block

Description

Cells

Name

(mA)

Interface Blocks (Cont.)

5V CMOS Open Drain Output Buffers

EVTH 5V N-ch open drain

3.0

1 (4)

EVTJ

5V N-ch open drain

6.0

1 (4)

EVT1

5V N-ch open drain

9.0

1 (8)

EVT9

5V N-ch open drain

12.0

1 (8)

EVT5

5V N-ch open drain

18.0

2 (8)

EVTD 5V N-ch open drain

24.0

2 (8)

5V CMOS Slew-Rate Output Buffers

EYT9

5V N-ch open drain

12.0

1 (2)

EYT5

5V N-ch open drain

18.0

2 (2)

EYTD 5V N-ch open drain

24.0

2 (2)

3V CMOS Bi-Directional Output Buffers

B00U

CMOS input, CMOS 3-state output

3.0

1 (9)

B0DU CMOS input, CMOS 3-state out, 50 k

pull-down

3.0

1 (9)

B0UU CMOS input, CMOS 3-state out, 50 k

pull-up

3.0

1 (9)

B0WU CMOS input, CMOS 3-state out, 5 k

pull-up

3.0

1 (9)

B00C

CMOS input, CMOS 3-state output

6.0

1 (9)

B0DC CMOS input, CMOS 3-state out, 50 k

pull-down

6.0

1 (9)

B0UC CMOS input, CMOS 3-state out, 50 k

pull-up

6.0

1 (9)

B0WC CMOS input, CMOS 3-state out, 5 k

pull-up

6.0

1 (9)

B003

CMOS inut, CMOS 3-state output

9.0

1 (8)

B0D3

CMOS input, CMOS 3-state out, 50 k

pull-down

9.0

1 (8)

B0U3

CMOS input, CMOS 3-state out, 50 k

pull-up

9.0

1 (8)

B0W3 CMOS in, CMOS 3-state out, 5 k

pull-up

9.0

1 (8)

B001

CMOS input, CMOS 3-state out

12.0

1 (9)

B0D1

CMOS input, CMOS 3-state out, 50 k

pull-down

12.0

1 (9)

B0U1

CMOS input, CMOS 3-state out, 50 k

pull-up

12.0

1 (9)

B0W1 CMOS input, CMOS 3-state out, 5 k

pull-up

12.0

1 (9)

B005

CMOS input, CMOS 3-state out

18.0 1 (12)

B0D5

CMOS input, CMOS 3-state out, 50 k

pull-down

18.0 1 (12)

B0U5

CMOS input, CMOS 3-state out, 50 k

pull-up

18.0 1 (12)

B0W5 CMOS input, CMOS 3-state out, 5 k

pull-up

18.0 1 (12)

B00F

CMOS input, CMOS 3-state out

24.0 1 (12)

B0DF

CMOS input, CMOS 3-state out, 50 k

pull-down

24.0 1 (12)

B0UF

CMOS input, CMOS 3-state out, 50 k

pull-up

24.0 1 (12)

B0WF CMOS input, CMOS 3-state out, 5 k

pull-up

24.0 1 (12)

B00W CMOS input, CMOS 3-state output

48.0 2 (12)

B0DW CMOS input, CMOS 3-state output,

48.0 2 (12)

50 k

pull-down

B0UW CMOS input, CMOS 3-state out,

48.0 2 (12)

50 k

pull-up resistor

B0WW CMOS input, CMOS 3-state output,

48.0 2 (12)

5 k

pull-up resistor

BSIU

CMOS Schmitt input, CMOS 3-state ouput

3.0 1 (14)

BSDU CMOS Schmitt input, CMOS 3-state output,

3.0 1 (14)

50 k

pull-down

BSUU CMOS Schmitt input, CMOS 3-state out,

3.0 1 (14)

50 k

pull-up

BSWU CMOS Schmitt input, CMOS 3-state output,

3.0 1 (14)

5 k

pull-up

BSIC

CMOS Schmitt input, CMOS 3-state output

6.0 1 (14)

BSDC CMOS Schmitt input, CMOS 3-state output,

6.0 1 (14)

50 k

pull-down

BSUC CMOS Schmitt input, CMOS 3-state output,

6.0 1 (14)

50 k

pull-up

BSWC CMOS Schmitt input, CMOS 3-state output,

6.0 1 (14)

5 k

pull-up

Interface Blocks (Cont.)

3V CMOS Bi-Directional Output Buffers

BSI3

CMOS Schmitt input, CMOS 3-state output

9.0 1 (14)

BSD3

CMOS Schmitt input, CMOS 3-state output,

9.0 1 (14)

50 k

pull-down

BSU3

CMOS Schmitt input, CMOS 3-state output,

9.0 1 (14)

50 k

pull-up

BSW3 CMOS Schmitt input, CMOS 3-state output,

9.0 1 (14)

5 k

pull-up

3V CMOS Three-State I/O Buffers

BSI1

CMOS Schmitt input, CMOS 3-state output

12.0 1 (14)

BSD1

CMOS Schmitt input, CMOS 3-state output,

12.0 1 (14)

50 k

pull-down

BSU1

CMOS Schmitt input, CMOS 3-state output,

12.0 1 (14)

50 k

pull-up

BSW1 CMOS Schmitt input, CMOS 3-state output,

12.0 1 (14)

5 k

pull-up

BSI5

CMOS Schmitt input, CMOS 3-state output

18.0 1 (17)

BSD5

CMOS Schmitt input, CMOS 3-state output,

18.0 1 (17)

50 k

pull-down

BSU5

CMOS Schmitt input, CMOS 3-state output,

18.0 1 (17)

50 k

pull-up

BSW5 CMOS Schmitt input, CMOS 3-state output,

18.0 1 (17)

5 k

pull-up

BSIF

CMOS Schmitt input, CMOS 3-state output

24.0 1 (17)

BSDF CMOS Schmitt input, CMOS 3-state output,

24.0 1 (17)

50 k

pull-down

BSUF

CMOS Schmitt input, CMOS 3-state output,

24.0 1 (17)

50 k

pull-up

BSWF CMOS Schmitt input, CMOS 3-state output,

24.0 1 (17)

5 k

pull-up

BSIW

CMOS Schmitt input, CMOS 3-state output

48.0 2 (17)

BSDW CMOS Schmitt input, CMOS 3-state output,

48.0 2 (17)

50 k

pull-down

BSUW CMOS Schmitt input, CMOS 3-state output,

48.0 2 (17)

50 k

pull-up

BSWW CMOS Schmitt input, CMOS 3-state output,

48.0 2 (17)

5 k

pull-up

3V CMOS Slew-Rate Three-State Output Buffers

BE01

CMOS input, CMOS 3-state output

12.0

1 (8)

BED1

CMOS input, CMOS 3-state output, 50 k

pull-dn

12.0

1 (8)

BEU1

CMOS input, CMOS 3-state output, 50 k

pull-up

12.0

1 (8)

BEW1 CMOS input, CMOS 3-state output, 5 k

pull-up

12.0

1 (8)

BE05

CMOS input, CMOS 3-state output

18.0

1 (8)

BED5

CMOS input, CMOS 3-state output, 50 k

pull-dn

18.0

1 (8)

BEU5

CMOS input, CMOS 3-state output, 50 k

pull-up

18.0

1 (8)

BEW5 CMOS input, CMOS 3-state output, 5 k

pull-up

18.0

1 (8)

BE0F

CMOS input, CMOS 3-state output

24.0

1 (8)

BEDF CMOS input, CMOS 3-state output, 50 k

pull-dn

24.0

1 (8)

BEUF CMOS input, CMOS 3-state output, 50 k

pull-up

24.0

1 (8)

BEWF CMOS input, CMOS 3-state output, 5 k

pull-up

24.0

1 (8)

BE0W CMOS input, CMOS 3-state output

48.0

2 (8)

BEDW CMOS input, CMOS 3-state output, 50 k

pull-dn

48.0

2 (8)

BEUW CMOS input, CMOS 3-state output, 50 k

pull-up

48.0

2 (8)

BEWW CMOS input, CMOS 3-state output, 5 k

pull-up

48.0

2 (8)

Note: Number of internal cells required is shown in parentheses.

CMOS-8L

Block

Description

Cells

Name

(mA)

Block

Description

Cells

Name

(mA)

BFI1

CMOS Schmitt input, CMOS 3-state output,

12.0 1 (13)

BFD1

CMOS Schmitt input, CMOS 3-state output,

12.0 1 (13)

50 k

pull-down

BFU1

CMOS Schmitt input, CMOS 3-state output,

12.0 1 (13)

50 k

pull-up

BFW1 CMOS Schmitt input, CMOS 3-state output,

12.0 1 (13)

5 k

pull-up

BFI5

CMOS Schmitt input, CMOS 3-state output

18.0 1 (13)

BFD5

CMOS Schmitt input, CMOS 3-state output,

18.0 1 (13)

50 k

pull-down

BFU5

CMOS Schmitt input, CMOS 3-state output,

18.0 1 (13)

50 k

pull-up

BFW5 CMOS Schmitt input, CMOS 3-state output,

18.0 1 (13)

5 k

pull-up

BFIF

CMOS Schmitt input, CMOS 3-state output,

24.0 1 (13)

BFDF

CMOSSchmitt input, CMOS 3-state output,

24.0 1 (13)

50 k

pull-down

BFUF

CMOS Schmitt input, CMOS 3-state output,

24.0 1 (13)

50 k

pull-up

BFWF CMOS Schmitt input, CMOS 3-state output,

24.0 1 (13)

5 k

pull-up

BFIW

CMOS Schmitt input, CMOS 3-state output,

48.0 2 (13)

BFDW CMOS Schmitt input, CMOS 3-state output,

48.0 2 (13)

50 k

pull-down

BFUW CMOS Schmitt input, CMOS 3-state output,

48.0 2 (13)

50 k

pull-up

BFWW CMOS Schmitt input, CMOS 3-state output,

48.0 2 (13)

5 k

pull-up

5V CMOS Bi-Directional Output Buffers

BW0X 5V CMOS input / CMOS 3-state output

1.0 1 (19)

BWDX 5V CMOS input / CMOS 3-state output,

1.0 1 (19)

with 50K pull-down

BW0K 5V CMOS input / CMOS 3-state output

2.0 1 (19)

BWDK 5V CMOS input / CMOS 3-state output,

2.0 1 (19)

with 50K

pull-down

BW0U 5V CMOS input / CMOS 3-state output

3.0 1 (19)

BWDU 5V CMOS input / CMOS 3-state output,

3.0 1 (19)

with 50K

pull-down

BW0C 5V CMOS input / CMOS 3-state output

6.0 1 (19)

BWDC 5V CMOS input / CMOS 3-state output,

6.0 1 (19)

with 50K

pull-down

BW03 5V CMOS input / CMOS 3-state output

9.0 1 (22)

BWD3 5V CMOS input / CMOS 3-state output,

9.0 1 (22)

with 50K

pull-down

BW01 5V CMOS input / CMOS 3-state output

12.0 2 (22)

BWD1 5V CMOS input / CMOS 3-state output,

12.0 2 (22)

with 50K

pull-down

BW05 5V CMOS input / CMOS 3-state output

18.0 2 (22)

BWD5 5V CMOS input/ CMOS 3-state output,

18.0 2 (22)

with 50K

pull-down

BW0F 5V CMOS input/ CMOS 3-state output,

24.0 3 (22)

BWDF 5V CMOS input/ CMOS 3-state output,

24.0 3 (22)

with 50K

pull-down

3V CMOS Slew-Rate Three-State Output Buffers (Cont.)

BKIX

5V CMOS Schmitt input, CMOS 3-state output

1.0 1 (24)

BKDX

5V CMOS Schmitt input,

1.0 1 (24)

CMOS 3-state output, 50 k

pull-down

BKIK

5V CMOS Schmitt input, CMOS 3-state output

2.0 1 (24)

BKDK

5V CMOS Schmitt input,

2.0 1 (24)

CMOS 3-state output, 50k

pull-down

BKIU

5V CMOS Schmitt input, CMOS 3-state output

3.0 1 (24)

BKDU 5V CMOS Schmitt input,

3.0 1 (24)

CMOS 3-state output, 50 k

pull-down

BKIC

5V CMOS Schmitt in, CMOS 3-state output

6.0 1 (24)

BKDC 5V CMOS Schmitt input,

6.0 1 (24)

CMOS 3-state out, 50 k

pull-down resistor

BKI3

5V CMOS Schmitt input, CMOS 3-state output

9.0 1 (27)

BKD3

5V CMOS Schmitt input,

9.0 1 (24)

CMOS 3-state output, 50 k

pull-down

BKI1

5V CMOS Schmitt input, CMOS 3-state output

12.0 2 (27)

BKD1

5V CMOS Schmitt input,

12.0 2 (27)

CMOS 3-state output, 50k

pull-down

BKI5

5V CMOS Schmitt input, CMOS 3-state output

18.0 2 (27)

BKD5

5V CMOS Schmitt input,

18.0 2 (27)

CMOS 3-state output, 50 k

pull-down resistor

BKIF

5V CMOS Schmitt input, CMOS 3-state output

24.0 3 (27)

BKDF 5V CMOS Schmitt input,

24.0 3 (27)

CMOS 3-state output, 50 k

pull-down

5V CMOS Slew-Rate Bi-Directional Output Buffers

BX01

5V CMOS input / CMOS 3-state output

12.0 2 (18)

BXD1

5V CMOS input / CMOS 3-state output,

12.0 2 (18)

with 50K

pull-down

BX05

5V CMOS input / CMOS 3-state output

18.0 2 (18)

BXD5

5V CMOS input / CMOS 3-state output,

18.0 2 (18)

with 50K

pull-down

BX0F

5V CMOS input / CMOS 3-state output

24.0 3 (18)

BXDF 5V CMOS input / CMOS 3-state output,

24.0 3 (18)

with 50K

pull-down

BZI1

5V CMOS Schmitt input, CMOS 3-state output

12.0 2 (23)

BZD1

5V CMOS Schmitt in, CMOS 3-state

12.0 2 (23)

output, 50k

pull-down

BZI5

5V CMOS Schmitt input, CMOS 3-state output

18.0 2 (23)

BZD5

5V CMOS Schmitt input, CMOS 3-state

18.0 2 (23)

output, 50 k

pull-down

BZ1F

5V CMOS Schmitt input, CMOS 3-state output

24.0 3 (23)

BZDF

5V CMOS Schmitt input, CMOS 3-state

24.0 3 (23)

output, 50 k

pull-down

Interface Blocks (Cont.)

5V CMOS Bi-Directional Output Buffers (Cont.)

Note: Number of internal cells required is shown in parentheses.

CMOS-8L

Note: Number of internal cells required is shown in parentheses.

Interface Blocks

Function Blocks Normal Power

Inverters

F101

Inverter (F/O = 17)

F102

Inverter (F/O = 37)

F103

Inverter (F/O = 60)

F104

Inverter (F/O = 92)

F108

Inverter (F/O = 160)

Buffers

F111

Non-inverting buffer (F/O = 17)

F112

Non-inverting buffer (F/O = 35)

F113

Non-inverting buffer (F/O = 54)

F114

Non-inverting buffer (F/O = 74)

F118

Non-inverting buffer (F/O = 180)

NOR Gates

F202

2-input NOR

F203

3-input NOR

F204

4-input NOR

F205

5-input NOR

F206

6-input NOR

F208

8-input NOR

F222

2-input NOR, power

F223

3-input NOR, power

F224

4-input NOR, power

OR Gates

F212

2-input OR

F213

3-input OR

F214

4-input OR

F215

5-input OR

F216

6-input OR

F232

2-input OR, power

F233

3-input OR, power

F234

4-input OR, power

NAND Gates

F302

2-input NAND

F303

3-input NAND

F304

4-input NAND

F305

5-input NAND

F306

6-input NAND

F308

8-input NAND

F322

2-input NAND, power

F323

3-input NAND, power

F324

4-input NAND, power

AND Gates

F312

2-input AND

F313

3-input AND

F314

4-input AND

F315

5-input AND

F316

6-input AND

F332

2-input AND, power

F333

3-input AND, power

F334

4-input AND, power

AND-NOR Gates

F421

2-wide 1-2-input AND-OR inverter

F422

3-wide 1-1-2-input AND-OR inverter

F423

2-wide 1-3-input AND-OR inverter

F424

2-wide 2-2-input AND-OR inverter

F425

3-wide 2-2-2-input AND-OR inverter

F426

2-wide 3-3-input AND-OR inverter

F429

4-wide 2-2-2-2-input AND-OR inverter

F442

2-wide 4-4-input AND-OR inverter

F462

3-wide 1-2-3-input AND-OR inverter

OR-NAND Gates

F431

2-wide 1-2-input OR-AND inverter

F432

3-wide 1-1-2-input OR-AND inverter

F433

2-wide 1-3-input OR-AND inverter

F434

2-wide 2-2-input OR-AND inverter

F435

2-wide 2-3-input OR-AND inverter

F436

2-wide 3-3-input OR-AND inverter

F454

4-wide 2-2-2-2-input OR-AND inverter

Clock Drivers

FCK1

Clock driver (F/O = 360)

FCK2

Clock driver (F/O = 720)

FCK3

Clock driver (F/O = 1080)

120

FCK4

Clock driver (F/O = 1440)

160

FCK5

Clock driver (F/O = 1800)

200

Exclusive OR Functions

F511

2-input Exclusive-OR

F512

2-input Exclusive-NOR

Parity Generators

F581

8-bit odd parity generator

F582

8-bit even parity generator

Adders

F521

1-bit full-adder

F523

4-bit binary full-adder

F526

Carry look-ahead generator

F527

4-bit full-adder

Miscellaneous

F091

H, L level generator

F093

Interface block for oscillator buffer

Three-state Buffers

F531

3-state buffer with enable

F532

3-state buffer with active low enable

Decoders

F561

2-to-4 decoder

F981

2-to-4 decoder with active low enable

F982

3-to-8 decoder with active low enable

Multiplexers

F569

8-to-1 multiplexer

F570

4-to-1 multiplexer

F571

2-to-1 multiplexer

F572

Quad 2-to-1 multiplexer

Block

Description

Cells

Name

Block

Description

Cells

Name

CMOS-8L

Latches

F595

R-S latch

F601

D-latch

F602

D-latch with reset

F603

D-latch with reset low

F604

D-latch with active low gate (G)

F605

D-latch with active low gate (G), reset low

F901

4-bit D-latch, buffered output

F902

8-bit D-latch, buffered output

Flip-Flops

F596

Synchronous R-S F/F with set-reset

F611

D-F/F

F614

D-F/F with set-reset

F615

D-F/F with reset low

F616

D-F/F with set low

F617

D-F/F with set-reset low

F631

D-F/F active low clock

F637

D-F/F active low clock with set-reset low

F641

D-F/F, buffered output

F644

D-F/F with set-reset, buffered output

F647

D-F/F with set-reset low, buffered output

F661

D-F/F active low clock, buffered output

F667

D-F/F active low clock with set-reset low,

buffered output

F714

Toggle F/F with set-reset

F717

Toggle F/F with set-reset low

F737

Toggle low F/F with set-reset low

F744

Toggle F/F with set-reset, buffered output

F747

Toggle F/F with set-reset low, buffered output

F767

Toggle active low F/F with set-reset low,

buffered output

F771

J-K F/F, buffered output

F774

J-K F/F with set-reset, buffered output

F777

J-K F/F with set-reset low, buffered output

F781

J-K F/F active low clock, buffered output

F787

J-K F/F active low clock with set-reset low,

buffered output

F791

Toggle F/F with set-reset and toggle enable

F792

Toggle active low F/F with set-reset low and toggle

enable low

F922

4-bit D-F/F with reset

F924

4-bit D-F/F

Shift Registers

F911

4-bit shift register with reset

F912

4-bit serial/parallel shift register

F913

4-bit serial/parallel shift register with reset low

F914

4-bit shift register

F915

4-bit shift register w/direct load low, buffered output

Counters

F961

4-bit synchronous binary up counter with reset low,

load low, buffered output

F962

4-bit synchronous binary up counter with reset low

F963

4-bit presettable synchronous up/down binary counter

(dual clock with clear)

F964

4-bit presettable synchronous up/down binary counter

Comparator

F985

4-bit magnitude comparator

Scan

S000

Scan path D-F/F with set-reset

S002

Scan path D-F/F

S050

Scan path D-F/F with set-reset, hold

S052

Scan path D-F/F with hold

S100

Scan path J-K F/F with set-reset

S102

Scan path J-K F/F

S150

Scan path J-K F/F with set-reset, hold

S152

Scan path J-K F/F with hold

S201

Scan path D-latch with reset

S202

Scan path D-latch

S301

Scan path D-latch with reset

S302

Scan path D-latch

S999

Scan path 2-to-1 data selector

Delays

F130

Delay block (for monostable multivibrator)

F131

Delay gate

F132

Delay gate

Function Blocks Low Power

Inverter

L101

Inverter

Buffer

L111

Non-inverting buffer

NOR Gates

L202

2-input NOR

L203

3-input NOR

L204

4-input NOR

OR Gates

L212

2-input OR

L213

3-input OR

L214

4-input OR

NAND Gates

L302

2-input NAND

L303

3-input NAND

L304

4-input NAND

L305

5-input NAND

L306

6-input NAND

AND Gates

L312

2-input AND

L313

3-input AND

L314

4-input AND

AND-NOR Gates

L421

2-wide 1-2-input AND-OR inverter

L422

3-wide 1-1-2-input AND-OR inverter

L423

2-wide 1-3-input AND-OR inverter

L424

2-wide 2-2-input AND-OR inverter

Function Blocks Normal Power (Cont.)

Block

Description

Cells

Name

Block

Description

Cells

Name

CMOS-8L

High-Speed Basic RAM Blocks - Hard Macros

KD49

Single-port RAM (32 word x 4 bit)

578

KD8B

Single-port RAM (64 word x 8 bit)

1712

KD8F

Single-port RAM (256 word x 8 bit)

6070

KDAB

Single-port RAM (64 word x 10 bit)

2020

KDAF

Single-port RAM (256 word x 10 bit)

7292

KE49

Dual-port RAM (32 word x 4 bit)

798

KE87

Dual-port RAM (16 word x 8 bit)

634

KE8B

Dual-port RAM (64 word x 8 bit)

2178

KE8F

Dual-port RAM (256 word x 8 bit)

6408

KEAB

Dual-port RAM (64 word x 10 bit)

2486

KEAF

Dual-port RAM (256 word x 10 bit)

7630

KE9H

Dual-port RAM (512 word x 9 bit)

12682

High-Speed Single Port RAM Blocks - Soft Macros

RJ49

Single-port RAM (32 word x 4 bit)

KD49 RU49

782

RJ4B

Single-port RAM (64 word x 4 bit)

KD49 RU4B

1389

RJ4D

Single-port RAM (128 word x 4 bit)

KD49 RU4D

2572

RJ4F

Single-port RAM (256 word x 4 bit)

KD49 RU4F

4940

RJ89

Single-port RAM (32 word x 8 bit)

KD49 RU89

1392

RJ8B

Single-port RAM (64 word x 8 bit)

KD8B RU8B

1964

RJ8D

Single-port RAM (128 word x 8 bit)

KD8B RU8D

3712

RJ8F

Single-port RAM (256 word x 8 bit)

KD8B RU8F

6354

RJ8H

Single-port RAM (512 word x 8 bit)

KD8B RU8H 12460

RJAB

Single-port RAM (64 word x 10 bit)

KDAB RUAB

2290

RJAD

Single-port RAM (128 word x 10 bit)

KDAB RUAD

4350

RJAF

Single-port RAM (256 word x 10 bit)

KDAB RUAF

7592

RJAH

Single-port RAM (512 word x 10 bit)

KDAB RUAH 14924

RJC9

Single-port RAM (32 word x 16 bit)

KD49 RUC9

2618

RJCB

Single-port RAM (64 word x 16 bit)

KD8B RUCB

3746

RJCD

Single-port RAM (128 word x 16 bit)

KD8B RUCD

7223

RJCF

Single-port RAM (256 word x 16 bit)

KD8B RUCF 12493

RJEB

Single-port RAM (64 word x 20 bit)

KDAB RUEB

4394

RJED

Single-port RAM (128 word x 20 bit)

KDAB RUED

8494

RJEF

Single-port RAM (256 word x 20 bit)

KDAB RUEF 14968

RJH9

Single-port RAM (32 word x 32 bit)

KD49 RUH9

5062

RJHB

Single-port RAM (64 word x 32 bit)

KD8B RUHB

7303

RJHD

Single-port RAM (128 word x 32 bit)

KD8B RUHD 14235

RJKB

Single-port RAM (64 word x 40 bit)

KDAB RUKB

8599

RJKD

Single-port RAM (128 word x 40 bit)

KDAB RUKD 16779

High-Speed Dual Port RAM Blocks - Soft Macros

RK49

Dual-port RAM (32 word x 4 bit)

KE49

RU49

1029

RK4B

Dual-port RAM (64 word x 4 bit)

KE49

RU4B

1866

RK4D

Dual-port RAM (128 word x 4 bit)

KE49

RU4D

3502

RK4F

Dual-port RAM (256 word x 4 bit)

KE49

RU4F

6768

RK87

Dual-port RAM (16 word x 8 bit)

KE87

RU87

885

RK89

Dual-port RAM (32 word x 8 bit)

KE49

RU89

1860

RK8B

Dual-port RAM (64 word x 8 bit)

KE8B RU8B

2463

RK8D

Dual-port RAM (128 word x 8 bit)

KE8B RU8D

4687

RK8F

Dual-port RAM (256 word x 8 bit)

KE8F RU8F

6733

RK8H

Dual-port RAM (512 word x 8 bit)

KE8F RU8H 13187

RKAB

Dual-port RAM (64 word x 10 bit)

KEAB RUAB

2787

RKAD

Dual-port RAM (128 word x 10 bit)

KEAB RUAD

5323

RKAF

Dual-port RAM (256 word x 10 bit)

KEAF RUAF

7971

RKAH

Dual-port RAM (512 word x 10 bit)

KEAF RUAH 15651

Basic

Block

Description

BIST

Cells

RAM

AND-NOR Gates

L425

3-wide 2-2-2-input AND-OR inverter

L426

2-wide 3-3-input AND-OR inverter

L429

4-wide 2-2-2-2-input AND-OR inverter

L442

2-wide 4-4-input AND-OR inverter

L462

3-wide 1-2-3-input AND-OR inverter

OR-NAND Gates

L431

2-wide 1-2-input OR-AND inverter

L432

3-wide 1-1-2-input OR-AND inverter

L433

2-wide 1-3-input OR-AND inverter

L434

2-wide 2-2-input OR-AND inverter

L435

2-wide 2-3-input OR-AND inverter

L436

2-wide 3-3-input OR-AND inverter

L454

4-wide 2-2-2-2-input OR-AND inverter

Exclusive OR Functions

L511

2-input EX-OR

EX-NOR Gate

L512

2-input EX-NOR

Decoders

L561

2-to-4 decoder

L981

2-to-4 decoder with active low enable

L982

3-to-8 decoder with active low enable

Latches

L601

D-latch

L602

D-latch with reset

L603

D-latch with reset low

L604

D-latch with active low gates (G)

L605

D-latch with active low gates (G), reset low

L901

4-bit latch

L902

8-bit latch

Flip-Flops

L611

D-F/F

L614

D-F/F with set-reset

L617

D-F/F with set-reset low

L631

D-F/F with active low clock

L637

D-F/F with active low clock, set-reset low

L714

Toggle-F/F with set-reset

L717

Toggle-F/F with set-reset low

L737

Toggle active low F/F with set-reset low

L922

4-bit D-F/F with reset

L924

4-bit D-F/F

Multiplexer

L571

2-to-1 multiplexer

L572

Quad 2-to-1 multiplexer

Shift Registers

L911

4-bit shift register with reset

L912

4-bit serial/parallel shift register

L913

4-bit serial/parallel in shift register with reset low

L914

4-bit shift register

Function Blocks Low Power (Cont.)

RAM Memory Blocks

Block

Description

Cells

Name

CMOS-8L

RKC9

Dual-port RAM (32 word x 16 bit)

KE49

RUC9

3524

RKCB

Dual-port RAM (64 word x 16 bit)

KE8B

RUCB

4709

RKCD

Dual-port RAM (128 word x 16 bit)

KE8B

RUCD

8127

RKCF

Dual-port RAM (256 word x 16 bit)

KE8F

RUCF 13209

RKEB

Dual-port RAM (64 word x 20 bit)

KEAB

RUEB

5357

RKED

Dual-port RAM (128 word x 20 bit)

KEAB

RUED

1039

RKEF

Dual-port RAM (256 word x 20 bit)

KE49

RUH9 15256

RKH9

Dual-port RAM (32 word x 32 bit)

KE8B

RUHB

6849

RKHB

Dual-port RAM (64 word x 32 bit)

KE8B

RUHD

9198

RKHD

Dual-port RAM (128 word x 32 bit)

KE8B

RUHD 18004

RKKB

Dual-port RAM (64 word x 40 bit)

KEAB

RUKB 10494

RKKD

Dual-port RAM (128 word x 40 bit)

KEAB

RUKD 20548

High-Density Single-Port RAM Blocks - Soft Macros

RB4D

Single-port RAM (128 word x 4 bit)

K14D

RU4D

1315

RB4F

Single-port RAM (256 word x 4 bit)

K14D

RU4F

2423

RB4H

Single-port RAM (512 word x 4 bit)

K14D

RU4H

4610

RB4M

Single-port RAM (1K word x 4 bit)

K14D

RU4M

8986

RB4S

Single-port RAM (2K word x 4 bit)

K14D

RU4S

17754

RB4U

Single-port RAM (4K word x 4 bit)

K14D

RU4U 35172

RB8D

Single-port RAM (128 word x 8 bit)

K14D

RU8D

2472

RB8F

Single-port RAM (256 word x 8 bit)

K18F

RU8F

3978

RB8H

Single-port RAM (512 word x 8 bit)

K18F

RU8H

7711

RB8M

Single-port RAM (1K word x 8 bit)

K18M

RU8M 12523

RB8S

Single-port RAM (2K word x 8 bit)

K18M

RU8S

24770

RBAF

Single-port RAM (256 word x 10 bit)

K1AF

RUAF

4877

RBAH

Single-port RAM (512 word x 10 bit)

K1AF

RUAH

9495

RBAM

Single-port RAM (1K word x 10 bit)

K1AM

RUAM 15499

RBAS

Single-port RAM (2K word x 10 bit)

K1AM

RUAS 30710

RBCD

Single-port RAM (128 word x 16 bit)

K14D

RUCD

4657

RBCF

Single-port RAM (256 word x 16 bit)

K18F

RUCF

7744

RBCH

Single-port RAM (512 word x 16 bit)

K18F

RUCH 15188

RBCM

Single-port RAM (1K word x 16 bit)

K18M

RUCM 24801

RBEF

Single-port RAM (256 word x 20 bit)

K1AF

RUEF

9539

RBEH

Single-port RAM (512 word x 20 bit)

K1AF

RUEH 18756

RBEM

Single-port RAM (1K word x 20 bit)

K1AM

RUHM 30754

RBHD

Single-port RAM (128 word x 32 bit)

K14D

RUHD

9109

RBHF

Single-port RAM (256 word x 32 bit)

K18F

RUHF 15268

RBHH

Single-port RAM (512 word x 32 bit)

K18F

RUHH 30137

RBKF

Single-port RAM (256 word x 40 bit)

K1AF

RUKF 18861

RBKH

Single-port RAM (512 word x 40 bit)

K1AF

RUKH 37273

Basic

Block

Description

BIST

Cells

RAM

Memory Blocks (Cont.)

High-Speed RAM Blocks - Soft Macros (Cont.)

ROM Memory Blocks

Block

Description

Cells

ROM Blocks

J14D

128 word x 4 bit ROM

720

J14F

256 word x 4 bit ROM

1040

J14H

512 word x 4 bit ROM

1512

J14M

1K word x 4 bit ROM

2408

J14S

2K word x 4 bit ROM

3960

J14U

4K word x 4 bit ROM

6776

J18D

128 word x 8 bit ROM

1040

J18F

256 word x 8 bit ROM

1456

J18H

512 word x 8 bit ROM

2352

J18M

1K word x 8 bit ROM

3784

J18S

2K word x 8 bit ROM

6600

J18U

4K word x 8 bit ROM

11704

J18W

8K word x 8 bit ROM

21584

J1CD

128 word x 16 bit ROM

1456

J1CF

256 word x 16 bit ROM

2352

J1CH

512 word x 16 bit ROM

3696

J1CM

1K word x 16 bit ROM

6512

J1CS

2K word x 16 bit ROM

11400

J1CU

4K word x 16 bit ROM

21280

J1HF

256 word x 32 bit ROM

3696

J1HH

512 word x 32 bit ROM

6512

J1HM

1K word x 32 bit ROM

11248

J1HS

2K word x 32 bit ROM

21128

RAM Test (BIST)

RU49

32 word x 4 bit

RU4B

64 word x 4 bit

RU4D

128 word x 4 bit

RU4F

256 word x 4 bit

RU87

16 word x 8 bit

RU89

32 word x 8 bit

RU8B

64 word x 8 bit

RU8D

128 word x 8 bit

RU8F

256 word x 8 bit

RU8H

512 word x 8 bit

RUAB

64 word x 10 bit

RUAD

128 word x 10 bit

RUAF

256 word x 10 bit

RUAH

512 word x 10 bit

RUC9

32 word x 16 bit

RUCB

64 word x 16 bit

RUCD

128 word x 16 bit

RUCF

256 word x 16 bit

RUEB

64 word x 20 bit

RUED

128 word x 20 bit

RUEF

256 word x 20 bit

RUH9

32 word x 32 bit

RUHB

64 word x 32 bit

RUHD

128 word x 32 bit

RUKB

64 word x 40 bit

RUKD

128 word x 40 bit

CMOS-8L

CORPORATE HEADQUARTERS

2880 Scott Boulevard
P.O. Box 58062
Santa Clara, CA 95052
TEL 408-588-6000

For literature, call toll-free 7 a.m. to 6 p.m. Pacific time: 1-800-366-9782

or FAX your request to: 1-800-729-9288

No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics Inc.
(NECEL). The information in this document is subject to change without notice. ALL DEVICES SOLD BY NECEL ARE COVERED BY THE
PROVISIONS APPEARING IN NECEL TERMS AND CONDITIONS OF SALES ONLY. INCLUDING THE LIMITATION OF LIABILITY, WARRANTY,
AND PATENT PROVISIONS. NECEL makes no warranty, express, statutory, implied or by description, regarding information set forth herein
or regarding the freedom of the described devices from patent infringement. NECEL assumes no responsibility for any errors that may
appear in this document. NECEL makes no commitments to update or to keep current information contained in this document. The devices
listed in this document are not suitable for use in applications such as, but not limited to, aircraft control systems, aerospace equipment,
submarine cables, nuclear reactor control systems and life support systems. "Standard" quality grade devices are recommended for
computers, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and
visual equipment, and other consumer products. For automotive and transportation equipment, traffic control systems, anti-disaster and
anti-crime systems, it is recommended that the customer contact the responsible NECEL salesperson to determine the reliabilty
requirements for any such application and any cost adder. NECEL does not recommend or approve use of any of its products in life support
devices or systems or in any application where failure could result in injury or death. If customers wish to use NECEL devices in applications
not intended by NECEL, customer must contact the responsible NECEL sales people to determine NECEL's willingness to support a given
application.

NEC Electronics Inc.

Document No. 70140-2

NEC ASIC DESIGN CENTERS

THIRD-PARTY DESIGN CENTERS

SOUTH CENTRAL/SOUTHEAST

· Koos Technical Services, Inc.

385 Commerce Way, Suite 101
Longwood, FL 32750

TEL

407-260-8727

FAX 407-260-6227

· Integrated Silicon Systems Inc.

2222 Chapel Hill Nelson Highway
Durham, NC 27713

TEL

919-361-5814

FAX 919-361-2019

WEST

· 3033 Scott Boulevard

Santa Clara, CA 95054

TEL 408-588-5008
FAX 408-588-5017

· One Embassy Centre

9020 S.W. Washington Square Road,
Suite 400
Tigard, OR 97223

TEL

503-671-0177

FAX 503-643-5911

SOUTH CENTRAL/SOUTHEAST

· 16475 Dallas Parkway, Suite 380

Dallas, TX 75248

TEL 972-250-4522
FAX 972-931-8680

· Research Triangle Park

2000 Regency Parkway, Suite 455
Cary, NC 27511

TEL 919-460-1890
FAX 919-469-5926

NORTH CENTRAL/NORTHEAST

· One Natick Executive Park

Natick, MA 01760

TEL 508-655-8833
FAX 508-653-2915

· Greenspoint Tower

2800 W. Higgins Road, Suite 765
Hoffman Estates, IL 60195

TEL 708-519-3945
FAX 708-882-7564

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CMOS-8L

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CMOS-8L

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CMOS-8L