1994,1996

DATA SHEET

MOS INTEGRATED CIRCUIT

Description

The

PD485505 is a 5,048 words by 8 bits high speed FIFO (First In First Out) line buffer. Its CMOS static circuitry

provides high speed access and low power consumption.

The

PD485505 can be used for one line delay and time axis conversion in high speed facsimile machines and

digital copiers.

Moreover, the

PD485505 can execute read and write operations independently on an asynchronous basis. Thus

the

PD485505 is suitable as a buffer for data transfer between units with different transfer rates and as a buffer for

the synchronization of multiple input signals. There are three versions, E, K, P, and L. This data sheet can be applied

to the version P and L. These versions operate with different specifications. Each version is identified with its lot

number (refer to 7. Example of Stamping).

Features

5,048 words by 8 bits

Asynchronous read/write operations available

Variable length delay bits; 21 to 5,048 bits (Cycle time: 25 ns)

15 to 5,048 bits (Cycle time: 35 ns)

Power supply voltage V

= 5.0 V

0.5 V

Suitable for sampling one line of A3 size paper (16 dots/mm)

All input/output TTL compatible

3-state output

Full static operation; data hold time = infinity

Ordering Information

Part Number

R/W Cycle Time

Package

PD485505G-25

25 ns

24-pin plastic SOP

PD485505G-35

35 ns

(11.43 mm (450))

PD485505

LINE BUFFER

5K-WORD BY 8-BIT

The mark shows major revised points.

Document No. M10059EJ7V0DSJ1 (7th edition)
Date Published December 2000 N CP(K)
Printed in Japan

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.

PD485505

Data Sheet M10059EJ7V0DS00

1. Input/Output Pin Function

Symbol

Number

Name

24 - 21

IN0

Data

Input

16 - 13

IN7

1 - 4

OUT0

Data

Output

9 - 12

OUT7

RSTW

Reset

Write

Input

RSTR

Reset

Read

Input

Write

Enable

Input

Read

Enable

Input

WCK

Write

Clock

Input

RCK

Read

Clock

Input

I/O

Function

Write data input pins.

The data inputs are strobed by the rising edge of WCK at the end of a cycle

and the setup and hold times (t

, t

) are defined at this point.

Out

Read data output pins.

The access time is regulated from the rising edge of RCK at the beginning of a

cycle and defined by t

Reset input pin for the initialization of the write address pointer.

The state of RSTW is strobed by the rising edge of WCK at the beginning of a

cycle and the setup and hold times (t

, t

) are defined.

Reset input pin for the initialization of the read address pointer.

The state of RSTR is strobed by the rising edge of RCK at the beginning of a

cycle and the setup and hold times (t

, t

) are defined.

Write operation control signal input pin.

When WE is in the disable mode ("H" level), the internal write operation is

inhibited and the write address pointer stops at the current position.

Read operation control signal input pin.

When RE is in the disable mode ("H" level), the internal read operation is

inhibited and the read address pointer stops at the current position. The output

changes to high impedance.

Write clock input pin.

When WE is enabled ("L" level), the write operation is executed in

synchronization with the write clock. The write address pointer is incremented

simultaneously.

Read clock input pin.

When RE is enabled ("L" level), the read operation is executed in synchroniza-

tion with the read clock. The read address pointer is incremented

simultaneously.

PD485505

Data Sheet M10059EJ7V0DS00

2. Operation Mode

PD485505 is a synchronous memory. All signals are strobed at the rising edge of the clock (RCK, WCK).

For this reason, setup time and hold time are specified for the rising edge of the clock (RCK, WCK).

2.1 Write Cycle

When the WE input is enabled ("L" level), a write cycle is executed in synchronization with the WCK clock

input.

The data inputs are strobed by the rising edge of the clock at the end of a cycle so that read data after a one-

line (5,048 bits) delay and write data can be processed with the same clock. Refer to Write Cycle Timing Chart.

When WE is disabled ("H" level) in a write cycle, the write operation is not performed during the cycle which

the WCK rising edge is in the WE = "H" level (t

WEW

). The WCK does not increment the write address pointer

at this time.

Unless inhibited by WE, the internal write address will automatically wrap around from 5,047 to 0 and begin

incrementing again.

2.2 Read Cycle

When the RE input is enabled ("L" level), a read cycle is executed in synchronization with the RCK clock input

and data is output after t

. Refer to Read Cycle Timing Chart.

When RE is disabled ("H" level) in a read cycle, the read operation is not performed during the cycle which

the RCK rising edge is in the RE = "H" level (t

REW

). The RCK does not increment the read address pointer at

this time.

2.3 Write Reset Cycle/Read Reset Cycle

After power up, the

PD485505 requires the initialization of internal circuits because the read and write

address pointers are not defined at that time.

It is necessary to satisfy setup requirements and hold times as measured from the rising edge of WCK and

RCK, and then input the RSTW and RSTR signals to initialize the circuit.

Write and read reset cycles can be executed at any time and the address pointer returns zero. Refer to Write

Reset Cycle Timing Chart, Read Reset Cycle Timing Chart.

Remark

Write and read reset cycles can be executed at any time and do not depend on the state of RE or WE.

PD485505

Data Sheet M10059EJ7V0DS00

3. Electrical Specifications

All voltages are referenced to GND.

Absolute Maximum Ratings

Parameter

Symbol

Condition

Rating

Unit

Voltage on any pin relative to GND

0.5

Note

to V

+ 0.5

Supply voltage

0.5 to +7.0

Output current

Operating ambient temperature

0 to 70

°C

Storage temperature

stg

55 to +125

°C

Note

3.0 V MIN. (Pulse width = 10 ns)

Caution

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

Recommended Operating Conditions

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Supply voltage

4.5

5.0

5.5

High level input voltage

2.4

+ 0.5

Low level input voltage

0.3

Note

+0.8

Operating ambient temperature

°C

Note

3.0 V MIN. (Pulse width = 10 ns)

DC Characteristics (Recommended Operating Conditions unless otherwise noted)

Parameter

Symbol

Test Condition

MIN.

TYP.

MAX.

Unit

Operating current

Input leakage current

= 0 to V

, Other Input 0 V

+10

Output leakage current

= 0 to V

+10

OUT

: High impedance

High level output voltage

= 1 mA

2.4

Low level output voltage

= 2 mA

0.4

Capacitance (T

= 25 °C, f = 1 MHz)

Parameter

Symbol

Test Condition

MIN.

TYP.

MAX.

Unit

Input capacitance

Output capacitance

PD485505

Data Sheet M10059EJ7V0DS00

AC Characteristics (Recommended Operating Conditions unless otherwise noted)

Notes 1, 2, 3

Parameter

Symbol

PD485505-25

PD485505-35

Unit

Notes

MIN.

MAX.

MIN.

MAX.

Write clock cycle time

WCK

Write clock pulse width

WCW

Write clock precharge time

WCP

Read clock cycle time

RCK

Read clock pulse width

RCW

Read clock precharge time

RCP

Access time

Write data-read delay time

WAR

470

Output hold time

Output low-impedance time

Output high-impedance time

Input data setup time

Input data hold time

RSTW/RSTR Setup time

RSTW/RSTR Hold time

RSTW/RSTR Deselected time (1)

RN1

RSTW/RSTR Deselected time (2)

RN2

WE Setup time

WES

WE Hold time

WEH

WE Deselected time (1)

WEN1

WE Deselected time (2)

WEN2

RE Setup time

RES

RE Hold time

REH

RE Deselected time (1)

REN1

RE Deselected time (2)

REN2

WE Disable time

WEW

RE Disable time

REW

Write reset time

RSTW

Read reset time

RSTR

Transition time

PD485505

Data Sheet M10059EJ7V0DS00

Notes 1. AC measurements assume t

= 5 ns.

2. AC Characteristics test condition

Input Timing Specification

Output Timing Specification

Output Loads for Timing

3. Input timing reference levels = 1.5 V. Output timing reference levels; V

= 2.0 V, V

= 0.8 V.

4. t

and t

are measured at

200 mV from the steady state voltage. Under any conditions, t

5. If either t

or t

is less than the specified value, reset operations are not guaranteed.

6. If either t

RN1

or t

RN2

is less than the specified value, reset operations may extend to cycles preceding or

following the period of reset operations.

7. If either t

WES

or t

WEH

is less than the specified value, write disable operations are not guaranteed.

8. If either t

WEN1

or t

WEN2

is less than the specified value, internal write disable operations may extend to cycles

preceding or following the period of write disable operations.

9. If either t

RES

or t

REH

is less than the specified value, read disable operations are not guaranteed.

10. If either t

REN1

or t

REN2

is less than the specified value, internal read disable operations may extend to cycles

preceding or following the period of read disable operations.

1.8 k

1.1 k

OUT

5 pF

, t

)

1.8 k

1.1 k

OUT

30 pF

, t

)

3.0 V

0 V

= 5 ns

1.5 V

Test points

0.8 V

2.0 V

High impedance

Test points

PD485505

Data Sheet M10059EJ7V0DS00

Write Reset Cycle Timing Chart (WE = Active)

Cycle n

Reset Cycle

Cycle 0

Cycle 1

RN2

RSTW

Note

RN1

"L" Level

(1)

(0)

(n)

(n1)

(Input)

WE (Input)

RSTW (Input)

WCK (Input)

Note

In write reset cycle, reset operation is executed even without a reset cycle (t

RSTW

WCK can be input any number of times in a reset cycle.

Write Reset Cycle Timing Chart (WE = Inactive)

Cycle n

Disable Cycle

Cycle 0

RN2

RSTW

Note

RN1

(0)

(n)

(n1)

(Input)

WE (Input)

RSTW (Input)

WCK (Input)

Reset Cycle

WEW

WEN1

WES

WEH

WEN2

Note

In write reset cycle, reset operation is executed even without a reset cycle (t

RSTW

WCK can be input any number of times in a reset cycle.

PD485505

Data Sheet M10059EJ7V0DS00

Read Reset Cycle Timing Chart (RE = Active)

Cycle n

Reset Cycle

Cycle 0

Cycle 1

RN2

RSTR

Note

RN1

"L" Level

(1)

(0)

(n)

(n1)

OUT

(Output)

RE (Input)

RSTR (Input)

RCK (Input)

(0)

Note

In read reset cycle, reset operation is executed even without a reset cycle (t

RSTR

RCK can be input any number of times in a reset cycle.

Read Reset Cycle Timing Chart (RE = Inactive)

Cycle n

Disable Cycle

Cycle 0

RN2

RSTR

Note

RN1

(0)

(n)

(n1)

OUT

(Output)

RE (Input)

RSTR (Input)

RCK (Input)

REH

Reset Cycle

REN1

RES

REW

REN2

High impedance

Note

In read reset cycle, reset operation is executed even without a reset cycle (t

RSTR

RCK can be input any number of times in a reset cycle.

PD485505

Data Sheet M10059EJ7V0DS00

4. Application

4.1 1 H Delay Line

PD485505 easily allows a 1 H (5,048 bits) delay line (see Figure 4.1).

Figure 4.1 1 H Delay Line Circuit

WCK

RSTW

RCK

OUT

RSTR

40 MHz Clock

Reset

Data Output

Data Input

Figure 4.2 1 H Delay Line Timing Chart

WCK

RCK

Cycle 0

Cycle 1

Cycle 2

1 H

(5,048 Cycles)

Cycle 5,047

Cycle 0'

2 H

(5,048 Cycles)

WCW

RCW

WCP

RCP

(0)

(1)

(2)

(5,046)

(5,047)

(0')

(1')

(0)

(1)

(2')

(3')

(2)

(3)

WCK/RCK

(Input)

RSTW /

RSTR

(Input)

OUT

(Output)

Cycle 1'

Cycle 2'

Cycle 3'

Write

Cycle 0

Read

Cycle 1

Cycle 2

Cycle 3

Remark

RE, WE = "L" level

PD485505

Data Sheet M10059EJ7V0DS00

4.2 n Bit Delay

It is possible to make delay read from the write data with the

PD485505.

(1) Perform a reset operation in the cycle proportionate to the delay length. (Figure 4.3)

(2) Shift the input timing of write reset (RSTW) and read reset (RSTR) depending on the delay length. (Figure 4.4)

(3) Shift the address by disabling RE for the period proportionate to the delay length. (Figure 4.5)

n bit: Delay bits from write cycle to read cycle correspond to a same address cell.

Restrictions

Delay bits n can be set from minimum bits to maximum bits depending on the operating cycle time. Refer

to 2. Operation Mode Operation-related Restriction.

Cycle time

MIN.

MAX.

25 ns

21 bits

5,048 bits

35 ns

15 bits

5,048 bits

Figure 4.3 n-Bit Delay Line Timing Chart (1)

WCK

RCK

Cycle 0

Cycle 1

Cycle 2

1 H

(n Cycles)

Cycle n1

2 H

(n Cycles)

WCW

RCW

WCP

RCP

(0)

(1)

(n2)

(n1)

(0')

(1')

(0)

(1)

(2')

(3')

(2)

(3)

WCK/RCK

(Input)

OUT

(Output)

(2)

RSTW /

RSTR

(Input)

Cycle 0'

Write

Cycle 0

Read

Cycle 1'

Cycle 1

Cycle 2'

Cycle 2

Cycle 3'

Cycle 3

WAR

Remark

RE, WE = "L" level

PD485505

Data Sheet M10059EJ7V0DS00

Figure 4.4 n-Bit Delay Line Timing Chart (2)

WCK

RCK

Cycle 0

Cycle 1

Cycle 2

Cycle n1

WCW

RCW

WCP

RCP

(0)

(1)

(2)

(n2)

(n1)

(n)

(n+1)

(0)

(1)

(n+2)

(n+3)

(2)

(3)

WCK/RCK

(Input)

RSTW

(Input)

OUT

(Output)

Cycle n+1

Cycle n+2

Cycle n+3

n Cycles

RSTR

(Input)

Cycle n

Write

Cycle 0

Read

Cycle 1

Cycle 2

Cycle 3

WAR

Remark

RE, WE = "L" level

Figure 4.5 n-Bit Delay Line Timing Chart (3)

WCK

RCK

Cycle 0

Cycle 1

Cycle 2

Cycle n1

WCW

RCW

WCP

RCP

(0)

(1)

(2)

(n2)

(n1)

(n)

(n+1)

(0)

(1)

(n+2)

(n+3)

(2)

(3)

WCK/RCK

(Input)

RSTW/

RSTR

(Input)

OUT

(Output)

Cycle n+1

Cycle n+2

Cycle n+3

REH

n Cycles

(Input)

REN2

Cycle n

Write

Cycle 0

Read

Cycle 1

Cycle 2

Cycle 3

WAR

High impedance

Remark

WE = "L" level

PD485505

Data Sheet M10059EJ7V0DS00

4.3 Double-speed Conversion

Figure 4.6 shows an example timing chart of double-speed and twice reading operation (f

= 2f

, 5,048 by

2 cycle) for a write operation (f

= 5,048 cycle).

Caution

The read operation collide with the write operation on the same line, last n bits output data

(5,048n to 5,048) in the first read operation will be undefined (see Figure 4.6 Double-speed

Conversion Timing Chart).

Undefined bits mentioned above depend on the cycle time.

Read cycle time

Undefined bits

25 ns

21 bits

35 ns

15 bits

Figure 4.6 Double-speed Conversion Timing Chart

Remark

RE, WE = "L" level

(5,048 Cycle)

5046 5047

5046' 5047'

5046 5047

5046'

5047'

(5,048 Cycle)

First read cycle

(5,048 Cycle)

Second read cycle

(5,048 Cycle)

First read cycle

n bits output data will be undefined.

5046 5047

0' 1' 2'

5046' 5047'

0' 1'

WCK

(Input)

RSTW

(Input)

RCK

(Input)

RSTR

(Input)

OUT

(Output)

PD485505

Data Sheet M10059EJ7V0DS00

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and trans-

ported in an anti-static container, static shielding bag or conductive material. All test and

measurement tools including work bench and floor should be grounded. The operator should be

grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar

precautions need to be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input

levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each

unused pin should be connected to V

or GND with a resistor, if it is considered to have a

possibility of being an output pin. All handling related to the unused pins must be judged device

by device and related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until

the reset signal is received. Reset operation must be executed immediately after power-on for

devices having reset function.

PD485505

[MEMO]

M8E 00. 4

The information in this document is current as of December, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
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developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
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The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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Document Outline

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Document Outline

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