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1999
MOS INTEGRATED CIRCUIT
PD464318AL, 464336AL
4M-BIT Bi-CMOS SYNCHRONOUS FAST STATIC RAM
256K-WORD BY 18-BIT / 128K-WORD BY 36-BIT
HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE
DATA SHEET
Document No. M13508EJ2V0DSJ1 (2nd edition)
Date Published December 2000 NS CP(K)
Printed in Japan
The mark
shows major revised points.
Description
The
PD464318AL is a 262,144 words by 18 bits, and the
PD464336AL is a 131,072 words by 36 bits
synchronous static RAM fabricated with advanced Bi-CMOS technology using N-channel memory cell.
This technology and unique peripheral circuits make the
PD464318AL and
PD464336AL a high-speed device.
The
PD464318AL and
PD464336AL are suitable for applications which require high-speed, low voltage, high-
density memory and wide bit configuration, such as cache and buffer memory.
These are packaged in a 119-pin plastic BGA (Ball Grid Array).
Features
Fully synchronous operation
HSTL Input / Output levels
Fast clock access time : 2.0 ns / 250 MHz, 2.3 ns / 225 MHz, 2.5 ns / 200 MHz
Asynchronous output enable control : /G
Byte write control : /SBa (DQa1-9), /SBb (DQb1-9), /SBc (DQc1-9), /SBd (DQd1-9)
Common I/O using three-state outputs
Internally self-timed write cycle
Late write with 1 dead cycle between Read-Write
User-configurable outputs :
Controlled impedance outputs or push-pull outputs
Boundary scan (JTAG) IEEE 1149.1 compatible
3.3 V (Chip) / 1.5V (I/O) supply
119 bump BGA package, 1.27 mm pitch, 14 mm x 22 mm
Sleep mode : ZZ(Enables sleep mode, active high)
Ordering Information
Part number
Access time
Clock frequency
Package
PD464318ALS1-A4
2.0 ns
250 MHz
119-pin plastic BGA
PD464318ALS1-A44
2.3 ns
225 MHz
PD464318ALS1-A5
2.5 ns
200 MHz
PD464336ALS1-A4
2.0 ns
250 MHz
PD464336ALS1-A44
2.3 ns
225 MHz
PD464336ALS1-A5
2.5 ns
200 MHz
3
PD464318AL, 464336AL
Data Sheet M13508EJ2V0DS
Pin Name and Functions [
PD464318ALS1]
Pin name
Description
Function
V
DD
Core Power Supply
Supplies power for RAM core
V
SS
Ground
V
DD
Q
Output Power Supply
Supplies power for output buffers
V
REF
Input Reference
K, /K
Main Clock Input
SA0 to SA17
Synchronous Address Input
DQa1 to DQb9
Synchronous Data Input / Output
/SS
Synchronous Chip Select
Logically selects SRAM
/SW
Synchronous Byte Write Enable
Write command
/SBa
Synchronous Byte "a" Write Enable
Write DQa1 to DQa9
/SBb
Synchronous Byte "b" Write Enable
Write DQb1 to DQb9
/G
Asynchronous Output Enable
Asynchronous input
ZZ
Asynchronous Sleep Mode
Enables sleep mode, active high
ZQ
Output Impedance Control
M1, M2
Mode select
Selects operation mode
Note
NC
No Connection
TMS
Test Mode Select (JTAG)
TDI
Test Data Input (JTAG)
TCK
Test Clock Input (JTAG)
TDO
Test Data Output (JTAG)
Note This device only supports Single Differential Clock, R/R Mode.
(R/R stands for Registered Input/Registered Output.)
5
PD464318AL, 464336AL
Data Sheet M13508EJ2V0DS
Pin Name and Functions [
PD464336ALS1]
Pin name
Description
Function
V
DD
Core Power Supply
Supplies power for RAM core
V
SS
Ground
V
DD
Q
Output Power Supply
Supplies power for output buffers
V
REF
Input Reference
K, /K
Main Clock
SA0 to SA16
Synchronous Address Input
DQa1 to DQd9
Synchronous Data Input / Output
/SS
Synchronous Chip Select
Logically selects SRAM
/SW
Synchronous Byte Write Enable
Write command
/SBa
Synchronous Byte "a" Write Enable
Write DQa1 to DQa9
/SBb
Synchronous Byte "b" Write Enable
Write DQb1 to DQb9
/SBc
Synchronous Byte "c" Write Enable
Write DQc1 to DQc9
/SBd
Synchronous Byte "d" Write Enable
Write DQd1 to DQd9
/G
Asynchronous Output Enable
Asynchronous input
ZZ
Asynchronous Sleep Mode
Enables sleep mode, active high
ZQ
Output Impedance Control
M1, M2
Mode Select
Selects operation mode
Note
NC
No Connection
TMS
Test Mode Select (JTAG)
TDI
Test Data Input (JTAG)
TCK
Test Clock Input (JTAG)
TDO
Test Data Output (JTAG)
Note This device only supports Single Differential Clock, R/R Mode.
(R/R stands for Registered Input/Registered Output.)
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