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1999
MOS INTEGRATED CIRCUIT
PD23C64202L
64M-BIT SYNCHRONOUS MASK-PROGRAMMABLE ROM
4M-WORD BY 16-BIT (WORD MODE) / 2M-WORD BY 32-BIT (DOUBLE WORD MODE)
DATA SHEET
The mark
!
!
!
!
shows major revised points.
Document No. M13945EJ5V0DS00 (5th edition)
Date Published August 2001 NS CP (K)
Printed in Japan
The mark
!
!
!
!
shows major revised points.
Description
The
PD23C64202L is a 67,108,864 bits synchronous mask-programmable ROM with multiplexed address bus.
The word organization is selectable (WORD mode : 4,194,304 words by 16 bits, DOUBLE WORD mode : 2,097,152
words by 32 bits).
The
PD23C64202L is packed in 86-pin PLASTIC TSOP (II).
Features
Fully synchronous mask-ROM; all signals referenced to a positive clock edge
Word organization :
4,194,304 words by 16 bits (WORD mode)
2,097,152 words by 32 bits (DOUBLE WORD mode)
Operation frequency : up to 100 MHz
Operation supply
voltage
V
CC
Clock frequency
MHz
Access time from CLK
ns (MAX.)
Operating current
(Burst mode)
mA (MAX.)
Standby current
(CMOS level input)
A (MAX.)
3.3 V
0.3 V
100
6
150
100
83
8
66
9
50
9
33
9
Programmable wrap type : Sequential or Interleave
Programmable burst length : 4, 8
Programmable /CAS latency : 3, 4, 5 or 6
Programmable /RAS latency : 1, 2
Burst termination by BURST STOP command
LVTTL compatible inputs and outputs
5
Data Sheet M13945EJ5V0DS
2
PD23C64202L
Ordering Information
Part number
Package
PD23C64202LG5-
-9JH
86-pin PLASTIC TSOP (II) (10.16 mm (400))
: ROM code suffix
Pin Configuration (Marking Side)
/xxx indicates active low signal.
86-pin PLASTIC TSOP (II) (10.16 mm (400))
[
PD23C64202LG5-
-9JH ]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
CC
O0
V
CC
Q
O16
O1
V
SS
Q
O17
O2
V
CC
Q
O18
O3
V
SS
Q
O19
/MR
V
CC
DQM
IC
/CAS
/RAS
/CS
/WORD
A12
A11
A10
A0
A1
A2
IC
V
CC
NC
O4
V
SS
Q
O20
O5
V
CC
Q
O21
O6
V
SS
Q
O22
O7
V
CC
Q
O23
V
CC
V
SS
O31
V
SS
Q
O15
O30
V
CC
Q
O14
O29
V
SS
Q
O13
O28
V
CC
Q
O12
IC
V
SS
NC
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
IC
V
SS
NC
O27
V
CC
Q
O11
O26
V
SS
Q
O10
O25
V
CC
Q
O9
O24
V
SS
Q
O8
V
SS
Remarks 1. IC : Internally connected; leave this pin unconnected or connect to GND.
NC : Not internally connected; signal can be applied.
2. Refer to 13. Package Drawing for the 1-pin index mark.
Data Sheet M13945EJ5V0DS
3
PD23C64202L
Pin Name
Symbol
Pin name
Pin number
CLK
Clock input
68
CKE
Clock enable input
67
/CS
Chip select
20
/RAS
Row address strobe
19
/CAS
Column address strobe
18
/MR
Mode register enable
14
/WORD
Mode select (DOUBLE WORD / WORD)
21
A0 - A12
Address inputs
25, 26, 27, 60, 61, 62, 63, 64, 65, 66, 24, 23, 22
O0 - O15, O16 - O31
Data outputs
2, 5, 8, 11, 31, 34, 37, 40, 45, 48, 51, 54, 74, 77, 80, 83, 4,
7, 10, 13, 33, 36, 39, 42, 47, 50, 53, 56, 76, 79, 82, 85
DQM
DQ mask enable
16
V
CC
Supply voltage (for internal circuit)
1, 15, 29, 43
V
CC
Q
Supply voltage (for output buffer)
3, 9, 35, 41, 49, 55, 75, 81
V
SS
Ground (for internal circuit)
44, 58, 72, 86
V
SS
Q
Ground (for output buffer)
6, 12, 32, 38, 46, 52, 78, 84
NC
No connection
30, 57, 69, 70, 71
IC
Internal connection
17, 28, 59, 73
Block Diagram
DQM
Clock generator
Command decoder
Memory Cell Matrix
4,194,304 words by 16 bits
(WORD mode)
or
2,097,152 words by 32 bits
(DOUBLE WORD mode)
Mode register
Control logic
Column buffer
Column decoder
Sense amplifier
Output control
Output buffer
O0 - O31
/CS
/RAS
/CAS
/MR
/WORD
CLK
CKE
A0 - A12
Row buffer
Row decoder
Data Sheet M13945EJ5V0DS
4
PD23C64202L
CONTENTS
1.
Input / Output Pin Functions ............................................................................................................ 7
2.
Simplified State Diagram .................................................................................................................. 9
3.
Commands ........................................................................................................................................ 10
3.1
MODE REGISTER SET (MRS) ................................................................................................................. 10
3.2
ROW ACTIVATE (ACT) ............................................................................................................................ 10
3.3
READ (READ) .......................................................................................................................................... 10
3.4
BURST STOP (BST) ................................................................................................................................. 10
4.
Truth Table ....................................................................................................................................... 11
4.1
Clock Enable and Command ................................................................................................................. 11
4.2
Command Truth Table ............................................................................................................................ 11
4.3
Operative Command Table ................................................................................................................... 12
5.
Mode Register Settings .................................................................................................................. 13
6.
Word Modes...................................................................................................................................... 14
6.1
Addressing Map (WORD Mode) ............................................................................................................. 14
6.2
Data Output (WORD Mode) .................................................................................................................... 14
6.3
Addressing Map (DOUBLE WORD Mode) ............................................................................................. 15
6.4
Data Output (DOUBLE WORD Mode) .................................................................................................... 15
7.
Relationship between Clock Frequency and /RAS Latency, /CAS Latency ............................... 16
8.
Command Interval ........................................................................................................................... 18
8.1
Relationship between Frequency, Parameter and Command Interval ............................................... 18
8.2
READ to READ Command Interval (t
CCD
) .............................................................................................. 19
8.3
READ to ROW ACTIVATE Command Interval ....................................................................................... 21
8.4
READ to BURST STOP Command Interval ............................................................................................ 24
8.5
ROW ACTIVATE to ROW ACTIVATE Command Interval ..................................................................... 24
9.
Power-On Sequence ....................................................................................................................... 25
10. Basic Operations ............................................................................................................................. 26
10.1
MODE REGISTER SET Command ......................................................................................................... 26
10.2
DQM Operation ........................................................................................................................................ 26
10.3
Burst Termination ................................................................................................................................... 26
10.4
POWER DOWN and CLOCK SUSPEND Mode ...................................................................................... 27
10.4.1
POWER DOWN Mode ................................................................................................................ 27
10.4.2
READ SUSPEND and ACTIVE POWER DOWN Mode .............................................................. 27
11. Electrical Specifications ................................................................................................................. 28
12. Timing Charts .................................................................................................................................. 32
12.1
Relationship between Frequency and Parameter ................................................................................ 32
12.1.1
ROW ACTIVATE - READ - ROW ACTIVATE - READ (1-1) ....................................................... 33
12.1.2
ROW ACTIVATE - READ - ROW ACTIVATE - READ (1-2) ....................................................... 33
12.1.3
ROW ACTIVATE - READ - ROW ACTIVATE - READ (2-1) ....................................................... 33
12.1.4
ROW ACTIVATE - READ - ROW ACTIVATE - READ (2-2) ....................................................... 34
12.1.5
ROW ACTIVATE - READ - ROW ACTIVATE - READ (2-3) ....................................................... 34
12.1.6
ROW ACTIVATE - READ - ROW ACTIVATE - READ (2-4) ....................................................... 34
12.1.7
ROW ACTIVATE - READ - ROW ACTIVATE - READ (3-1) ....................................................... 35
12.1.8
ROW ACTIVATE - READ - ROW ACTIVATE - READ (3-2) ....................................................... 35
12.1.9
ROW ACTIVATE - READ - ROW ACTIVATE - READ (4-1) ....................................................... 35
12.1.10 ROW ACTIVATE - READ - ROW ACTIVATE - READ (4-2) ....................................................... 36
12.1.11 ROW ACTIVATE - READ - ROW ACTIVATE - READ (4-3) ....................................................... 36
Data Sheet M13945EJ5V0DS
5
PD23C64202L
12.1.12 ROW ACTIVATE - READ - ROW ACTIVATE - READ (4-4) ....................................................... 36
12.1.13 ROW ACTIVATE - READ - READ (1-1) ...................................................................................... 37
12.1.14 ROW ACTIVATE - READ - READ (1-2) ...................................................................................... 37
12.1.15 ROW ACTIVATE - READ - READ (2-1) ...................................................................................... 37
12.1.16 ROW ACTIVATE - READ - READ (2-2) ...................................................................................... 38
12.1.17 ROW ACTIVATE - READ - READ (2-3) ...................................................................................... 38
12.1.18 ROW ACTIVATE - READ - READ (2-4) ...................................................................................... 38
12.1.19 ROW ACTIVATE - READ - READ (3-1) ...................................................................................... 39
12.1.20 ROW ACTIVATE - READ - READ (3-2) ...................................................................................... 39
12.1.21 ROW ACTIVATE - READ - READ (4-1) ...................................................................................... 39
12.1.22 ROW ACTIVATE - READ - READ (4-2) ...................................................................................... 40
12.1.23 ROW ACTIVATE - READ - READ (4-3) ...................................................................................... 40
12.1.24 ROW ACTIVATE - READ - READ (4-4) ...................................................................................... 40
12.2
Random Row Read Timing .................................................................................................................... 41
12.2.1
at 100 MHz (2-5-1-1-1) ............................................................................................................... 41
12.2.2
at 100 MHz (2-5-1-1-1-1-1-1-1) ................................................................................................... 41
12.2.3
at 83 MHz (2-5-1-1-1) ................................................................................................................. 42
12.2.4
at 83 MHz (2-5-1-1-1-1-1-1-1) ..................................................................................................... 42
12.2.5
at 66 MHz (2-5-1-1-1) ................................................................................................................. 43
12.2.6
at 66 MHz (2-5-1-1-1-1-1-1-1) ..................................................................................................... 43
12.2.7
at 50 MHz (1-4-1-1-1) ................................................................................................................. 44
12.2.8
at 50 MHz (1-4-1-1-1-1-1-1-1) ..................................................................................................... 44
12.2.9
at 33 MHz (1-3-1-1-1) ................................................................................................................. 45
12.2.10 at 33 MHz (1-3-1-1-1) ................................................................................................................. 45
12.2.11 at 33 MHz (1-3-1-1-1-1-1-1-1) ..................................................................................................... 46
12.2.12 at 33 MHz (1-3-1-1-1-1-1-1-1) ..................................................................................................... 46
12.3
Random Column Read Timing ............................................................................................................... 47
12.3.1
at 100 MHz (2-5-1-1-1) ............................................................................................................... 47
12.3.2
at 100 MHz (2-5-1-1-1-1-1-1-1) ................................................................................................... 47
12.3.3
at 83 MHz (2-5-1-1-1) ................................................................................................................. 48
12.3.4
at 83 MHz (2-5-1-1-1-1-1-1-1) ..................................................................................................... 48
12.3.5
at 66 MHz (2-5-1-1-1) ................................................................................................................. 49
12.3.6
at 66 MHz (2-5-1-1-1-1-1-1-1) ..................................................................................................... 49
12.3.7
at 50 MHz (1-4-1-1-1) ................................................................................................................. 50
12.3.8
at 50 MHz (1-4-1-1-1) ................................................................................................................. 50
12.3.9
at 50 MHz (1-4-1-1-1-1-1-1-1) ..................................................................................................... 51
12.3.10 at 50 MHz (1-4-1-1-1-1-1-1-1) ..................................................................................................... 51
12.3.11 at 33 MHz (1-3-1-1-1) ................................................................................................................. 52
12.3.12 at 33 MHz (1-3-1-1-1) ................................................................................................................. 52
12.3.13 at 33 MHz (1-3-1-1-1-1-1-1-1) ..................................................................................................... 53
12.3.14 at 33 MHz (1-3-1-1-1-1-1-1-1) ..................................................................................................... 53
12.3.15 BURST STOP ............................................................................................................................. 54
12.3.16 CLOCK SUSPEND and POWER DOWN ................................................................................... 54
12.4
Command Combination Examples ........................................................................................................ 55
12.4.1
ROW ACTIVATE - READ (1) ...................................................................................................... 55
12.4.2
ROW ACTIVATE - READ (2) ...................................................................................................... 55
12.4.3
ROW ACTIVATE - READ (3) ...................................................................................................... 56
12.4.4
ROW ACTIVATE - READ (4) ...................................................................................................... 56
12.4.5
ROW ACTIVATE - READ (5) ...................................................................................................... 57
Data Sheet M13945EJ5V0DS
6
PD23C64202L
12.4.6
ROW ACTIVATE - ROW ACTIVATE .......................................................................................... 57
12.4.7
READ - READ (1) ....................................................................................................................... 58
12.4.8
READ - READ (2) ....................................................................................................................... 58
12.4.9
READ - READ (3) ....................................................................................................................... 59
12.4.10 READ SUSPEND (1) .................................................................................................................. 60
12.4.11 READ SUSPEND (2) .................................................................................................................. 60
12.4.12 BURST STOP (1) ........................................................................................................................ 61
12.4.13 BURST STOP (2) ........................................................................................................................ 61
12.4.14 CLOCK SUSPEND ..................................................................................................................... 62
12.4.15 POWER DOWN .......................................................................................................................... 62
12.4.16 ROW ACTIVATE - READ (1) ...................................................................................................... 63
12.4.17 ROW ACTIVATE - READ (2) ...................................................................................................... 63
12.4.18 ROW ACTIVATE - READ (3) ...................................................................................................... 64
12.4.19 ROW ACTIVATE - READ (4) ...................................................................................................... 64
12.4.20 ROW ACTIVATE - READ (5) ...................................................................................................... 65
12.4.21 ROW ACTIVATE - ROW ACTIVATE .......................................................................................... 65
12.4.22 READ - READ (1) ....................................................................................................................... 66
12.4.23 READ - READ (2) ....................................................................................................................... 66
12.4.24 READ - READ (3) ....................................................................................................................... 67
12.4.25 READ SUSPEND (1) .................................................................................................................. 68
12.4.26 READ SUSPEND (2) .................................................................................................................. 68
12.4.27 BURST STOP (1) ........................................................................................................................ 69
12.4.28 BURST STOP (2) ........................................................................................................................ 69
12.4.29 CLOCK SUSPEND ..................................................................................................................... 70
12.4.30 POWER DOWN .......................................................................................................................... 70
12.4.31 ROW ACTIVATE - READ (1) ...................................................................................................... 71
12.4.32 ROW ACTIVATE - READ (2) ...................................................................................................... 71
12.4.33 ROW ACTIVATE - READ (3) ...................................................................................................... 72
12.4.34 ROW ACTIVATE - READ (4) ...................................................................................................... 72
12.4.35 ROW ACTIVATE - READ (5) ...................................................................................................... 73
12.4.36 ROW ACTIVATE - ROW ACTIVATE .......................................................................................... 73
12.4.37 READ - READ (1) ....................................................................................................................... 74
12.4.38 READ - READ (2) ....................................................................................................................... 74
12.4.39 READ - READ (3) ....................................................................................................................... 75
12.4.40 READ SUSPEND (1) .................................................................................................................. 76
12.4.41 READ SUSPEND (2) .................................................................................................................. 76
12.4.42 BURST STOP (1) ........................................................................................................................ 77
12.4.43 BURST STOP (2) ........................................................................................................................ 77
12.4.44 CLOCK SUSPEND ..................................................................................................................... 78
12.4.45 POWER DOWN .......................................................................................................................... 78
13. Package Drawing ............................................................................................................................. 79
14. Recommended Soldering Condition ............................................................................................. 80
Data Sheet M13945EJ5V0DS
7
PD23C64202L
1. Input / Output Pin Functions
(1/2)
Pin name
Input / Output
Function
CLK
(Clock input)
Input
CLK is the master clock input. Other inputs signals are referenced to the CLK rising
edge.
CKE
(Clock enable input)
Input
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising
edge is valid; otherwise, it is invalid. If the CLK rising edge is invalid, the internal
clock is not issued and this device suspends operation.
When this device is not in burst mode and CKE is negated, the device enters
POWER DOWN mode. During POWER DOWN or READ SUSPEND mode, CKE
must remain low.
/CS
(Chip select)
Input
Command control signal. For details, refer to 4.2 Command Truth Table.
/CS low starts the command input cycle. When /CS is high, commands are ignored
but operations continue.
/RAS
(Row address strobe)
Input
Command control signal. For details, refer to 4.2 Command Truth Table.
Row address is determined by A0 - A12 at the CLK (clock) rising edge in the ROW
ACTIVATE command cycle.
/CAS
(Column address
strobe)
Input
Command control signal. For details, refer to 4.2 Command Truth Table.
Column address is determined by A0 - A8 at the CLK rising edge in the READ
command cycle.
Column address is used differently in the WORD mode and the DOUBLE WORD
mode, respectively.
WORD mode (4M words by 16 bits)
Column address : A0 - A8
DOUBLE WORD mode (2M words by 32 bits)
Column address : A0 - A7
/MR
(Mode register enable)
Input
Command control signal. For details, refer to 4.2 Command Truth Table.
/WORD
(Mode select)
Input
The pin for switching WORD mode and DOUBLE WORD mode.
Low level : WORD mode (4M words by 16 bits)
High level : DOUBLE WORD mode (2M words by 32 bits)
A0 - A12
(Address inputs)
Input
Address input pins.
A0 - A12 are used differently in the WORD mode and the DOUBLE WORD mode,
respectively.
WORD mode (4M words by 16 bits)
Row address
: A0 - A12
Column address
: A0 - A8
DOUBLE WORD mode (2M words by 32 bits)
Row address
: A0 - A12
Column address
: A0 - A7
Also they are used as command control signal. For details, refer to 4.2 Command
Truth Table.
O0 - O15, O16 - O31
(Data outputs)
Output
Data output pins.
O0 - O15, O16 - O31 are used differently in the WORD mode and the DOUBLE
WORD mode, respectively.
WORD mode (4M words by 16 bits)
16 bits data outputs to O0 - O15, and O16 - O31 are Hi-Z.
DOUBLE WORD mode (2M words by 32 bits)
32 bits data outputs to O0 - O31.
DQM
(DQ mask enable)
Input
DQM controls the output buffers like the /OE pin of an asynchronous mask ROM.
DQM high and DQM low turn the output buffers off and on, respectively.
DQM latency is 2 clocks.
Data Sheet M13945EJ5V0DS
8
PD23C64202L
(2/2)
Pin name
Input / Output
Function
V
CC
(Supply voltage)
Power supply pin for internal circuits.
V
CC
Q
(Supply voltage)
Power supply pin for the output buffers.
V
SS
(Ground)
Ground pin for internal circuits.
V
SS
Q
(Ground)
Ground pin for the output buffers.
NC
(No connection)
Not internally connected (The signal can be applied).
IC
(Internal connection)
Internally connected (Leave this pin unconnected or connect to GND).
Data Sheet M13945EJ5V0DS
9
PD23C64202L
2. Simplified State Diagram
CKE
CKE
ACT
IDLE
ACTIVE
ACTIVE
POWER
DOWN
POWER
ON
Automatic sequence
Manual input
READ
CKE
CKE
READ
SUSPEND
CKE
CKE
POWER
DOWN
READ
ACT
READ
BST
MRS
MODE
REGISTER
SET
MRS
Data Sheet M13945EJ5V0DS
10
PD23C64202L
3. Commands
3.1 MODE REGISTER SET (MRS)
This device has a mode register that defines how the device
operates. In this command, A0 through A6 are the data input pins.
After power on, the mode register set command must be executed
to initialize the device. During 2 clocks (t
RSC
) following this
command, this device cannot accept any other commands.
Figure of MODE REGISTER SET (MRS)
/MR
/CAS
/RAS
/CS
CKE
CLK
H
Address
L
L
L
L
3.2 ROW ACTIVATE (ACT)
This command activates a row address selected by A0 - A12.
Figure of ROW ACTIVATE (ACT)
/MR
/CAS
/RAS
/CS
CKE
CLK
H
Address
L
L
H
Row
H
3.3 READ (READ)
Read data is available after /CAS latency requirements have been
met. This command sets the burst start address given by the
column address.
Figure of READ (READ)
/MR
/CAS
/RAS
/CS
CKE
CLK
H
Address
L
L
Col
H
H
3.4 BURST STOP (BST)
This command terminates the current burst
operation.
Figure of BURST STOP (BST)
(Standard)
(SDRAM-precharge-like)
/MR
/CAS
/RAS
/CS
CKE
CLK
H
Address
L
H
H
L
/MR
/CAS
/RAS
/CS
CKE
CLK
H
Address
L
L
H
L
Data Sheet M13945EJ5V0DS
11
PD23C64202L
4. Truth Table
4.1 Clock Enable and Command
/CS
/RAS
/CAS
/MR
Address
CKE
CLK
H
n
-
1
n
n+1
Command
4.2 Command Truth Table
Function
Symbol
CKE
/CS
/RAS
/CAS
/MR
DQM
A0 - A12
/WORD
n
-
1
n
MODE REGISTER SET
MRS
H
L
L
L
L
Code
ROW ACTIVATE
ACT
H
L
L
H
H
RA
READ
READ
H
L
H
L
H
CA
BURST STOP
Standard
BST
H
L
H
H
L
SDRAM-
precharge-like
H
L
L
H
L
POWER DOWN
Entry
PWDN
H
L
Exit
L
H
DQM
READ
H
V
No operation
NOP
H
H
H
L
H
H
H
Organization control
H
L
H
L
H
CA
H or L
Illegal
(SDRAM write)
H
L
H
L
L
CA
(SDRAM refresh)
H
L
L
L
H
Remark
H : High level
L
: Low level
: Don't care (high or low level)
V : Valid data input
RA : Row address
CA : Column address
Data Sheet M13945EJ5V0DS
12
PD23C64202L
4.3 Operative Command Table
Current state
CKE
/CS
/RAS
/CAS
/MR
Address
Command
Action
IDLE
L
PWDN
Power down
(POWER-ON or
H
L
L
L
L
A0 - A6
MRS
Mode register accessing
MODE REGISTER SET)
H
L
L
H
H
RA
ACT
Row activating
H
L
H
L
H
CA
READ
Illegal (ignored)
H
L
H
H
L
BST
No operation
H
L
L
H
L
ACTIVE
L
-
Clock suspend
H
L
L
L
L
A0 - A6
MRS
Mode register accessing
H
L
L
H
H
RA
ACT
Row activating
H
L
H
L
H
CA
READ
READ start
H
L
H
H
L
BST
Illegal (ignored)
H
L
L
H
L
READ
L
-
Clock suspend / Power down
H
L
L
L
L
A0 - A6
MRS
Mode register accessing
H
L
L
H
H
RA
ACT
Row activating
H
L
H
L
H
CA
READ
Next READ start
H
L
H
H
L
BST
Burst stop
H
L
L
H
L
Any state
H
L
H
L
L
CA
-
Illegal
H
L
L
L
H
-
Illegal
H
H
NOP
No operation
H
L
H
H
H
NOP
No operation
Remark
H : High level
L
: Low level
: Don't care (high level or low level)
V : Valid data input
RA : Row address
CA : Column address
Data Sheet M13945EJ5V0DS
13
PD23C64202L
5. Mode Register Settings
/CS
CKE
CLK
H
A1
L
A0
A3
A2
A5
A4
;
;
;;
;;
/RAS
L
/CAS
L
/MR
L
;
A6
;
;;
;
;
;;
;;
;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
A0
A1
A2
A3
A4
A5
A6
Burst length
4
8
A1
0
0
1
1
A0
0
1
0
1
Burst Length
Wrap type
Sequential
Interleave
A2
0
1
Wrap Type
/CAS latency
3
4
5
6
A5
0
0
0
0
1
1
1
1
A3
0
1
0
1
0
1
0
1
/CAS latency
A4
0
0
1
1
0
0
1
1
/RAS latency
1
2
A6
0
1
/RAS latency
Remark
: inhibited
Lower 2 or 3 bits of column address indicate
starting column address of burst read.
0
0
0
0 1 2 3 4 5 6 7
0
0
1
1 2 3 4 5 6 7 0
0
1
0
2 3 4 5 6 7 0 1
0
1
1
3 4 5 6 7 0 1 2
1
0
0
4 5 6 7 0 1 2 3
1
0
1
5 6 7 0 1 2 3 4
1
1
0
6 7 0 1 2 3 4 5
0 1 2 3 4 5 6 7
1 0 3 2 5 4 7 6
2 3 0 1 6 7 4 5
3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3
5 4 7 6 1 0 3 2
6 7 4 5 2 3 0 1
Starting column
address
Sequential
Interleave
1
1
1
7 0 1 2 3 4 5 6
7 6 5 4 3 2 1 0
A2
A1
A0
0
0
0 1 2 3
0
1
1 2 3 0
1
0
2 3 0 1
1
1
3 0 1 2
0 1 2 3
1 0 3 2
2 3 0 1
3 2 1 0
Burst
length
4
8
Burst Sequence
Addressing sequence
4
3
2
1
0
Column address
Burst
length = 4
Burst
length = 8
Data Sheet M13945EJ5V0DS
14
PD23C64202L
6. Word Modes
6.1 Addressing Map (WORD Mode)
Row address
Column address
Address
bits
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A12
11
10
9
8
7
6
5
4
3
2
1
0
12
5
4
3
2
1
0
6
MSB
LSB
21
7
20
8
6.2 Data Output (WORD Mode)
When /WORD is set to low level, the device is set to WORD mode and 16-bit data will be output.
;;;;;
;;
CLK
Command
/WORD
READ
/CAS latency = 6, Burst length = 4
A8
O0 - O15
Hi-Z
O16 - O31
Hi-Z
Q0
Q1
Q2
Q3
;;;;;
;;;;;
;
;
Data 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32 bits data
O14
O15
O12
O13
O10
O11
O8
O9
O7
O4
O6
O2
O3
O0
O1
0
O6
A8 = Low level
Lower 16 bits data
will be output
A8 = High level
Upper 16 bits data
will be output
Data outputs 0
Data 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
Data 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
Data 3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
Data outputs 1
Data outputs 2
Data outputs 3
Data Sheet M13945EJ5V0DS
15
PD23C64202L
6.3 Addressing Map (DOUBLE WORD Mode)
Row address
Column address
Address
bits
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A12
11
10
9
8
7
6
5
4
3
2
1
0
12
MSB
LSB
5
4
3
2
1
0
6
20
7
6.4 Data Output (DOUBLE WORD Mode)
When /WORD is set to high level, the device is set to DOUBLE WORD mode and 32-bit data will be output.
CLK
Command
/WORD
READ
/CAS latency = 6, Burst length = 4
A8
O0 - O15
Hi-Z
O16 - O31
Hi-Z
Q0
Q1
Q2
Q0
Q1
Q2
Q3
;;;;;
;;;;;;
;;;;;;
;;;;;;
;;;;;;
Q3
;;
Data 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32 bits data
O14
O15
O12
O13
O10
O11
O8
O9
O7
O4
O6
O2
O3
O0
O1
0
O6
Data outputs 0
Data 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
Data 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
Data 3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
Data outputs 1
Data outputs 2
Data outputs 3
O30
O31
O28
O29
O26
O27
O24
O25
O23
O20
O22
O18
O19
O16
O17
O21
Data Sheet M13945EJ5V0DS
16
PD23C64202L
7. Relationship between Clock Frequency and /RAS Latency, /CAS Latency
Clock frequency (Clock cycle time)
/RAS latency (MIN.)
/CAS latency (MIN.)
Data output cycle
33 MHz (30 ns)
1
3
1
50 MHz (20 ns)
1
4
1
66 MHz (15 ns)
2
5
1
83 MHz (12 ns)
2
5
1
100 MHz (10 ns)
2
5
1
ACT
READ
1
2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15
1
2
3
4
CLK
Command
OQ
/CAS latency
/RAS latency
Hi-Z
66 MHz (15 ns)
ACT
1
T0
T1
T2
T3
1
2
3
CLK
Command
OQ
/CAS latency
Hi-Z
50 MHz (20 ns)
T4
T5
T6
T7
T8
T9
T10
T11
READ
1
T0
T1
T2
T3
1
CLK
Command
OQ
/CAS latency
Hi-Z
33 MHz (30 ns)
T4
T5
T6
T7
READ
ACT
2
3
/RAS latency
/RAS latency
1
Data output cycle
1
Data output cycle
Data output cycle
1
4
5
Data Sheet M13945EJ5V0DS
17
PD23C64202L
1
2
T0
CLK
Command
OQ
/CAS latency
Hi-Z
83 MHz (12 ns)
T1 T2 T3 T4 T5 T6 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20
1
2
3
4
5
1 2
T0
CLK
Command
OQ
/CAS latency
Hi-Z
100 MHz (10 ns)
T1
ACT
READ
T4 T5
T2 T3
T8 T9
T6 T7
T12 T13
T10 T11
T16 T17
T14 T15
T20 T21
T18 T19
T22 T23
1
2
3
4 5
/RAS latency
/RAS latency
ACT READ
Data output cycle
Data output cycle
1
1
Data Sheet M13945EJ5V0DS
18
PD23C64202L
8. Command Interval
8.1 Relationship between Frequency, Parameter and Command Interval
Frequency (t
CK
)
Burst
length
/RAS
latency
/CAS
latency
READ to READ
command interval
READ to ROW ACTIVATE
command interval (MIN.)
Unit
(MIN.)
t
CCD
(MIN.)
Read data is
NOT terminated
Read data is
terminated
100 MHz (10 ns)
4
2
5
4
4
4
CLK
6
5
5
5
8
5
8
8
4
6
9
9
5
83 MHz (12 ns)
4
2
5
4
4
4
CLK
6
5
5
5
8
5
8
8
4
6
9
9
5
66 MHz (15 ns)
4
2
5
4
4
4
CLK
6
5
5
5
8
5
8
8
4
6
9
9
5
50 MHz (20 ns)
4
1
4
3
3
3
CLK
5
4
4
4
6
5
5
5
8
4
7
7
3
5
8
8
4
6
9
9
5
33 MHz (30 ns)
4
1
3
2
2
2
CLK
4
3
3
3
5
4
4
4
6
5
5
5
8
3
6
6
2
4
7
7
3
5
8
8
4
6
9
9
5
Data Sheet M13945EJ5V0DS
19
PD23C64202L
8.2 READ to READ Command Interval (t
CCD
)
A minimum of t
CCD
interval is required between two READ commands. For details, refer to 8.1 Relationship
between Frequency, Parameter and Command Interval.
CLK
OQ
/CAS latency = 3, Burst length = 4
READa
Qa0 Qa1 Qb0 Qb1
Command
READb
t
CCD (MIN.)
= 2 clocks
CLK
OQ
/CAS latency = 4, Burst length = 4
READa
Qa0 Qa1 Qa2 Qb0
Command
READb
t
CCD (MIN.)
= 3 clocks
Qb2 Qb3
Qb1 Qb2 Qb3
CLK
OQ
/CAS latency = 5, Burst length = 4
READa
Qa0 Qa1 Qa2
Qb0
Command
READb
t
CCD (MIN.)
= 4 clocks
Qb1 Qb2 Qb3
Qa3
CLK
OQ
/CAS latency = 6, Burst length = 4
READa
Qa0 Qa1 Qa2
Qb0
Command
READb
t
CCD (MIN.)
= 5 clocks
Qb1 Qb2 Qb3
Qa3
Data Sheet M13945EJ5V0DS
20
PD23C64202L
CLK
OQ
/CAS latency = 3, Burst length = 8
READa
Qa0 Qa1 Qa2 Qa3
Command
READb
t
CCD (MIN.)
= 6 clocks
Qa5 Qb0 Qb1 Qb2
Qa4
Qb3 Qb4 Qb5 Qb6 Qb7
CLK
OQ
/CAS latency = 4, Burst length = 8
READa
Qa0 Qa1 Qa2 Qa3
Command
READb
t
CCD (MIN.)
= 7 clocks
Qa5
Qb0 Qb1 Qb2
Qa4
Qb3 Qb4 Qb5 Qb6 Qb7
Qa6
CLK
OQ
/CAS latency = 5, Burst length = 8
READa
Qa0 Qa1 Qa2 Qa3
Command
READb
t
CCD (MIN.)
= 8 clocks
Qa5
Qa7 Qb0 Qb1
Qa4
Qb2 Qb3 Qb4
Qa6
Qb5
CLK
OQ
/CAS latency = 6, Burst length = 8
READa
Qa0 Qa1 Qa2 Qa3
Command
READb
t
CCD (MIN.)
= 9 clocks
Qa5
Qa7
Qb0 Qb1
Qa4
Qb2 Qb3
Qa6
Data Sheet M13945EJ5V0DS
21
PD23C64202L
8.3 READ to ROW ACTIVATE Command Interval
An interval required between READ and ROW ACTIVATE command differs according to whether burst data is
terminated or NOT, before the ROW ACTIVATE command.
a. Read Data NOT Terminated
When read data is NOT terminated before the ROW ACTIVATE command, a required interval is as shown in 8.1
Relationship between Frequency, Parameter and Command Interval.
CLK
OQ
/CAS latency = 3, Burst length = 4
READ
Q0
Q1
Q2
Q3
Commands
ACT
2 clocks (MIN.)
CLK
OQ
/CAS latency = 4, Burst length = 4
READ
Q0
Q1
Q2
Q3
Command
ACT
3 clocks (MIN.)
CLK
OQ
/CAS latency = 5, Burst length = 4
READ
Q0
Q1
Q2
Q3
Command
ACT
4 clocks (MIN.)
CLK
OQ
/CAS latency = 6, Burst length = 4
READ
Q0
Q1
Q2
Q3
Command
ACT
5 clocks (MIN.)
Data Sheet M13945EJ5V0DS
22
PD23C64202L
CLK
OQ
/CAS latency = 3, Burst length = 8
READ
Q0
Q1
Q2
Q3
Command
ACT
6 clocks (MIN.)
Q5
Q6
Q7
Q4
CLK
OQ
/CAS latency = 4, Burst length = 8
READ
Q0
Q1
Q2
Q3
Command
ACT
7 clocks (MIN.)
Q5
Q7
Q4
Q6
CLK
OQ
/CAS latency = 5, Burst length = 8
READ
Q0
Q1
Q2
Q3
Command
ACT
8 clocks (MIN.)
Q5
Q7
Q4
Q6
CLK
OQ
/CAS latency = 6, Burst length = 8
READ
Q0
Q1
Q2
Q3
Command
ACT
9 clocks (MIN.)
Q5
Q7
Q4
Q6
Data Sheet M13945EJ5V0DS
23
PD23C64202L
b. Read Data Terminated
When read data is terminated before the ROW ACTIVATE command, a required interval is one clock less than
/CAS latency. For details, refer to 8.1 Relationship between Frequency, Parameter and Command Interval.
CLK
OQ
/CAS latency = 3, Burst length = 4, 8
READa
Qa0
Command
ACT
2 clocks (MIN.)
CLK
OQ
/CAS latency = 4, Burst length = 4, 8
READa
Qa0
Command
ACT
3 clocks (MIN.)
BST
BST
CLK
OQ
/CAS latency = 5, Burst length = 4, 8
READa
Qa0
Command
ACT
4 clocks (MIN.)
BST
CLK
OQ
/CAS latency = 6, Burst length = 4, 8
READa
Qa0
Command
ACT
BST
5 clocks (MIN.)
Data Sheet M13945EJ5V0DS
24
PD23C64202L
8.4 READ to BURST STOP Command Interval
A minimum of one-clock interval is required between READ and BURST STOP command.
CLK
Command
ACT
/CAS latency = 3, Burst length = 4
OQ
Hi-Z
1 clock (MIN.)
READ
BST
Q0
8.5 ROW ACTIVATE to ROW ACTIVATE Command Interval
A minimum of one-clock interval is required between two ROW ACTIVATE command.
However, t
RC
is required between two ROW ACTIVATE command for valid data output. See 12.1 Relationship
between Frequency and Parameter for details.
CLK
Command
ACTa
/CAS latency = 3, Burst length = 4
OQ
Hi-Z
Qb0
Qb1
Qb2
Qb3
1 clock (MIN.)
ACTb READb
Data Sheet M13945EJ5V0DS
25
PD23C64202L
9. Power-On Sequence
This device must be powered-on in a manner as follows.
CKE and DQM must be held at high level on power-on.
On power-on, the mode register is set to default values; /RAS latency is set to 2, /CAS latency to 6, burst length to 4
and wrap type to sequential. To change these values, MODE REGISTER SET command is required.
In order to keep all outputs to Hi-Z until the MODE REGISTER SET command is finished, DQM must be held at
high level.
CLK
CKE
/RAS
/CS
/MR
A0 - A6
DQM
/CAS
Hi-Z
H
OQ
A7 - A12
H
t
RSC
(MIN.)
2 clocks
MODE
REGISTER
SET
command
ROW
ACTIVATE
command
Code
Note
;;;
;;;
;;;;
;;;;
;;;
;;;
;;;
;;;;;
;;;;;
;;;;
;;;;
;;;
;;;;;
;;;;
;
Note For details of input code, refer to 5. Mode Register Settings.
5
5
Data Sheet M13945EJ5V0DS
26
PD23C64202L
10. Basic Operations
10.1 MODE REGISTER SET Command
A minimum of 2 clocks are required between MODE REGISTER SET command and others.
CLK
Command
Hi-Z
OQ
t
RSC
= 2 clocks (MIN.)
ACT
MRS
10.2 DQM Operation
Read data can be masked by setting DQM high level as follows.
CLK
Command
OQ
(/CAS latency = 3)
Masked by DQM after 2 clocks
READ
OQ
(/CAS latency = 4)
OQ
(/CAS latency = 6)
Hi-Z
Hi-Z
Q0
Q3
Q0
Q1
Q2
Q1
Hi-Z
Hi-Z
Hi-Z
/CAS latency = 3, 4, 5, 6, Burst length = 4
DQM
OQ
(/CAS latency = 5)
Hi-Z
Q0
Q2
Q3
Hi-Z
Hi-Z
Q1
Q2
Q3
10.3 Burst Termination
During a read cycle, when the BURST STOP command is issued, the burst read data will be terminated and the
data bus will be Hi-Z after the /CAS latency. At least one-clock interval is required between READ and BURST STOP
command regardless of the /CAS latency.
CLK
Command
OQ
(/CAS latency = 3)
READ
Hi-Z
Hi-Z
Hi-Z
/CAS latency = 3, 4, 5, 6, Burst length = 4 or 8
OQ
(/CAS latency = 4)
OQ
(/CAS latency = 6)
BST
Note
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Q0
Q2
Q0
Q1
Q2
Q0
Q1
Q2
Q1
Q0
Q1
Q2
OQ
(/CAS latency = 5)
Note Both standard and SDRAM-precharge-like types of the BURST STOP command can be used.
Data Sheet M13945EJ5V0DS
27
PD23C64202L
10.4 POWER DOWN and CLOCK SUSPEND Mode
Operation modes of this device is shown as follows. Refer to 2. Simplified State Diagram for details.
CLK
Command
OQ
IDLE
ACT
Q0
Q1
Hi-Z
/CAS latency = 3, Burst length = 4
READ
Q2
READ
ACTIVE
Q3
ACTIVE
10.4.1 POWER DOWN Mode
When CKE is held at low level in the IDLE state, the device will turn to the POWER DOWN (Standby) mode.
CLK
Command
CKE
NOP
Internal
CLK
OQ
Hi-Z
POWER DOWN
ACT
Command input accepted
Remark
Once the device had turned to the POWER DOWN mode, ROW ACTIVATE command is necessary in
order to read data.
10.4.2 READ SUSPEND and ACTIVE POWER DOWN Mode
When CKE is held at low level in READ mode, the device will turn to the READ SUSPEND (Active standby) mode.
When CKE is held at low level in ACTIVE mode, the device will turn to the ACTIVE POWER DOWN (Active standby)
mode.
CLK
Command
CKE
READ
/CAS latency = 3, Burst length = 4
Internal
CLK
OQ
Hi-Z
Q1
Q3
Q2
Q0
ACTIVE
POWER DOWN
READ SUSPEND
Data Sheet M13945EJ5V0DS
28
PD23C64202L
11. Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Voltage on power supply pin relative to GND
V
CC
0.5
Note
to +4.6
V
Voltage on any pin relative to GND
V
T
0.5
Note
to V
CC
+ 0.5 V,
+4.6
V
Short circuit output current
I
O
50
mA
Power dissipation
P
D
1
W
Operating ambient temperature
T
A
0 to 70
C
Storage temperature
T
stg
55 to +150
C
Note 1.0 V (MIN.) : 10 ns pulse width measured at 50% of pulse amplitude.
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Supply voltage
V
CC
3.0
3.3
3.6
V
High level input voltage
V
IH
2.0
V
CC
+0.3
Note1
V
Low level input voltage
V
IL
0.3
Note2
+0.8
V
Operating ambient temperature
T
A
0
70
C
Notes 1. V
CC
+ 0.5 V (MAX.) : 10 ns pulse width measured at 50% of pulse amplitude.
2.
-
0.5 V (MIN.) : 10 ns pulse width measured at 50% of pulse amplitude.
Capacitance (T
A
= 25
C, f = 1 MHz)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Input capacitance
C
I
All input pins
5
pF
Output capacitance
C
O
All output pins
7
pF
Data Sheet M13945EJ5V0DS
29
PD23C64202L
DC Characteristics (Recommended Operating Conditions unless Otherwise Noted)
Parameter
Symbol
Test condition
MIN.
MAX.
Unit
Note
Standby current
I
CC3
P
CKE
V
IL (MAX.)
, t
CK
= 10 ns
3
mA
in power down mode
I
CC3
PS
CKE = 0 V, t
CK
= 10 ns
100
A
Active standby current
I
CC3
N
CKE
V
IH (MIN.)
, t
CK
= 10 ns, /CS
V
IH (MIN.)
,
50
mA
in non power down mode
input signals are changed one time during 10 ns.
I
CC3
NS
CKE
V
IH (MIN.)
, t
CK
=
,
10
input signals are stable.
Operating current (Burst mode)
I
CC4
t
CK
= 10 ns, I
O
= 0 mA, /CAS latency = 5
150
mA
1
Input leakage current
I
I (L)
V
I
= 0 to 3.6 V, all other pins not under test = 0 V
10
+10
A
Output leakage current
I
O (L)
D
OUT
is disabled, V
O
= 0 to 3.6 V
10
+10
A
High level output voltage
V
OH
I
O
= 2.0 mA
2.4
V
Low level output voltage
V
OL
I
O
= +2.0 mA
0.4
V
Note 1. I
CC4
depends on output loading and cycle rates. Specified values are obtained with output open. In addition
to this, I
CC4
is measured on condition that addresses are changed only one time during t
CK (MIN.)
.
5
Data Sheet M13945EJ5V0DS
30
PD23C64202L
AC Characteristics (Recommended Operating Conditions unless Otherwise Noted)
AC Characteristics Test Conditions
AC measurements assume t
T
= 1 ns.
Reference level for measuring timing of input signals is 1.4 V. Transition times are measured between V
IH
and V
IL
.
If t
T
is longer than 1 ns, reference level for measuring timing of input signals is V
IH (MIN.)
and V
IL (MAX.)
.
An access time is measured at 1.4 V.
t
CK
t
CH
t
CL
2.4 V
1.4 V
0.4 V
CLK
2.4 V
1.4 V
0.4 V
Input
t
Setup
t
Hold
Output
t
AC
t
OH
1.4 V
1.4 V
Output Load
Output
Z = 50
1.4 V
50 pF
50
Asynchronous Characteristics
Parameter
Symbol
100 MHz
83 MHz
66 MHz
50 MHz
33 MHz
Unit
MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN.
MAX.
Mode register set time
t
RSC
2
2
2
2
2
clock
/RAS to /CAS delay time (/RAS latency)
t
RCD
20
24
30
20
30
ns
Transition time
t
T
0.1
10.0
0.1
10.0
0.1
10.0
0.1
10.0
0.1
10.0
ns
Data Sheet M13945EJ5V0DS
31
PD23C64202L
Synchronous Characteristics
Parameter
Symbol
100 MHz
83 MHz
66 MHz
50 MHz
33 MHz
Unit
Note
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Clock cycle time
t
CK
10
12
15
20
30
ns
Access time from CLK
t
AC
6
8
9
9
9
ns
CLK high level width
t
CH
4
4
4
4
4
ns
CLK low level width
t
CL
4
4
4
4
4
ns
Data-out hold time
t
OH
2.5
2.5
2.5
2.5
2.5
ns
Data-out Low-Z time
t
LZ
0
0
0
0
0
ns
Data-out Hi-Z time
t
HZ
2.5
6
2.5
8
2.5
9
2.5
9
2.5
9
ns
Address setup time
t
AS
3
3
4
4
4
ns
Address hold time
t
AH
1
1
2
2
2
ns
CKE setup time
t
CKS
3
3
4
4
4
ns
CKE hold time
t
CKH
1
1
2
2
2
ns
CKE setup time (power down exit)
t
CKSP
4+t
CK
4+t
CK
4+t
CK
4+t
CK
4+t
CK
ns
Command setup time
(/CS, /RAS, /CAS, /MR, /WORD)
t
CMS
3
3
4
4
4
ns
Command hold time
(/CS, /RAS, /CAS, /MR, /WORD)
t
CMH
1
1
2
2
2
ns
AC Parameters for Read Timing
;;;;;;;
;;;;;;;
;;
;;;;;;
;;
;;
;;;;;;
;;;;;;
;;
;;;;;;
CLK
/CAS latency = 5, Burst length = 4
CKE
/RAS
/CS
/MR
Address
/WORD
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
/CAS
t
CKS
t
CH
t
CK
t
CL
t
CMS
t
CMH
t
AS
t
AH
Hi-Z
;;
;;
;
;
;
;
t
AC
t
AC
t
OH
t
LZ
;
;
;
;
;
;
;
;
;;
;;
;
;
t
HZ
t
OH
t
RCD
H
t
CKH
OQ
t
CMS
t
CMH
Data Sheet M13945EJ5V0DS
32
PD23C64202L
12. Timing Charts
12.1 Relationship between Frequency and Parameter
Frequency (t
CK
)
/RAS latency (MIN.)
/CAS latency
Burst length
t
RC (MIN.)
Note1
t
CCD (MIN.)
Note2
Unit
100 MHz (10 ns)
2
5
4
6
4
CLK
6
7
5
5
8
10
8
6
11
9
83 MHz (12 ns)
2
5
4
6
4
CLK
6
7
5
5
8
10
8
6
11
9
66 MHz (15 ns)
2
5
4
6
4
CLK
6
7
5
5
8
10
8
6
11
9
50 MHz (20 ns)
1
4
4
4
3
CLK
5
5
4
6
6
5
4
8
8
7
5
9
8
6
10
9
33 MHz (30 ns)
1
3
4
3
2
CLK
4
4
3
5
5
4
6
6
5
3
8
7
6
4
8
7
5
9
8
6
10
9
Notes 1. t
RC
: ACT to ACT command period
2. t
CCD
: READ to READ command period
Data Sheet M13945EJ5V0DS
33
PD23C64202L
12.1.1 ROW ACTIVATE - READ - ROW ACTIVATE - READ (1-1)
CLK
Command
at 100, 83, 66 MHz
/RAS latency = 2, /CAS latency = 6, Burst length = 4
INVALID case
Case 1
Case 2
READb
READb
READb
Qa0 Qa1 Qa2 Qa3
Qa0
Qa2
;;
;
;
;;
Qb1 Qb2 Qb3
Qb0
Qb1 Qb2
Qb1
Qb0
Qb0
Qa1
Qa3
READa
INVALID case
Case 2
Case 1
;
INVALID data
ACT
ACT
ACT
ACT
t
RC
= 7
Qb3
Qb2
12.1.2 ROW ACTIVATE - READ - ROW ACTIVATE - READ (1-2)
CLK
Command
at 100, 83, 66 MHz
/RAS latency = 2, /CAS latency = 5, Burst length = 4
INVALID case
Case 1
Case 2
READb
READb
READb
Qa0 Qa1 Qa2 Qa3
Qa0
Qa2
;
;;
;
;
Qb1 Qb2 Qb3
Qb0
Qb1 Qb2 Qb3
Qb1 Qb2 Qb3
Qb0
Qb0
Qa1
Qa3
READa
INVALID case
Case 2
Case 1
;
INVALID data
ACT
ACT
ACT
ACT
t
RC
= 6
12.1.3 ROW ACTIVATE - READ - ROW ACTIVATE - READ (2-1)
CLK
Command
at 50, 33 MHz
/RAS latency = 1, /CAS latency = 6, Burst length = 4
INVALID case
Case 1
Case 2
READb
Qa0 Qa1 Qa2 Qa3
Qa0
Qa2
;
;;
;
Qb1 Qb2 Qb3
Qb0
Qb1 Qb2 Qb3
Qb1 Qb2
Qb0
Qb0
Qa1
Qa3
READa
INVALID Case
Case 2
Case 1
;
INVALID data
ACT
ACT
t
RC
= 6
READb
ACT
READb
ACT
Qb3
;
Data Sheet M13945EJ5V0DS
34
PD23C64202L
12.1.4 ROW ACTIVATE - READ - ROW ACTIVATE - READ (2-2)
CLK
Command
at 50, 33 MHz
/RAS latency = 1, /CAS latency = 5, Burst length = 4
INVALID case
Case 1
Case 2
READb
Qa0 Qa1 Qa2 Qa3
Qa0
Qa2
;;
;
;;
Qb1 Qb2 Qb3
Qb0
Qb1 Qb2 Qb3
Qb1 Qb2
Qb0
Qb0
Qa1
Qa3
READa
INVALID case
Case 2
Case 1
;
INVALID data
ACT
ACT
t
RC
= 5
READb
ACT
READb
ACT
Qb3
;
12.1.5 ROW ACTIVATE - READ - ROW ACTIVATE - READ (2-3)
CLK
Command
at 50, 33 MHz
/RAS latency = 1, /CAS latency = 4, Burst length = 4
INVALID case
Case 1
Case 2
READb
Qa0 Qa1 Qa2 Qa3
Qa0
Qa2
;
;;
;
Qb1 Qb2 Qb3
Qb0
Qb1 Qb2 Qb3
Qb1 Qb2
Qb0
Qb0
Qa1
Qa3
READa
INVALID case
Case 2
Case 1
;
ACT
ACT
t
RC
= 4
READb
ACT
READb
ACT
Qb3
INVALID data
12.1.6 ROW ACTIVATE - READ - ROW ACTIVATE - READ (2-4)
CLK
Command
at 33 MHz
/RAS latency = 1, /CAS latency = 3, Burst length = 4
INVALID case
Case 1
Case 2
READb
Qa0 Qa1 Qa2
Qa0
Qa2
;
;
Qb1 Qb2 Qb3
Qb0
Qb1 Qb2 Qb3
Qb1 Qb2
Qb0
Qb0
Qa1
READa
INVALID case
Case 2
Case 1
;
INVALID data
ACT
t
RC
= 3
READb
ACT
READb
ACT
Qb3
Qa3
ACT
Data Sheet M13945EJ5V0DS
35
PD23C64202L
12.1.7 ROW ACTIVATE - READ - ROW ACTIVATE - READ (3-1)
CLK
Command
at 100, 83, 66 MHz
/RAS latency = 2, /CAS latency = 6, Burst length = 8
INVALID case 1
INVALID case 2
Case 1
READb
READb
READb
Qa0 Qa1 Qa2 Qa3
Qa0
Qa2
;;
;
;
;;
Qa1
Qa3
READa
INVALID case 1
Case 2
INVALID case 2
;;
INVALID data
ACT
ACT
ACT
ACT
t
RC
= 11
Case 2
Qa0
Qa2
Qa1
Qa3
READb
ACT
Case 1
;
;
;
;;
;
Qa5
Qa4
Qa6 Qa7
Qa5
Qa4
Qa6 Qa7
Qb0
Qb2
Qb1
;
Qb1
Qb0
Qb0
Qb0
Qb2
Qb1
Qb3
Qb5
Qb4
Qb6
12.1.8 ROW ACTIVATE - READ - ROW ACTIVATE - READ (3-2)
CLK
Command
at 100, 83, 66 MHz
/RAS latency = 2, /CAS latency = 5, Burst length = 8
INVALID case 1
INVALID case 2
Case 1
READb
READb
READb
Qa0 Qa1 Qa2 Qa3
Qa0
Qa2
;
;;
;
;
Qb1
Qb0
Qb0
Qa1
Qa3
READa
INVALID case 1
Case 2
INVALID Case 2
;
INVALID data
ACT
ACT
ACT
ACT
t
RC
= 10
Case 2
Qa0
Qa2
Qb0
Qa1
Qa3
READb
ACT
Case 1
;;
Qb2
Qb1
;;
;;
;
;
;
;
;;
;;
Qa5
Qa4
Qa6 Qa7
Qa5
Qa4
Qa6 Qa7
Qb0
Qb2
Qb1
Qb3
Qb5
Qb4
Qb6
12.1.9 ROW ACTIVATE - READ - ROW ACTIVATE - READ (4-1)
CLK
Command
at 50, 33 MHz
/RAS latency = 1, /CAS latency = 6, Burst length = 8
INVALID case 1
INVALID case 2
Case 1
READb
READb
Qa1 Qa2 Qa3
Qa0
Qa2
;;
;
;
Qa1
Qa3
READa
Case 2
INVALID case 2
;
INVALID data
ACT
ACT
ACT
t
RC
= 10
Case 2
Qa0
Qa2
Qa1
Qa3
READb
ACT
Case 1
;
;
;;
Qa5
Qa4
Qa6 Qa7
Qa5
Qa4
Qa6 Qa7
READb
ACT
Qb0
Qb2
Qb1
Qb0
Qb1
Qb0
Qb0
Qb2 Qb3
Qb5
Qb4
Qb1
Qb6
Qa0
INVALID case 1
;;;
Data Sheet M13945EJ5V0DS
36
PD23C64202L
12.1.10 ROW ACTIVATE - READ - ROW ACTIVATE - READ (4-2)
CLK
Command
at 50, 33 MHz
/RAS latency = 1, /CAS latency = 5, Burst length = 8
INVALID case 1
INVALID case 2
Case 1
READb
READb
Qa1 Qa2 Qa3
Qa0
Qa2
;
;;
;
Qa1
Qa3
READa
Case 2
INVALID case 2
;
INVALID data
ACT
ACT
ACT
t
RC
= 9
Case 2
Qa0
Qa2
Qa1
Qa3
READb
ACT
Case 1
;;
;
;
Qa5
Qa4
Qa6 Qa7
Qa5
Qa4
Qa6 Qa7
READb
ACT
Qb0
Qb2
Qb1
Qb3 Qb4
Qb0
Qb1
Qb2
Qb1
Qb0
Qb0
Qb2 Qb3
Qb5
Qb4
Qb1
Qb7
Qb6
Qa0
Qb2 Qb3
INVALID case 1
;;;
12.1.11 ROW ACTIVATE - READ - ROW ACTIVATE - READ (4-3)
CLK
Command
at 50, 33 MHz
/RAS latency = 1, /CAS latency = 4, Burst length = 8
INVALID case 1
INVALID case 2
Case 1
READb
READb
Qa1 Qa2 Qa3
Qa0
Qa2
;
;;
;
Qa1
Qa3
READa
Case 2
INVALID case 2
;
INVALID data
ACT
ACT
ACT
t
RC
= 8
Case 2
Qa0
Qa2
Qa1
Qa3
READb
ACT
Case 1
;
;
;;
Qa5
Qa4
Qa6 Qa7
Qa5
Qa4
Qa6 Qa7
READb
ACT
Qb0
Qb2
Qb1
Qb3
Qb5
Qb4
Qb0
Qb1
Qb2
Qb1
Qb3 Qb4
Qb0
Qb0
Qb2 Qb3
Qb5
Qb4
Qb1
Qb7
Qb6
Qa0
Qb6
Qb2 Qb3
Qb5
Qb4
INVALID case 1
12.1.12 ROW ACTIVATE - READ - ROW ACTIVATE - READ (4-4)
CLK
Command
at 33 MHz
/RAS latency = 1, /CAS latency = 3, Burst length = 8
INVALID case 1
INVALID case 2
Case 1
READb
READb
Qa1 Qa2 Qa3
Qa0
Qa2
;
Qa1
Qa3
READa
Case 2
INVALID case 2
;
INVALID data
ACT
ACT
ACT
t
RC
= 7
Case 2
Qa0
Qa2
Qa1
Qa3
READb
ACT
Case 1
;
;
Qa5
Qa4
Qa6
Qb7
Qa5
Qa4
Qa6 Qa7
READb
ACT
Qb0
Qb2 Qb3
Qb5
Qb4
Qb1
Qb6
Qa0
INVALID case 1
;
;;
;;
Qb7
Qb0
Qb2 Qb3
Qb5
Qb4
Qb1
Qb6
Qb0
Qb2 Qb3
Qb5
Qb4
Qb1
Qb6
Qb0
Qb2 Qb3
Qb5
Qb4
Qb1
Qb6
Qa7
Data Sheet M13945EJ5V0DS
37
PD23C64202L
12.1.13 ROW ACTIVATE - READ - READ (1-1)
CLK
Command
at 100, 83, 66 MHz
/RAS latency = 2, /CAS latency = 6, Burst length = 4
INVALID case
Case 1
Case 2
READb
Qa0 Qa1 Qa2 Qa3
Qa0
Qa2
;;
;
;
Qb1 Qb2 Qb3
Qb0
Qb1 Qb2 Qb3
Qb1 Qb2
Qb0
Qb0
Qa1
Qa3
READa
INVALID case
Case 2
Case 1
;
INVALID data
ACT
t
CCD
= 5
READb
READb
Qb3
;;
12.1.14 ROW ACTIVATE - READ - READ (1-2)
CLK
Command
at 100, 83, 66 MHz
/RAS latency = 2, /CAS latency = 5, Burst length = 4
INVALID case
Case 1
Case 2
READb
Qa0 Qa1 Qa2 Qa3
Qa0
Qa2
;
;;
;
Qb1 Qb2
Qb0
Qb1 Qb2 Qb3
Qb1 Qb2
Qb0
Qb0
Qa1
Qa3
READa
INVALID case
Case 2
Case 1
;
INVALID data
ACT
t
CCD
= 4
READb
READb
Qb3
Qb3
12.1.15 ROW ACTIVATE - READ - READ (2-1)
CLK
Command
INVALID case
Case 1
Case 2
READb
Qa0 Qa1 Qa2 Qa3
Qa0
Qa2
;
;;
;
Qb1 Qb2 Qb3
Qb0
Qb1 Qb2 Qb3
Qb1 Qb2
Qb0
Qb0
Qa1
Qa3
READa
INVALID case
Case 2
Case 1
;
INVALID data
ACT
t
CCD
= 5
READb
READb
Qb3
at 50, 33 MHz
/RAS latency = 1, /CAS latency = 6, Burst length = 4
;
Data Sheet M13945EJ5V0DS
38
PD23C64202L
12.1.16 ROW ACTIVATE - READ - READ (2-2)
CLK
Command
INVALID case
Case 1
Case 2
READb
Qa0 Qa1 Qa2 Qa3
Qa0
Qa2
;;
;
;;
Qb1 Qb2 Qb3
Qb0
Qb1 Qb2 Qb3
Qb1 Qb2
Qb0
Qb0
Qa1
Qa3
READa
INVALID case
Case 2
Case 1
;
INVALID data
ACT
t
CCD
= 4
READb
READb
Qb3
at 50, 33 MHz
/RAS latency = 1, /CAS latency = 5, Burst length = 4
12.1.17 ROW ACTIVATE - READ - READ (2-3)
CLK
Command
INVALID case
Case 1
Case 2
READb
Qa0 Qa1 Qa2
Qa0
Qa2
;
;;
Qb1 Qb2 Qb3
Qb0
Qb1 Qb2 Qb3
Qb1 Qb2
Qb0
Qb0
Qa1
Qa3
READa
INVALID case
Case 2
Case 1
;
INVALID data
ACT
t
CCD
= 3
READb
READb
Qb3
at 50, 33 MHz
/RAS latency = 1, /CAS latency = 4, Burst length = 4
12.1.18 ROW ACTIVATE - READ - READ (2-4)
CLK
Command
INVALID case
Case 1
Case 2
Qa0 Qa1
Qa0
Qa2
Qb1 Qb2 Qb3
Qb0
Qb1 Qb2 Qb3
Qb1 Qb2
Qb0
Qb0
Qa1
READa
INVALID case
Case 2
Case 1
;
INVALID data
ACT
READb
READb
Qb3
at 33 MHz
/RAS latency = 1, /CAS latency = 3, Burst length = 4
;
t
CCD
= 2
READb
Data Sheet M13945EJ5V0DS
39
PD23C64202L
12.1.19 ROW ACTIVATE - READ - READ (3-1)
CLK
Command
at 100, 83, 66 MHz
/RAS latency = 2, /CAS latency = 6, Burst length = 8
INVALID case 1
INVALID case 2
Case 1
READb
READb
Qa1 Qa2 Qa3
Qa0
Qa2
;;
;
;
Qa1
Qa3
READa
Case 2
INVALID case 2
;
INVALID data
ACT
t
CCD
= 9
Case 2
Qa0
Qa2
Qa1
Qa3
READb
Case 1
;
;
;
;
Qa5
Qa4
Qa6 Qa7
Qa5
Qa4
Qa6 Qa7
READb
Qb0
Qb2
Qb1
Qb0
Qb1
Qb0
Qb0
Qb2 Qb3
Qb5
Qb4
Qb1
Qb6
Qa0
INVALID case 1
;
;
;;
;;
;;
12.1.20 ROW ACTIVATE - READ - READ (3-2)
CLK
Command
at 100, 83, 66 MHz
/RAS latency = 2, /CAS latency = 5, Burst length = 8
INVALID case 1
INVALID case 2
Case 1
READb
READb
Qa1 Qa2 Qa3
Qa0
Qa2
;
;;
;
Qa1
Qa3
READa
Case 2
INVALID case 2
;
INVALID data
ACT
t
CCD
= 8
Case 2
Qa0
Qa2
Qa1
Qa3
READb
Case 1
;
;
;
;
Qa5
Qa4
Qa6 Qa7
Qa5
Qa4
Qa6 Qa7
READb
Qb0
Qb2
Qb1
Qb3 Qb4
Qb0
Qb1
Qb2
Qb1
Qb0
Qb0
Qb2 Qb3
Qb5
Qb4
Qb1
Qb7
Qb6
Qa0
Qb2 Qb3
INVALID case 1
;;
;;
12.1.21 ROW ACTIVATE - READ - READ (4-1)
CLK
Command
at 50, 33 MHz
/RAS latency = 1, /CAS latency = 6, Burst length = 8
INVALID case 1
INVALID case 2
Case 1
READb
READb
Qa1 Qa2 Qa3
;
;;
READa
Case 2
INVALID case 2
;
INVALID data
ACT
t
CCD
= 9
Case 2
Qa0
Qa2
Qa1
Qa3
READb
Case 1
;
Qa5
Qa4
Qa6 Qa7
Qb0
Qb2 Qb3
Qb5
Qb4
Qb1
Qb6
Qa0
INVALID case 1
;;
Qb7
Qb0
Qb2 Qb3
Qb1
READb
Qb1
Qb0
Qb2
Qb1
Qb0
;;
Qa0
Qa2
Qa1
Qa3
Qa5
Qa4
Qa6 Qa7
;;
;
Data Sheet M13945EJ5V0DS
40
PD23C64202L
12.1.22 ROW ACTIVATE - READ - READ (4-2)
CLK
Command
at 50, 33 MHz
/RAS latency = 1, /CAS latency = 5, Burst length = 8
INVALID case 1
INVALID case 2
Case 1
READb
READb
Qa1 Qa2 Qa3
;;
;
READa
Case 2
INVALID case 2
;
INVALID data
ACT
t
CCD
= 8
Case 2
Qa0
Qa2
Qa1
Qa3
READb
Case 1
;;
Qa5
Qa4
Qa6 Qa7
Qb0
Qb2 Qb3
Qb5
Qb4
Qb1
Qb6
Qa0
INVALID case 1
;
Qb7
Qb0
Qb2 Qb3
Qb5
Qb4
Qb1
READb
Qb2 Qb3
Qb1
Qb0
Qb2 Qb3 Qb4
Qb1
Qb0
;;;
Qa0
Qa2
Qa1
Qa3
Qa5
Qa4
Qa6 Qa7
12.1.23 ROW ACTIVATE - READ - READ (4-3)
CLK
Command
at 50, 33 MHz
/RAS latency = 1, /CAS latency = 4, Burst length = 8
INVALID case 1
INVALID case 2
Case 1
READb
READb
Qa1 Qa2 Qa3
;
;;
READa
Case 2
INVALID case 2
;
INVALID data
ACT
Case 2
Qa0
Qa2
Qa1
Qa3
READb
Case 1
;
Qa5
Qa4
Qa6 Qa7
Qb0
Qb2 Qb3
Qb5
Qb4
Qb1
Qb6
Qa0
INVALID case 1
;
Qb7
Qb0
Qb2 Qb3
Qb5
Qb4
Qb1
READb
Qb2 Qb3
Qb1
Qb0
Qb2 Qb3 Qb4
Qb1
Qb0
Qa0
Qa2
Qa1
Qa3
Qa5
Qa4
Qa6
Qb6
Qb5
Qb4
t
CCD
= 7
Qb7
Qb6
Qb5
12.1.24 ROW ACTIVATE - READ - READ (4-4)
CLK
Command
at 33 MHz
/RAS latency = 1, /CAS latency = 3, Burst length = 8
INVALID case 1
INVALID case 2
Case 1
READb
READb
Qa1 Qa2 Qa3
Qa0
Qa2
;
Qa1
Qa3
READa
Case 2
INVALID case 2
;
INVALID data
ACT
t
CCD
= 6
Case 2
Qa0
Qa2
Qa1
Qa3
READb
Case 1
Qa5
Qa4
Qa5
Qa4
Qa6
Qb2 Qb3
Qb5
Qb4
Qb1
Qb6
Qa0
INVALID case 1
;;
;;
Qb7
READb
Qb2 Qb3
Qb5
Qb4
Qb1
Qb0
Qb2 Qb3
Qb5
Qb4
Qb1
Qb6
Qb0
Qb0
Qb0
Qb2 Qb3
Qb5
Qb4
Qb1
Qb6 Qb7
Qb7
Qb6 Qb7
Data Sheet M13945EJ5V0DS
41
PD23C64202L
12.2 Random Row Read Timing
12.2.1 at 100 MHz (2-5-1-1-1)
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
t
RC
t
RC
= 6
(Burst length = 4)
4 clocks (MIN.) are
necessary between
READ and ACT
;;;
;;;;;;
;;;
;;;
;;
;;;;
;;;;
;;;;;;;;
Ca0
/RAS latency = 2, /CAS latency = 5, Burst length = 4
ACT
READ
ACT
READ
ACT
READ
;
Ra0
Ra0
Cb0
Rb0
Rb0
;
Cc0
Rc0
Rc0
;;
H
;;;;;;
;;;;;;
;;;
;;;;;;
H
Hi-Z
Qa0
Qa2 Qa3
Qb0 Qb1 Qb2 Qb3
Qa1
Qc0 Qc1 Qc2 Qc3
12.2.2 at 100 MHz (2-5-1-1-1-1-1-1-1)
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
Qa0
Qa2 Qa3
t
RC
t
RC
= 10
(Burst length = 8)
Qa1
;;
;;;;;;;
;;;;;;;;
Ca0
/RAS latency = 2, /CAS latency = 5, Burst length = 8
ACT
READ
ACT
READ
;
Ra0
Ra0
Cb0
Rb0
Rb0
;
Qa4
Qa6 Qa7
Qa5
;;;;
;;;;;
;;;;
;;;;
;;;;;
;;;;;
;;;;
;;;;;
H
H
Hi-Z
Qb0
Qb2 Qb3
Qb1
Qb4
Qb6
Qb5
Data Sheet M13945EJ5V0DS
42
PD23C64202L
12.2.3 at 83 MHz (2-5-1-1-1)
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
t
RC
t
RC
= 6
(Burst length = 4)
4 clocks (MIN.) are
necessary between
READ and ACT
;;;
;;;;;;
;;;
;;;
;;
;;;;
;;;;
;;;;;;;;
Ca0
/RAS latency = 2, /CAS latency = 5, Burst length = 4
ACT
READ
ACT
READ
ACT
READ
;
Ra0
Ra0
Cb0
Rb0
Rb0
;
Cc0
Rc0
Rc0
;;
H
;;;;;;
;;;;;;
;;;
;;;;;;
H
Hi-Z
Qa0
Qa2 Qa3
Qb0 Qb1 Qb2 Qb3
Qc0 Qc1 Qc2 Qc3
Qa1
12.2.4 at 83 MHz (2-5-1-1-1-1-1-1-1)
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
Qa0
Qa2 Qa3
Qb0 Qb1 Qb2 Qb3
t
RC
t
RC
= 10
(Burst length = 8)
Qa1
;;
;;;;;;;
;;;;;;;;
Ca0
/RAS latency = 2, /CAS latency = 5, Burst length = 8
ACT
READ
ACT
READ
;
Ra0
Ra0
Cb0
Rb0
Rb0
;
Qa4
Qa6 Qa7
Qa5
Qb4 Qb5
;;;;
;;;;;
;;;;
;;;;
;;;;;
;;;;;
;;;;
;;;;;
H
H
Hi-Z
Qb6
Data Sheet M13945EJ5V0DS
43
PD23C64202L
12.2.5 at 66 MHz (2-5-1-1-1)
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
t
RC
t
RC
= 6
(Burst length = 4)
4 clocks (MIN.) are
necessary between
READ and ACT
;;;
;;;;;;
;;;
;;;
;;
;;;;
;;;;
;;;;;;;;
Ca0
/RAS latency = 2, /CAS latency = 5, Burst length = 4
ACT
READ
ACT
READ
ACT
READ
;
Ra0
Ra0
Cb0
Rb0
Rb0
;
Cc0
Rc0
Rc0
;;
H
;;;;;;
;;;;;;
;;;
;;;;;;
H
Hi-Z
Qa0
Qa2 Qa3
Qb0 Qb1 Qb2 Qb3
Qc0 Qc1 Qc2 Qc3
Qa1
12.2.6 at 66 MHz (2-5-1-1-1-1-1-1-1)
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
Qa0
Qa2 Qa3
Qb0 Qb1 Qb2 Qb3
t
RC
t
RC
= 10
(Burst length = 8)
Qa1
;;
;;;;;;;
;;;;;;;;
Ca0
/RAS latency = 2, /CAS latency = 5, Burst length = 8
ACT
READ
ACT
READ
;
Ra0
Ra0
Cb0
Rb0
Rb0
;
Qa4
Qa6 Qa7
Qa5
Qb4 Qb5
;;;;
;;;;;
;;;;
;;;;
;;;;;
;;;;;
;;;;
;;;;;
H
H
Hi-Z
Qb6
Data Sheet M13945EJ5V0DS
44
PD23C64202L
12.2.7 at 50 MHz (1-4-1-1-1)
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
;;
;;;;;;;
;;
;;
;;
;;
;;;;;
;;;;;
Ca0
/RAS latency = 1, /CAS latency = 4, Burst length = 4
READ
Ra0
Ra0
Rb0
Rc0
;;;;;
;;;;;
;;;;
;;;;
;;;;;
;;;;
;;;;;
;;;;
READ
READ
Rb0
;;
Cb0
;;
;;
Rc0 Cc0
t
RC
t
RC
= 4
(Burst length = 4)
3 clocks (MIN.) are
necessary between
READ and ACT
H
ACT
ACT
ACT
Qa0
Qa2
Qb3 Qc0 Qc1 Qc2
Qa1
Qb0
Qb2
Qb1
H
Hi-Z
Qa3
Qc3
12.2.8 at 50 MHz (1-4-1-1-1-1-1-1-1)
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
;;
;;;
;;;;;
;;
;;;
;;;;;
Ca0
/RAS latency = 1, /CAS latency = 4, Burst length = 8
Ra0
Ra0
Rb0
;;;;
;;;;
;;;;;
;;;;
;;;;;
;;;;
READ
Rb0 Cb0
t
RC
t
RC
= 8
(Burst length = 8)
H
Qa0
Qa2
Qb4 Qb5 Qb6 Qb7
Qa1
Qb0
Qb2 Qb3
Qb1
Qa4
Qa6
Qa5
Qa3
;;;;;
;;;;;
ACT
ACT READ
H
Hi-Z
Qa7
Data Sheet M13945EJ5V0DS
45
PD23C64202L
12.2.9 at 33 MHz (1-3-1-1-1)
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
Qa0
Qa2
Qa1
;;
;;;;;;;
;;
;;
;;
;;
;;;;;
;;;;;
Ca0
/RAS latency = 1, /CAS latency = 3, Burst length = 4
ACT
Ra0
Ra0
Rb0
Rc0
Qb0 Qb1
;;;;;
;;;;;
;;;;
;;;;
;;;;;
;;;;
;;;;;
;;;;
Ra0
;
Cb0
;
;
Rc0 Cc0
H
2 clocks (MIN.) are
necessary between
READ and ACT
READ
READ
ACT
READ
ACT
H
Hi-Z
t
RC
t
RC
= 3
(Burst length = 4)
Qb2 Qc0 Qc1 Qc2 Qc3
12.2.10 at 33 MHz (1-3-1-1-1)
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
;;
;;;;;;;
;;
;;;;;;;
Ca0
/RAS latency = 1, /CAS latency = 3, Burst length = 4
ACT READ
Ra0
Ra0
Rb0
Rc0
;;;;;
;;;;;
;;;;
;;;;
;;;;;
;;;;
;;;;;
;;;;
READ
READ
Rb0
;;
Cb0
;;
Rc0 Cc0
H
ACT
ACT
Qa0
Qa2 Qa3
Qc0 Qc1 Qc2 Qc3
Qa1
Qb0
Qb2 Qb3
Qb1
H
Hi-Z
Data Sheet M13945EJ5V0DS
46
PD23C64202L
12.2.11 at 33 MHz (1-3-1-1-1-1-1-1-1)
;;;;;
;;;;;
;;;;
;;;;
;;;;;
;;;;
;;;;;
;;;;
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
Qa0
Qa2
Qb4 Qb5 Ob6 Qb7
Qa1
;;
;;;
;;;;;
;;
;;
;;;
;;;
;;;;;
;;;;;
Ca0
/RAS latency = 1, /CAS latency = 3, Burst length = 8
READ
Ra0
Ra0
Rb0
Qb0
Qb2 Qb3
Qb1
READ
Rb0 Cb0
t
RC
t
RC
= 7
(Burst length = 8)
Qa4
Qa6
Qa5
Qa3
H
ACT
H
Hi-Z
ACT
12.2.12 at 33 MHz (1-3-1-1-1-1-1-1-1)
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
Qa0
Qa2
Qb4 Qb5 Qb6 Qb7
Qa1
;;
;;;
;;;;;
;;
;;;
;;;;;
Ca0
/RAS latency = 1, /CAS latency = 3, Burst length = 8
READ
Ra0
Ra0
Rb0
Qb0
Qb2 Qb3
Qb1
;;;;;
;;;;;
;;;;
;;;;
;;;;;
;;;;
;;;;;
;;;;
READ
Rb0 Cb0
Qa4
Qa6 Qa7
Qa5
Qa3
H
ACT
H
Hi-Z
ACT
Data Sheet M13945EJ5V0DS
47
PD23C64202L
12.3 Random Column Read Timing
12.3.1 at 100 MHz (2-5-1-1-1)
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
t
CCD
t
CCD
= 4
(Burst length = 4)
4 clocks (MIN.) are
necessary between
READ and READ
;;;;
;;;;;
;;;;
;;;;
;;;;;
;;;;;
;;;;
;;;;;
;;
;;;;;;;
;;;;;;;;
Ca0
/RAS latency = 2, /CAS latency = 5, Burst length = 4
ACT
READ
READ
;
Ra0
Ra0
Cc0
H
Cb0
H
Hi-Z
Qa0
Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qc0 Qc1 Qc2 Qc3
Qa1
READ
12.3.2 at 100 MHz (2-5-1-1-1-1-1-1-1)
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
Qb0 Qb1 Qb2 Ob3
t
CCD
t
CCD
= 8
(Burst length = 8)
;;;;
;;;;;
;;;;
;;;;
;;;;;
;;;;;
;;;;
;;;;;
;;
;;;;;;;
;;
;;;;
Ca0
/RAS latency = 2, /CAS latency = 5, Burst length = 8
ACT
READ
READ
;
Ra0
Ra0
H
Cb0
;;
Qb4 Qb5 Qb6
Qa0
Qa2 Qa3 Qa4 Qa5 Qa6 Qa7
Qa1
H
Hi-Z
Qb7
Data Sheet M13945EJ5V0DS
48
PD23C64202L
12.3.3 at 83 MHz (2-5-1-1-1)
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
t
CCD
t
CCD
= 4
(Burst length = 4)
4 clocks (MIN.) are
necessary between
READ and READ
;;;;
;;;;;
;;;;
;;;;
;;;;;
;;;;;
;;;;
;;;;;
;;
;;;;;;;
;;;;;;;;
Ca0
/RAS latency = 2, /CAS latency = 5, Burst length = 4
ACT
READ
READ
;
Ra0
Ra0
Cc0
H
Cb0
H
Hi-Z
Qa0
Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qc0 Qc1 Qc2 Qc3
Qa1
READ
12.3.4 at 83 MHz (2-5-1-1-1-1-1-1-1)
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
Qb0 Qb1 Qb2 Ob3
t
CCD
t
CCD
= 8
(Burst length = 8)
;;;;
;;;;;
;;;;
;;;;
;;;;;
;;;;;
;;;;
;;;;;
;;
;;;;;;;
;;
;;;;
Ca0
/RAS latency = 2, /CAS latency = 5, Burst length = 8
ACT
READ
READ
;
Ra0
Ra0
H
Cb0
;;
Qb4 Qb5 Qb6 Qb7
Qa0
Qa2 Qa3 Qa4 Qa5 Qa6 Qa7
Qa1
H
Hi-Z
Data Sheet M13945EJ5V0DS
49
PD23C64202L
12.3.5 at 66 MHz (2-5-1-1-1)
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
;;;;
;;;;;
;;;;
;;;;
;;;;;
;;;;;
;;;;
;;;;;
;;
;;;;;;;
;;;;;;;;
Ca0
/RAS latency = 2, /CAS latency = 5, Burst length = 4
ACT
READ
READ
;
Ra0
Ra0
Cc0
H
Cb0
H
Hi-Z
Qa0
Qa2
Qb0 Qb1
Qb3
Qc1 Qc2 Qc3
Qa1
READ
t
CCD
t
CCD
= 4
(Burst length = 4)
4 clocks (MIN.) are
necessary between
READ and READ
Qc0
Qa3
Qb2
12.3.6 at 66 MHz (2-5-1-1-1-1-1-1-1)
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
Qb0 Qb1 Qb2 Ob3
t
CCD
t
CCD
= 8
(Burst length = 8)
;;;;
;;;;;
;;;;
;;;;
;;;;;
;;;;;
;;;;
;;;;;
;;
;;;;;;;
;;
;;;;
Ca0
/RAS latency = 2, /CAS latency = 5, Burst length = 8
ACT
READ
READ
;
Ra0
Ra0
H
Cb0
;;
Qb4 Qb5 Qb6 Qb7
Qa0
Qa2 Qa3 Qa4 Qa5 Qa6
Qa1
H
Hi-Z
Qa7
Data Sheet M13945EJ5V0DS
50
PD23C64202L
12.3.7 at 50 MHz (1-4-1-1-1)
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
Qa0
Qa2 Qb0 Qb1 Qb2
Qa1
;;;;;
;;;;
;;;;;
;;;;;
;;;;
;;;;
;;;;;
;;;;
;;
;;;;;;;
;;
;;
;;
;;;;;
Ca0
/RAS latency = 1, /CAS latency = 4, Burst length = 4
ACT READ
READ
READ
Ra0
Ra0
Cc0
H
Cb0
t
CCD
t
CCD
= 3
(Burst length = 4)
3 clocks (MIN.) are
necessary between
READ and READ
Hi-Z
H
Qc0
Qc2 Qc3
Qc1
12.3.8 at 50 MHz (1-4-1-1-1)
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
;;;;;
;;;;
;;;;;
;;;;;
;;;;
;;;;
;;;;;
;;;;
;;
;;;;;;;
;;
;;
;;
;;;;;
Ca0
/RAS latency = 1, /CAS latency = 4, Burst length = 4
ACT READ
READ
READ
Ra0
Ra0
Cc0
H
Cb0
H
Hi-Z
Qa0
Qb0 Qb1
Qc0 Qc1 Qc2 Qc3
Qa1 Qa2 Qa3
Qb2 Qb3
Data Sheet M13945EJ5V0DS
51
PD23C64202L
12.3.9 at 50 MHz (1-4-1-1-1-1-1-1-1)
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
;;;;;
;;;;
;;;;;
;;;;;
;;;;
;;;;
;;;;;
;;;;
;;
;;;;;;;
;;
;;
;;;
;;;
;;;;;
;;;;;
Ca0
/RAS latency = 1, /CAS latency = 4, Burst length = 8
ACT READ
READ
Ra0
Ra0
H
Cb0
t
CCD
t
CCD
= 7
(Burst length = 8)
Hi-Z
H
Qa0
Qa2
Qa4 Qa5
Qb0 Qb1 Qb2 Qb3
Qa1
Qb4 Qb5 Qb6 Qb7
Qa3
Qa6
12.3.10 at 50 MHz (1-4-1-1-1-1-1-1-1)
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
Qa0
Qa2
Qa5 Qa6 Qa7 Qb0 Qb1 Qb2 Qb3
Qa1
;;;;;
;;;;
;;;;;
;;;;;
;;;;
;;;;
;;;;;
;;;;
;;
;;;;;;;
;;
;;;
;;;;;
Ca0
/RAS latency = 1, /CAS latency = 4, Burst length = 8
ACT READ
READ
Ra0
Ra0
H
Cb0
Qb4 Qb5 Qb6 Qb7
Qa3
Hi-Z
H
Qa4
Data Sheet M13945EJ5V0DS
52
PD23C64202L
12.3.11 at 33 MHz (1-3-1-1-1)
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
Qa0
Qb1 Qc0 Qc1 Qc2 Qc3
Qa1
;;;;;;
;;;
;;;;;;
;;;;;;
;;;
;;;
;;;;;;
;;;
;;
;;;;;;;
;;
;;
;
;;;;;;
Ca0
/RAS latency = 1, /CAS latency = 3, Burst length = 4
ACT READ
READ
READ
Ra0
Ra0
Cc0
H
Cb0
t
CCD
t
CCD
= 2
(Burst length = 4)
Qb0
2 clocks (MIN.) are
necessary between
READ and READ
H
Hi-Z
12.3.12 at 33 MHz (1-3-1-1-1)
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
Qa0
Qa2 Qa3
Qb1 Qb2 Qb3 Qc0 Qc1 Qc2 Qc3
Qa1
;;;;;
;;;;
;;;;;
;;;;;
;;;;
;;;;
;;;;;
;;;;
;;
;;;;;;;
;;
;;
;;
;;;;;
Ca0
/RAS latency = 1, /CAS latency = 3, Burst length = 4
ACT READ
READ
READ
Ra0
Ra0
Cc0
H
Cb0
Qb0
Hi-Z
H
Data Sheet M13945EJ5V0DS
53
PD23C64202L
12.3.13 at 33 MHz (1-3-1-1-1-1-1-1-1)
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
Qa0
Qa2 Qa3
Qa5 Qb0 Qb1 Qb2 Qb3
Qa1
;;;;
;;;;;
;;;;;
;;;;
;;;;
;;;;;
;;;;
;;
;;;;;;;
;;
;;;
;;;;;
Ca0
/RAS latency = 1, /CAS latency = 3, Burst length = 8
ACT READ
READ
Ra0
Ra0
H
Cb0
t
CCD
t
CCD
= 6
(Burst length = 8)
Qa4
Qb4 Qb5 Qb6 Qb7
Hi-Z
H
;;;;;
12.3.14 at 33 MHz (1-3-1-1-1-1-1-1-1)
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
;;;;;;;;
/WORD
OQ
Qa0
Qa2 Qa3
Qa5 Qa6 Qa7 Qb0 Qb1 Qb2 Qb3
Qa1
;;;;
;;;;;
;;;;;
;;;;
;;;;
;;;;;
;;;;
;;
;;;;;;;
;;
;;;
;;;;;
/RAS latency = 1, /CAS latency = 3, Burst length = 8
READ
H
Cb0
Qa4
Qb4 Qb5 Qb6 Qb7
;;;;;
H
Hi-Z
READ
Ra0
Ra0
ACT
Ca0
Data Sheet M13945EJ5V0DS
54
PD23C64202L
12.3.15 BURST STOP
CLK
CKE
/CS
/RAS
/CAS
/MR
A8 - A12
A0 - A7
Qa0
Qa3
Qb0 Qb1 Qb2 Qb3
Qa1
;;;
;;;;;;
;;;
;;;
;;;;;;
;;;;;;
;;;
;;;;;;
;;
;;;;;;;
;;;;;;;;
Ca0
/RAS latency = 2, Burst length = 8
ACT
READ
BST
READ
BST
;
Ra0
Ra0
Cb0
Hi-Z
Qa0
Qa2 Qa3
Qa1
OQ
(/CAS latency = 3)
Qb0
Qb2 Qb3
Qb1
Hi-Z
Hi-Z
Hi-Z
OQ
(/CAS latency = 4)
Note
Note
H
Qa2
Note Both standard and SDRAM-precharge-like types of the BURST STOP command can be used.
12.3.16 CLOCK SUSPEND and POWER DOWN
CLK
CKE
/RAS
/CAS
/MR
;;;;;
;;;;
;;;;;
;;;;
;;;;;;;;
;;;;;;;;
Col
/RAS latency = 2, /CAS latency = 5, Burst length = 4
;
Row
Row
Q0
Q2
Q3
Q1
/CS
Internal
CLK
;;;;;
;;;;
A8 - A12
ACT
READ
OQ
A0 - A7
POWER DOWN
entry
POWER DOWN
exit
CLOCK
SUSPEND
entry
CLOCK
SUSPEND
exit
POWER DOWN
CLOCK SUSPEND
H
Hi-Z
t
CKSP
D
a
ta S
heet M
13945E
J5V
0
D
S
55
PD23C64202L
ACT
CLK
/CAS latency = 3, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
Qa0
Qa1
Qa2
Qa3
READb
Qb0
Qb1
Qb2
Qb3
H
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
CLK
/CAS latency = 3, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
Qa0
Qa1
Qa2
Qa3
ACT
READb
Qb0
Qb1
Qb2
Qb3
H
12.4.2 ROW ACTIVATE - READ (2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
12.4.1 ROW ACTIVATE - READ (1)
12.4 Command Combination Examples
D
a
ta S
heet M
13945E
J5V
0
D
S
56
PD23C64202L
CLK
/CAS latency = 3, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
Qa0
Qa1
Qa2
Qa3
READb
Qb0
Qb1
Qb2
Qb3
H
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
CLK
/CAS latency = 3, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
Qa0
Qa1
Qa2
Qa3
ACT
READb
Qb0
Qb1
Qb2
Qb3
H
12.4.4 ROW ACTIVATE - READ (4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
12.4.3 ROW ACTIVATE - READ (3)
ACT
D
a
ta S
heet M
13945E
J5V
0
D
S
57
PD23C64202L
CLK
/CAS latency = 3, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
READb
H
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
CLK
/CAS latency = 3, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
Qa0
Qa1
Qa2
ACT
READb
Qa3
Qb1
Qb2
Qb3
H
12.4.6 ROW ACTIVATE - ROW ACTIVATE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
12.4.5 ROW ACTIVATE - READ (5)
ACT
ACT
Qb0
Qa0
Qa1
Qa2
Qb0
Qb1
Qb2
Qb3
D
a
ta S
heet M
13945E
J5V
0
D
S
58
PD23C64202L
CLK
/CAS latency = 3, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
CLK
/CAS latency = 3, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
Qa0
Qa1
Qa2
Qa3
H
12.4.8 READ - READ (2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
12.4.7 READ - READ (1)
Qa1
Qa2
Qa3
Qb1
Qb2
Qb3
READb
READb
Qb1
Qb2
Qb3
Qb0
Qa0
Qb0
D
a
ta S
heet M
13945E
J5V
0
D
S
59
PD23C64202L
CLK
/CAS latency = 3, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
12.4.9 READ - READ (3)
READb
Qa0
Qa1
Qb0
Qb1
Qb2
Qb3
D
a
ta S
heet M
13945E
J5V
0
D
S
60
PD23C64202L
CLK
/CAS latency = 3, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READ
Q0
Q1
Q2
Q3
H
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
CLK
/CAS latency = 3, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READ
Q0
Q1
Q2
Q3
H
12.4.11 READ SUSPEND (2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
12.4.10 READ SUSPEND (1)
D
a
ta S
heet M
13945E
J5V
0
D
S
61
PD23C64202L
CLK
/CAS latency = 3, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
Qb0
Qb1
H
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
CLK
/CAS latency = 3, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
Qa0
Qc0
Qc1
H
12.4.13 BURST STOP (2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
12.4.12 BURST STOP (1)
BST
ACT READb
BST
Qa0
ACT READb
BST
BST READc
Qc2
Qc3
Qb0
Qb1
D
a
ta S
heet M
13945E
J5V
0
D
S
62
PD23C64202L
CLK
/CAS latency = 3, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
CLK
/CAS latency = 3, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
12.4.15 POWER DOWN
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
12.4.14 CLOCK SUSPEND
ACT
ACT READb
Qa1
Qa2
Qa3
Qa0
READb
Qb1
Qb2
Qb3
Qb0
Qa0
Qa1
Qa2
Qa3
Qb1
Qb2
Qb3
Qb0
D
a
ta S
heet M
13945E
J5V
0
D
S
63
PD23C64202L
CLK
/CAS latency = 5, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
CLK
/CAS latency = 5, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
12.4.17 ROW ACTIVATE - READ (2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
12.4.16 ROW ACTIVATE - READ (1)
ACT
ACT
READb
Qa1
Qa2
Qa3
Qa0
READb
Qb1
Qb2
Qb3
Qb0
Qa0
Qa1
Qa2
Qa3
Qb1
Qb2
Qb3
Qb0
D
a
ta S
heet M
13945E
J5V
0
D
S
64
PD23C64202L
CLK
/CAS latency = 5, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
CLK
/CAS latency = 5, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
12.4.19 ROW ACTIVATE - READ (4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
12.4.18 ROW ACTIVATE - READ (3)
ACT
ACT
READb
Qa1
Qa2
Qa3
Qa0
READb
Qb1
Qb2
Qb3
Qb0
Qa0
Qa1
Qa2
Qa3
Qb1
Qb2
Qb3
Qb0
D
a
ta S
heet M
13945E
J5V
0
D
S
65
PD23C64202L
CLK
/CAS latency = 5, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
12.4.20 ROW ACTIVATE - READ (5)
ACT
Qa1
Qa2
Qa3
Qa0
READb
Qb1
Qb2
Qb3
Qb0
CLK
/CAS latency = 5, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
12.4.21 ROW ACTIVATE - ROW ACTIVATE
ACT
Qa1
Qa2
Qa3
Qa0
READb
Qb1
Qb2
Qb0
ACT
Qb3
D
a
ta S
heet M
13945E
J5V
0
D
S
66
PD23C64202L
CLK
/CAS latency = 5, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
12.4.22 READ - READ (1)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
Qa0
Qa1
Qa2
Qa3
Qb1
Qb2
Qb3
Qb0
READb
CLK
/CAS latency = 5, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
12.4.23 READ - READ (2)
Qa1
Qa2
Qa3
Qa0
READb
Qb1
Qb2
Qb3
Qb0
D
a
ta S
heet M
13945E
J5V
0
D
S
67
PD23C64202L
CLK
/CAS latency = 5, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
12.4.24 READ - READ (3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
Qa0
Qa1
Qa2
Qa3
Qb1
Qb2
Qb3
Qb0
READb
D
a
ta S
heet M
13945E
J5V
0
D
S
68
PD23C64202L
CLK
/CAS latency = 5, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READ
H
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
CLK
/CAS latency = 5, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READ
Q0
Q1
Q2
Q3
H
12.4.26 READ SUSPEND (2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
12.4.25 READ SUSPEND (1)
Q0
Q1
Q2
Q3
D
a
ta S
heet M
13945E
J5V
0
D
S
69
PD23C64202L
CLK
/CAS latency = 5, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
Qb0
Qb1
H
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
CLK
/CAS latency = 5, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
12.4.28 BURST STOP (2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
12.4.27 BURST STOP (1)
BST
ACT
READb
BST
Qa0
ACT
READb
BST
BST
READc
Qa0
Qc0
Qc1
Qc2
Qc3
Qb0
Qb1
D
a
ta S
heet M
13945E
J5V
0
D
S
70
PD23C64202L
CLK
/CAS latency = 5, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
CLK
/CAS latency = 5, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
12.4.30 POWER DOWN
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
12.4.29 CLOCK SUSPEND
ACT
ACT
READb
Qa1
Qa2
Qa3
Qa0
READb
Qb0
Qa0
Qa1
Qb1
Qb0
T26
T27
T26
T27
Qb1
Qb2
Qb3
Qb2
Qa2
Qa3
D
a
ta S
heet M
13945E
J5V
0
D
S
71
PD23C64202L
CLK
/CAS latency = 6, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
CLK
/CAS latency = 6, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
12.4.32 ROW ACTIVATE - READ (2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
12.4.31 ROW ACTIVATE - READ (1)
ACT
ACT
READb
Qa1
Qa2
Qa3
Qa0
READb
Qb1
Qb2
Qb0
Qa0
Qa1
Qa2
Qa3
Qb1
Qb2
Qb3
Qb0
D
a
ta S
heet M
13945E
J5V
0
D
S
72
PD23C64202L
CLK
/CAS latency = 6, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
CLK
/CAS latency = 6, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
12.4.34 ROW ACTIVATE - READ (4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
12.4.33 ROW ACTIVATE - READ (3)
ACT
ACT
READb
Qa1
Qa2
Qa3
Qa0
READb
Qb1
Qb2
Qb3
Qb0
Qa0
Qa1
Qa2
Qa3
Qb1
Qb2
Qb3
Qb0
D
a
ta S
heet M
13945E
J5V
0
D
S
73
PD23C64202L
CLK
/CAS latency = 6, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
12.4.35 ROW ACTIVATE - READ (5)
ACT
Qa1
Qa2
Qa3
Qa0
READb
Qb1
Qb2
Qb3
Qb0
CLK
/CAS latency = 6, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
12.4.36 ROW ACTIVATE - ROW ACTIVATE
ACT
Qa1
Qa2
Qa3
Qa0
READb
Qb1
Qb2
Qb0
ACT
D
a
ta S
heet M
13945E
J5V
0
D
S
74
PD23C64202L
CLK
/CAS latency = 6, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
12.4.37 READ - READ (1)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
Qa0
Qa1
Qa2
Qa3
Qb1
Qb2
Qb3
Qb 0
READb
CLK
/CAS latency = 6, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
12.4.38 READ - READ (2)
Qa1
Qa2
Qa3
Qa0
READb
Qb1
Qb2
Qb3
Qb0
D
a
ta S
heet M
13945E
J5V
0
D
S
75
PD23C64202L
CLK
/CAS latency = 6, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
12.4.39 READ - READ (3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
Qa0
Qa1
Qa2
Qa3
Qb1
Qb2
Qb3
Qb0
READb
D
a
ta S
heet M
13945E
J5V
0
D
S
76
PD23C64202L
CLK
/CAS latency = 6, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READ
H
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
CLK
/CAS latency = 6, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READ
Q0
Q1
Q2
Q3
H
12.4.41 READ SUSPEND (2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
12.4.40 READ SUSPEND (1)
Q0
Q1
Q2
Q3
D
a
ta S
heet M
13945E
J5V
0
D
S
77
PD23C64202L
CLK
/CAS latency = 6, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
Qb0
Qb1
H
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
CLK
/CAS latency = 6, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
12.4.43 BURST STOP (2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
12.4.42 BURST STOP (1)
BST
ACT
READb
BST
Qa0
ACT
READb
BST
BST
READc
Qa0
Qc0
Qc1
Qc2
Qc3
Qb0
Qb1
D
a
ta S
heet M
13945E
J5V
0
D
S
78
PD23C64202L
CLK
/CAS latency = 6, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
CLK
/CAS latency = 6, Burst length = 4
CKE
MRS
Command
/WORD
OQ
ACT
Hi-Z
H
READa
H
12.4.45 POWER DOWN
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
12.4.44 CLOCK SUSPEND
ACT
ACT
READb
Qa1
Qa2
Qa3
Qa0
READb
Qb0
Qa0
Qa1
Qb1
Qb0
T26
T27
T26
T27
Qb1
Qb3
Qb2
Qa2
Qa3
Data Sheet M13945EJ5V0DS
79
PD23C64202L
13. Package Drawing
M
86
44
1
43
S
P
C
N
S
B
M
D
L
K
J
L
S
G
E
F
detail of lead end
NOTES
1. Each lead centerline is located within 0.1 mm of
its true position (T.P.) at maximum material condition.
R
H
I
2. Dimension "A" does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
A
ITEM
B
C
I
86-PIN PLASTIC TSOP (
II
) (10.16 mm (400))
A
D
E
F
G
H
J
K
L
MILLIMETERS
0.5 (T.P.)
0.765 MAX.
10.16
0.10
22.22
0.05
0.10
0.05
0.22
1.1
0.1
11.76
0.20
1.00
+
0.06
-
0.04
0.80
0.20
0.145
+
0.025
-
0.015
0.50
0.1
M
N
P
0.10
3
+
5
-
3
0.25
R
S
0.60
0.15
S86G5-50-9JH1-1
Data Sheet M13945EJ5V0DS
80
PD23C64202L
14. Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of the
PD23C64202L.
Type of Surface Mount Device
PD23C64202LG5-9JH : 86-pin PLASTIC TSOP (II) (10.16 mm (400))
Data Sheet M13945EJ5V0DS
81
PD23C64202L
[ MEMO ]
Data Sheet M13945EJ5V0DS
82
PD23C64202L
[ MEMO ]
Data Sheet M13945EJ5V0DS
83
PD23C64202L
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
PD23C64202L
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
M8E 00. 4
The information in this document is current as of August, 2001. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special":
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
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